. LSI Logic - Index of

SDVD001. LSI LogicData Book1986~TEXASINSTRUMENTS

General InformationLSI DevicesApplication ReportsMechanical Data

LSI Logic Data BookTEXASINSTRUMENTS

IMPORTANT NOTICETexas Instruments (Til reserves the right to make changes in thedevices or the device specifications identified in this publicationwithout notice. TI advises its customers to obtain the latest versionof device specifications to verify, before placing orders, that theinformation being relied upon by the customer is current.TI warrants performance of its semiconductor products, including SNJand SMJ devices, to current specifications in accordance with TI'sstandard warranty. Testing and other quality control techniques areutilized to the extent TI deems such testing necessary to support thiswarranty. Unless mandated by government requirements, specifictesting of all parameters of each device is not necessarily performed.In the absence of written agreement to the contrary, TI assumes noliability for TI applications assistance, customer's product design, orinfringement of patents or copyrights of third parties by or arising fromuse of semiconductor devices described herein. Nor does TI warrantor represent that any license, either express or implied, is grantedunder any patent right, copyright, or other intellectual property rightof TI covering or relating to any combination, machine, or process inwhich such semiconductor devices might be or are used.Specifications contained in this data book supersede all data for theseproducts published by TI in the United States before November 1985.ISBN 0-89512-197-2Copyright © 1986. Texas Instruments Incorporated

INTRODUCTIONThe LSI Logic Data Book presents pertinent technical information on Texas Instruments complex bipolar, andCMOS LSI logic'integrated circuits. The bipolar LSI products described in this volume include:ooooThe fastest TTL-compatible 8-bit processor slice chip set available. The chip set includes an 8-bitregistered ALU, a 14-bit microsequencer, a 16- and 32-bit expandable barrel shifter, and a 16-wordby 4-bit register file.The fastest stand-alone 32-bit error detection and correction circuit (EDAC)High-performance 16 x 4 and 16 x 5 "zero-fCiIl-through" FIFOs (first in, first out) memory deviceswith 24-nanosecond fall-through timesA high-speed "flash" 32-bit barrel shifter (SN74AS8838). The SN74AS8838 is the first member ofthe Texas Instruments 32-bit processor chip set.Specifications on CMOS LSI products included in this volume describe the following:• The THCT1 01 0, which is the lowest power 16- x 16-bit multiplier and accumulator (MAC) available.ooTwo 64K and 256K DRAM controllers with inputs that are TTL- and CMOS-voltage compatible.Two high-speed CMOS multilevel pipeline registers, which offer a red'uction in power over previouslyavailable devices.To assist you in the selection of complex MSllogic components to complement a system design, the LSI LogicData Book contains specifications on high-performance bus transceivers, read back latches, comparators, andcontrollers.Many Texas Instruments leadership bipolar LSI functions use our new advanced bipolar technology, IMPACr"(IMPlanted Advanced Composed Technology). This unique innovation offers performance advantages in speed,power, and circuit density over preceding bipolar technologies. The process offers such features as:0 2-ftm feature size0 7-ftm metal pitch0 Walled emitters0 Ion implantation•Oxide isolation0 Composed masksThis data book provides a functional index to all bipolar digital device types available or under development.Packaging dimensions given in the Mechanical Data section of this book are in metric measurement (andparenthetically in inches), which should simplify board layout for designers involved in metric conversion andnew designs. The general information section includes an explanation. of the function tables, parametermeasurement information, and typical characteristics related to the products listed ,in this volume.Complete technical data for any Texas Instruments semiconductor/component product is available from yournearest TI field sales office, local authorized TI distributor, or by writing direct to:Texas Instruments IncorporatedP.O. Box 225012, MS 308Dallas, Texas 75265We sincerely believe that you will find the new LSI Logic Data Book a meaningful addition to your technical library .IMPACT is a trademark of Texas Instrumentsv

General InformationNumerical IndexGlossaryExplanation of Function TablesParameter Measurement InformationFunctional IndexLSI DevicesApplication ReportsAdvanced Schottky FamilyError Detection and CorrectionMemory MappingBit-Slice Processor 8-Bit FamilyExcerpt - SN74AS888, SN74AS890Bit-Slice Processor User's GuideMechanical Data1-1

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0 •••••••• 2-411NUMERICAL INDEXNUMERICAL INDEXSN54AS181A SN74AS181A ................ 2-3 SN54AS852 SN74AS852 . .............. 2-201SN54LS222 SN74LS222 ................. 2-13 SN54AS856 SN74AS856 ............... 2-207SN54LS224 SN74LS224 ................. 2-13 SN54AS867 SN74AS867 ............... 2-213SN74S225 .................. 2-21 SN54AS869 SN74AS869 ............... 2-213SN54LS227 SN74LS227 ................. 2-13 SN54AS870 SN74AS870 ............... 2-219SN54LS228 SN74LS228 ................. 2-13 SN54AS871 SN74AS871 ............... 2-219SN54ALS229A SN74ALS229A .............. 2-27 SN54AS877 SN74AS877 . .............. 2-225SN54ALS232A SN74ALS232A .............. 2-33 SN54AS881A SN74AS881A . ............... 2-3SN54ALS233A SN74ALS233A .............. 2-37 SN54AS882A SN74AS882A . ............. 2-231SN74AS250 ................ 2-43 SN54AS885 SN74AS885 . .............. 2-239 r::::SN54ALS280 SN74ALS280 ................ 2-47 SN54AS887 SN74AS887 ............... 2-245 0SN54AS280 SN74AS280 ,., ............. 2-47 SN54AS888 SN74AS888 . ......... " .... 2-293 ",tjSN54AS286 SN74AS286 ................ 2-53 SN54AS890 SN74·AS890 . .............. 2-343 COSN54LS610 SN74LS610 ................. 2-59 SN54AS895 SN74AS895 ............... 2-361 ESN54LS611 SN74LS611 ................. 2-59 SN54AS897A SN74AS897A •••••.......SN54LS612 SN74LS612 ................. 2-59 SN54ALS963 SN74ALS963 ............... 2-429 0SN54LS613 SN74LS613 ................. 2-59 SN54ALS964 SN74ALS964 ............... 2-429 r:::SN54ALS616 SN74ALS616 ................ 2-69 SN74ALS990 ....... > ••••••• 2-441SN54ALS617 SN74ALS617 ................ 2-69 SN74ALS991 ............... 2-441ctiSN54ALS632A SN74ALS632A ...... ........ 2-81 SN74ALS992 ............... 2-449 ...Q)2-457 r::::Q)SN54ALS634 SN74ALS634 ................ 2-81 SN74ALS995 ............... 2-457SN54AS634 SN74AS634 · ............... 2-97 SN74ALS996 ............... 2-465 (!JSN54AS632SN54ALS633SN74AS632 · ............... 2-97SN74ALS633 ................ 2-81SN74ALS993 ............... 2-449SN74ALS994 ...............SN54ALS635 SN74ALS635 ................ 2-81 SN54ASl181 SN74AS1181 .............. 2-471SN54ALS646 SN74ALS646 ............... ·2-111 SN54ALS2967 SN74ALS2967 .............. 2-483SN54AS646 SN74AS646 ............... 2-111 SN54ALS2968 SN74ALS2968 .............. 2-483SN54ALS647 SN74ALS647 ............... 2-111 SN54ALS6301 SN74ALS6301 .............. 2-503SN54ALS648 SN74ALS648 ............... 2-111 SN54ALS6302 SN74ALS6302 .............. 2-503SN54AS648 SN74AS648 ............... 2-111 SN74ALS8400 .............. 2-509SN54ALS649 SN74ALS649 ............... 2-111 SN54AS8834 SN74AS8834 .............. 2-513SN54ALS651 SN74ALS651 ........ _...... 2-125 SN54AS8838 SN74AS8838 .............. 2-523SN54AS651 SN74AS651 · .............. 2-125 SN54ALS29818 SN74ALS29818 ............. 2-533SN54ALS652 SN74ALS652 ............... 2-125 SN54ALS29819 SN74ALS29819 ............. 2-533SN54AS652 SN74AS652 ............... 2-125 SN54ALS29821 SN74ALS29821 ............. 2-545SN54ALS653 SN74ALS653 ............... 2-125 SN54ALS29822 SN74ALS29822 ............. 2-545SN54ALS654 SN74ALS654 ............... 2-125 SN54ALS29823 SN74ALS29823 ............. 2-551SN54ALS666 SN74ALS666 ............... 2-137 SN54ALS29824 SN74ALS29824 ............. 2-551SN54ALS667 SN74ALS667 ............... 2-137 SN54ALS29825 SN74ALS29825 ............. 2-559SN54AS821 SN74AS821 ............... 2-145 SN54ALS29826 SN74ALS29826 ............. 2-559SN54AS822 SN74AS822 ............... 2-145 SN54ALS29827 SN74ALS29827 ............. 2-565SN54AS823 SN74AS823 ............... 2-151 SN54ALS29828 SN74ALS29828 ............. 2-565SN54AS824 SN74AS824 ............... 2-151 SN54ALS29861 SN74ALS29861 ............. 2-571SN54AS825 SN74AS825 ............... 2-157 SN54ALS29862 SN74ALS29862 ............. 2-571SN54AS826 SN74AS826 ............... 2-157 SN54ALS29863 SN74ALS29863 ............. 2-577SN54ALS841 SN74ALS841 ............... 2-163 SN54ALS29864 SN74ALS29864 ............. 2-577SN54AS841 SN74AS841 ............... 2-163 THCt1 01 0-160M . ........................... 2-583SN54ALS842 SN74ALS842 ............... 2-163 THCTl010-100 ............. 2-583SN54AS842 SN74AS842 ............... 2-163 THCTl010-140E . . . . . . . . . . . . 2-583SN54ALS843 SN74ALS843 ............... 2-173 THCT2000M THCT2000E ................ 2-593SN54AS843 SN74AS843 , .............. 2-173 THCT4502 ................. 2-597SN54ALS844 SN74ALS844 ............... 2-173 THCT29520E ............... 2-613SN54AS844 SN74AS844 ............... 2-173 THCT29520 ................ 2-613SN54ALS845 SN74ALS845 ............... 2-181 THCT29521E ............... 2-613SN54AS845 SN74AS845 .............. . 2-181 THCT29521 ................ 2-613SN54ALS846 SN74ALS846 ............... 2-181 TMS2150 ................. 2-619SN54AS846 SN74AS846 ............... 2-181 TMS4500A . .......... , .... 2-627SN74AS850 ............... 2-191SN74AS851 ............... 2-191TEXAS ..INSTRUMENTSPOST OFFICE BOX 2250;2 • DALLAS. TExAS 752651-3

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GLOSSARYTTL SYMBOLS, TERMS, AND DEFINITIONSINTRODUCTIONThese symbols, terms, and definitions are in accordance with those currently agreed upon by the JEDEC Council of theElectronic Industries Association (EIA) for use in the USA and by the International Electrotechnical Commission (IEC)for international use.PART I -f maxICCICCHICClIIHIIIOPERATING CONDITIONS AND CHARACTERISTICS (IN SEQUENCE BY lETTER SYMBOLS)Maximum clock frequencyThe highest rate at which the clock input of a bistable circuit can be driven through its required sequencewhile maintaining stable transitions of logic level at the output with input conditions established that shouldcause changes of output logic level in accordance with the specification.Supply currentThe current into* the VCC supply terminal of an integrated circuit.Supply current, outputs highThe current into* the VCC supply terminal of an integrated circuit when all (or a specified number) of theoutputs are at the high level.Supply current, outputs lowThe current into* the VCC supply terminal of an integrated circuit when all (or a specified number) of theoutputs are at the low level.High-level input currentThe current into* an input when a high-level voltage is applied to that input.low-level input currentThe current into * an input when a low-level voltage is applied to that input.c:o"';::;COE .......oc:CO...Q)c:Q)~10H10llOS10ZHHigh-level output currentThe current into* an output with input conditions applied that, according to the product specification, willestablish a high level at the output.low-level output currentThe current into * an output with input conditions applied that, according to the product specification, willestablish a low level at the output.Short-circuit output currentThe current into* an output when that output is short-circuited to ground (or other specified potential) withinput conditions applied to establish the output logic level farthest from ground potential (or other specifiedpotential).Off-state (high-impedance-statel output current (of a three-state output I with high-level voltage appliedThe current flowing into* an output having three-state capability with input conditions established that,according to the product specification, will establish the high-impedance state at the output and with a highlevelvoltage applied to the output.NOTE: This parameter is measured with other input conditions established that would cause the output tobe at a low level if it were enabled.* Current out of a terminal is given as a negative value.TEXAS -1.!1INSTRUMENTSPOST O~FICE BOX 225012 • DAL.LAS, TEXAS 752651-5

GLOSSARYTTL SYMBOLS, TERMS, AND DEFINITIONSI::l....o...3Q):!'.o::l10ZlVIHVIKVilVOHVOLOff-state (high-impedance-state) output current (of a three-state output) with low-level voltage appliedThe current flowing into* an output having three-state capability with input conditions established that,.according to the product specification, will establish the high-impedance state at the output and with a lowlevelvoltage applied to the output.NOTE: This parameter is measured with other input conditions established that would cause the output tobe at a high level if it were enabled.High-level input voltageAn input voltage within the more positive (less negative) of the two ranges of values used to represent thebinary variables.NOTE: A minimum is specified that is the least-positive value of high-level input voltage for which operationof the logic element within specification limits is guaranteed.Input clamp voltageAn input voltage in a region of relatively low differential resistance that serves to limit the input voltage swing.low-level input voltageAn input voltage level within the less positive (more negative) of the two ranges of values used to representthe binary variables.NOTE: A maximum is specified that is the most-positive value of low-level input voltage for which operationof the logic element within specification limits is guaranteed.High-level output voltageThe voltage at an output terminal with input conditions applied that, according to the product specification,will establish a high 'Ievel at the output.low-level output voltageThe voltage at an output terminal with input conditions applied t~at, according to the product specification,will establish a low level at the output.tatdistenAccess time. The time interval between the application of a specified input pulse and the availability of valid signals atan output.Disable time (of a three-state or open-collector output)The propagation time between the specified reference points on the input and output voltage waveformswith the output changing from either of the defined active levels (high or low) to a high-impedance (off) state.NOTE: For 3-state outputs, tdis = tpHZ or tPlZ. Open-collector outputs will change only if they are lowat the time of disabling so tdis = tplH.Enable time (of a three-state or open-collector output)The propagation time between the specified reference points on the input and output voltage waveformswith the output changing from a high-impedance (off) state to either of the defined active levels (high or low).NOTE: In the case of memories, this is the access time from an enable input (e.g., (3). For 3-state outputs,ten = tpZH or tpZl. Open-collector outputs will change only if they are responding to data that wouldcause the output to go low so ten = tpHl.*Current out of a terminal is given as a negative value.1-6TEXAS -Ij}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

GLOSSARYTTL SYMBOLS, TERMS, AND DEFINITIONSthHold timeThe time interval during which a signal is retained at a specified input terminal after an active transition occursat another specified input terminal.NOTES: 1. The hold time is the actual time interval between two signal events and is determined by thesystem in which the digital circuit operates. A minimum value is specified that is the shortestinterval for which correct operation of the digital circuit is guaranteed.2. The hold time may have a negative value in which case the minimum limit defines the longestinterval (between the release of the signal and the active transition) for which correct operationof the digital circuit is guaranteed.Propagation delay timeThe time between the specified reference points on the input and output voltage waveforms with the outputchanging from one defined level (high or low) to the other defined level. (tDd = tpHL or tpLH).Propagation delay time. high-to-Iow-Ievel outputThe time between the specified reference points on the input and output voltage waveforms with the outputchanging from the defined high level to the defined low level.eo',tjCOElIIo.l+-oeDisable time (of a three-state output) from high levelThe time interval between the specified reference points on the input and output voltage waveforms with thethree-state output changing from the defined high level to a high-impedance (off) state.tPLHtPLZtpZHtpZLtsrtsuPropagation delay time. low-to-high-Ievel outputThe time between the specified reference points on the input and output voltage waveforms with the outputchanging from the defined low level to the defined high level.Disable time (of a three-state output) from low levelThe time interval between the specified reference points on the input and output voltage waveforms with thethree-state output changing from the defined low level to a high-impedance (off) state.Enable time (of a three-state output) to high levelThe time interval between the specified reference points on the input and output voltage waveforms with thethree-state output changing from a high-impedance (off) state to the defined high level.Enable time (of a three-state output) to low levelThe time interval between the specified reference points on the input and output voltage waveforms with thethree-state output changing from a high-impedance (off) state to the defined low level.Sense recovery timeThe time interval needed to switch a memory from a write mode to a read mode and to obtain valid datasignals at the output.Setup timeThe time interval between the application of a signal at a specified input terminal and a subsequent activetransition at another specified input terminal.NOTES: 1. The setup time is the actual time interval between two signal events and is determined by thesystem in which the digital circuit operates. A minimum value is specified that is the shortestinterval for which correct operation of the digital circuit is guaranteed.2. The setup time may have a negative value in which case the minimum limit defines the longestinterval (between the active transition and the application of the other signal) for which correctoperation of the digital circuit is guaranteed.twPulse duration (width)The time interval between specified reference points on the leading and trailing edges of the pulse waveform.TEXAS -1.11INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752651-7

GLOSSARYTTL SYMBOLS, TERMS, AND DEFINITIONSPART II -CLASSIFICATION OF CIRCUIT COMPLEXITYGate Equivalent CircuitA basic unit-of-measure of relative digital-circuit complexity. The number of gate equivalent circuits is that number ofindividual logic gates that would have to be interconnected to perform the same function.Ilarge-Scale Integration, lSIA concept whereby a complete major subsystem or system function is fabricated as a single microcircuit. In thiscontext a major subsystem or system, whether digital or linear, is considered to be one that contains 100 or moreequivalent gates or circuitry of similar complexity.Medium-Scale Integration, MSIA concept whereby a complete subsystem or system function is fabricated as a single microcircuit. The subsystem orsystem is smaller than for LSI, but whether digital or linear, is considered to be one that contains 12 or more equivalentgates or circuitry of similar complexity.Small-Scale Integration, SSIIntegrated circuits of less complexity than medium-scale integration (MSI).Very-large-Scale Integration, VlSIThe description of any IC technology that is much more complex than large-scale integration (LSI), and involves a muchhigher equivalent gate count. At this time an exact definition including a minimum gate count has not beenstandardized by JEDEC or the IEEE.1-8TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

EXPLANATION OF FUNCTION TABLESThe following symbols are used in function tables on TI data sheets:HLt4-("\XZa .. h0000OnJLLJTOGGLEhigh level (steady state)low level (steady state)transition from low to high leveltransition from high to low levelvalue/level or resulting value/level is routed to indicated destinationvalue/level is re·enteredirrelevant (any input, including transitions)off (high·impedance) state of a 3-state-outputthe level of steady-state' inputs at inputs A through H respectivelylevel of 0 before the indicated steady-state input conditions were establishedcomplement of 00 or level of Q before the indicated steady-state input conditions were establishedlevel of 0 before the most recent active transition indicated by 4- or tone high-level pulseone low-level pulseeach output changes to the complement of its previous level on each active transition indicated by4- or t.IIc::o.~COE .........os::(ij....Q)s:::Q)C!JIf, in the input columns, a row contains only the symbols H, L; and/or X, this means the indicated output is valid wheneverthe input configuration is achieved and regardless of the sequence in which it is achieved. The output persists solong as the input configuration is maintained.If, in the input columns, a row contains H, L, and/or X together with t and/or 4-, this means the output is valid wheneverthe input configuration is achieved but the transition(s) must occur following the achievement of the steady-statelevels. If the output is shown as a level (H, L, 00, or 00), it persists so long as the steady-state input levels and thelevels that terminate indicated transitions are maintained. Unless otherwise indicated, input transitions in the oppositedirection to those shown have no effect at the output. (If the output is shown as a pulse,rL or u-: the pulsefollows the indicated input transition and persists for an interval dependent on the circuit.)TEXAS l!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752651-9

EXPLANATION OF FUNCTION TABLESAmong the most complex function tables in this book are those of the shift registers. These embody most of thesymbols used in any of the function tables, plus more. Below is the function table of a 4·bit bidirectional universalshift register, e.g., type SN74194.IG)CD::JCD...~::J-ho...INPUTSFUNCTION TABLEOUTPUTSMODE SERIAL PARALLELCLEAR - CLOCK aA aB ac aDSl SO LEFT RIGHT A B C 0L X X X X X X X X X L L L LH X X L X X X X X X QAO QSO QCO QOOH H H t X X a b c d a b c dH L H t X H X X X X H QAn QSn QCnH L H t X L X X X X L QAn QS n °CnH H L t H X X X X X QS n QCn QOn HH H L 1 L X X X X X QSn QCn QO n LH L L X X X X X X X QAO QSO QCO 0003! The first line of the table represents a synchronous clearing of the register and says that if clear is low, all four outputs0' will be reset low regardless of the other inputs. In the following lines, clear is inactive (high) and so has no effect.::JThe second line shows that so long as the clock input remains low (while clear is high), no other input has any effectand the outputs maintain the levels they assumed before the steady·state combination of clear high and clock low wasestablished. Since on other lines of the table only the rising transition of the clock is shown to be active, the second lineimplicitly shows that no further change in the outputs will occur while the clock remains high or on the high·to·lowtransition of the clock.The third line of the table represents synchronous parallel loading of the register and says that if S1 and SO are bothhigh then, without regard to the serial input, the data entered at A will be at output OA, data entered at B will be atOB, and so forth, following a low·to·high clock transition. .The fourth and fifth lines represent the loading of high· and low·level data, respectively, from the shift·right serial inputand the shifting of previously entered data one bit; data previously at 0A is now at OB, the previous levels of OB andOc are now at Oc and OD respectively, and the data previously at OD is no longer in the register. This entry of serialdata and shift takes place on the low·to·high transition of the clock when S1 is low and SO is high and the levels atinputs A through D have np effect.The sixth and seventh lines represent the loading of high· and low·level data, respectively, from the shift·left serial inputand the shifting of previously entered data one bit; data previously at 0B is now at OA, the previous levels of Oc and0D are now at OB and OC, respectively, and the data previously at OA is no longer in the register. This entry of serialdata and shift takes place on the low·to·high transition of the clock when S1 is high and SO is low and the levels atinputs A through D have no effect.The last line shows that as long as both mode inputs are low, no other input has any effect and, as in the second line,the outputs maintain the levels they assumed before the steady·state combination of clear high and both mode inputslow was established.1·10TEXAS ..INSTRUMENTS/lOST OHICS BOX ~2~a1a , CAbLM, nXM 7&~69

SERIES 54ALS/74ALS AND 54AS/74AS DEVICESPARAMETER MEASUREMENT INFORMATION7VVCC ~ RL = R1 = R2SlL~FROM OUTPUT;q- TEST FROM OUTPUT TESTUNDER TESTPOINTUNDER TEST POINT R1CL RL FROM OUTPUT TEST(See Note A) CL ---UNDER TEST ---41~---41~---41~- POINT'''', NOhAITCL R2(See Note A)LOAD CIRCUIT FORBI·STATETOTEM·POLE OUTPUTSNOTE A: CL includes probe and jig capacitance.TIMINGINPUT/>.3 V,- - - - - - -- 0.3 V~ tsu ....-th ~LOAD CIRCUIT FOROPEN·COLLECTOR OUTPUTS3.5V~3.5VDATAINPUT 1.3 V 1.3 V0.3VLOAD CIRCUIT FORTHREE·STATE OUTPUTSHIGH·LEVEL~ 3.5VPULSE I II I 0.3 V4-- tw -----.3.5 VLOW·LEVEL' 1 .3V1.3V ____PULSE 0.3Vc:o"';:COE~'to-oc:C6~Q)c:Q)(!)VOL TAGE WAVEFORMSSETUP AND HOLD TIMESVOL TAGE WAVEFORMSPULSE WIDTHSINPUT ~~.;V-- - 3.5V-/: I..>V .~ 0.3V~tPLH" j.tPHL"IN.PHASE~:I-:-- VOHOUTPUT : 1.3 V : 1.3 V, : VOLj4tPHL'"~tpLH'"OUT -OF·PHASE ~ 1 ., \I l/.:': VOHOUTPUT ~~.~V(See Note D) - - - VOLVOLTAGE WAVEFORMSPROPAGATION DELAY TIMESOUTPUTCONTROL 1.3 V 1.3 V3.5 V(low·level I -:-- - - ---- 0.3 Venabling) tpZL ___tel --tI It- tPLZI I I'I I I : '" 3.5 VWAVEFORM 1 --y\! 1.3 V i :~3 V1 --~~_LvSl CLOSED i ~.-------------=--=-!:iII.==-~= VOL(See Note B) tpZH -l..I I TWAVEFORM 2 I ----"l-- OHSl OPEN 1.3 V 0.3 V(See Note B)"'0 VVOLTAGE WAVEFORMSENABLE AND DISABLE TIMES, THREE·STATE OUTPUTSNOTES:B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.C. Ail input pulses have the following characteristics: PRR :$ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.D. When measuring propagation delay times of 3·state outputs, switch S 1 is closed.TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752651-11

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FUNCTIONAL INDEXGATES AND INVERTERSPOSITIVE-NAND GATES AND INVERTERSTECHNOLOGYSTDDESCRIPTIONTYPE ALS AS H L LS S VOLUMETTLHex 2-lnput Gates '804'04Hex Inverters'1004'00Quadruple 2-lnput Gates'1000'10Triple 3-lnpul GatesA'1010 A'20Dual4-lnput Gates'10208-lnput Gates '30A13-lnpul Gates '133DESCR;PTIONPOSITIVE-AND GATES WITH OPEN-COLLECTOR OUTPUTSTyrEQuadruple 2-lnput Gates '09Triple 3-lnput Gates '15DESCRIPTIONSTDTTLPOSITIVE-OR GATESHex 2-lnput Gates '832Quadruple 2-lnpul GatesTECHNOLOGYALS AS H LS S VOLUMETECHNOLOGYSTDTYPE ALS AS LS S VOLUMETTL'1032r,:;;Ple 4-lnpu! ORINOR '802 .a.POSITIVE-NOR GATES'32 t--'---+-+--+--=--t--=--t---==-----,-jt:o'';:;caE....~ot:Dual 2-lnput Gates '8003POSITIVE-NAND GATES AND INVERTERS WITH OPEN-COLLECTOR OUTPUTSDESCRIPTIONHex InvertersTECHNOLOGYSTDTYPE ALS AS H L LS S VOLUMETTL'05 i----=-+---:--I-+-=++-=--+--=-il-~---i'1005'01 1-+-::--1-+-+--+---=-+-11---"--1DESCRIPTIONTYPEHex 2-lnput Gates '805'02Quadruple 2-lnflut Gates'1002Triple. 3-lnput Gates '27Dual 4-lnpul Gates with Strobe , 25Dual 5-lnput Gates '260STDTTLTECHNOLOGYALS AS L LS S VOLUMEQuadruple 2-Input GatesTriple 3-lnput GatesDual 4-lnput GatesDESCRIPTIONHex 2~lnput Gates'03B'1003 A'12A'22POSITIVE-AND GATESTECHNOLOGYSTDTYPEALS AS H LS S VOLUMETTL'80SDESCRIPTIONHex InvertersSCHMITT-TRIGGER POSITIVE-NAND GATES AND INVERTERSTECHNOLOGYSTDTYPE TTL ALS AS LS S VOLUME'14 •'19Octal Inverters '619Dual 4-lnput POSItive-NANDTriple 4-lnput Positive-NANDQuadruple 2-lnput Positive-NAND'13 •'18'61S'24'132 •Quadruple 2-tnput Gates'08CURRENT-SENSING GATES.'1008Triple 3-lnput Gates'11'lOllADESCRIPTIONHexDual 4-lnput Gates'21DELAY ELEMENTSTriple 4-lnput ANDINAND'800DESCRIPTIONInverting and Noninverting Elements,2-lnput NAND Buffers• Denotes available technology,.6. Denotes planned new products,A Denotes" A" suffix version available in the technology indicated,8 Denotes "8" suffix version availab!e in the technology indicated,. TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752651-13

FUNCTIONAL INDEXGATES, EXPANDERS, BUFFERS, DRIVERS, AND TRANSCEIVERS::::J.....o""t3D)r+0"::::JDESCRIPTIONAND·OR·INVERT GATESTYPE2-Wide 4-lnput ·554-Wide 4-2-3-2 Input '644-Wide 2-2-3-2 Input '544-Wide 2-lnput '544-Wide 2-3-3-2 Input '54Dual 2-Wide 2-lnput '51DESCRIPTION4-Wide 4-2-3-2 InputDESCRIPTIONSTDTTLTECHNOLOGYALS AS H L LS S VOLUMEAND·DR·INVERT GATES WITH OPEN·COLLECTOR OUTPUTSDual 4-lnput Positive-NORwith StrobeEXPANDABLE GATESTYPE'234-Wide AND·OR '524-Wide AND·OR-INVERT '532-Wide AND-OR-INVERT '55Dual 2-Wide AND-DR-INVERT '50DESCRIPTIONSTDTTLEXPANDERSDual 4-lnput '60Triple 3-lnput '613-2-2-3 Input AND-OR '62TECHNOLOGYALS AS H L LS VOLUMETECHNOLOGYSTDTYPEALS ASTTLHVOLUMEDESCRIPTIONHexBUFFER AND INTERFACE GATES WITH OPEN-COLLECTOR OUTPUTSTECHNOLOGYSTDTYPE ALS AS LS S VOLUMETTL'07 •'17 •'35'1035'06 •Hex Inverter '16 •Quad 2-lnput Positive-NANDQuad 2-lnput Positive-NOR'1005'26 •'38 1---+--+--+--+-+-.,.--1'39 •'1003'33 I---+--+--+--+-+-~-IBUFFERS, DRIVERS, AND BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTSDESCRIPTIONNoninvertingOctal Buffers/DriversInverting OctalBuffers/DriversInverting and NoninvertingOctal Buffers/DriversNoninverting Quad TransceiversInverting Ouad TransceiversTECHNOLOGYTYPE STD ALS AS LS S VOLUMETTL'743'757'760'742'756'763'762'759'758• Denotes available technology,.Denotes planned new products.A Denotes "A" suffix version available in the technology indicated.1-14 TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TeXAS 75265

FUNCTIONAL INDEXGATES, EXPANDERS, BUFFERS, DRIVERS, AND TRANSCEIVERSGATES, BUFFERS, DRIVERS, AND BUS TRANSCEIVERS50-0HM/75-0HM LINE DRIVERSWITH 3-STATE OUTPUTSTECHNOLOGYDESCRIPTIONTYPENoninverting 10-Bit Buffers/Drivers '29827Inverting 10-Bit Buffers/Drivers '29828Noninverting 1 O-Bit Transceivers '29861Inverting 10-Blt Transceivers '29862Nonmvertmg 9-81t Transceivers '29863Inverting 9-8it Transceivers '29864NoninvertingOctal Buffers/Drivers'241'244'465'467TECHNOLOGYSTDTTlALS AS LS......AAAASVOLUMELSIDESCRIPTIONHex 2-lnput Positive-NANDHex 2-lnput Positive-NORHex 2-lnput Positive-ANDHex 2-lnput Positive-ORQuad 2-lnput Positive-NORDual 4-lnput Positive-NANDSTDTYPE ALS AS S VOLUMETTL'804 A'805'808 A'832'128c:'140o",tjnlE'ō....c:'541'1241 ~'1244~'231A'240Inverting OctalBuffers/Drivers'466'468'540'1240'Inverting and NoninvertlngOctal BufferslDrivers'230Octal Transceivers'245'1245Noninverting'365.AHex BufferslDrivers'367·23InvertingHex Buffers/DriversQuad Buffers/DriversI with IndependentOutput Controls'366'368'125'126'425'426AANoninverting '243Quad Transceivers'12431-AInverting '242Quad Transceivers'1242'Quad Transceivers with Storage '22612-lnput NAND Gate '134• Denotes available technology.A. Denotes planned new products_f Denotes very low power.A Denotes" A" suffix version available in the technology indicated.8 Denotes "8" suffix version available in the technology indicated.. TEXAS.INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752651-15

FUNCTIONAL. INDEXBUFFERS, DRIVERS, TRANSCEIVERS, AND CLOCK GENERATORSBUFFERS, CLOCK/MEMORY DRIVERSOCTAL BHTRI,DlRECTIONAL BUS TRANSCEIVERSTECHNOLOGYG)CD::l(t)""I~::l...0""I3Q)r+o·::lDESCRIPTIONTYPEHex 2-lnput Positive-NAND '804Hex 2-lnput Positive-NOR '805Hex 2-lnput Positive-AND '808Hex 2-lnput Positive-OR '832Hex Inverter '1004Hex BufferQuad 2-lnput Positive-NANDQuad 2-lnput Positive-NOR'34'1034'37STDTTLALS AS H LS S VOLUMEA'1000 A'28A'1002 A'1036Quad 2-lnput Positive-AND '1008 AQuad 2-1nput Positive-OR '1032 ATriple 3-lnput Positive-NAND '1010Triple 3-lnput Positive-AND '1011Triple 4-lnput AND-NAND '800 ....Triple 4-lnput OR-NOR '802Dual 4-lnput Positive-NAND'40A'1020 ADESCRIPTION, 2 mA;24 rnA 48 rnA, 64 rnASmk, True Outputs12 mA/24 mA'48 rnA 64 rnASmk, Invertln9 OutputsVery LowOF, OUTPUT'245DCOC, 3 StaleOC,3-$tate '654OC, 3 State '163933tateOC '622DC, 3 StateALS3 & LSI3 & LSIline Driver/Memory Driverwith Series Damping Resistor'436OC,3·Stateline Driver/Memory Driver '437Very LowBI-/TRI-DIRECTIONAL BUS TRANSCEIVERS AND DRIVERS -OC, 3·Stat~DESCRIPTIONTYPEOFOUTPUTQuad with Bit Direction 3-State '446Controls 3-State '449Ouad TridirectionOC '440OC '4413-State '4423-5tate '4433-5tate '444OC '4484-8it with Storage 3-State '226TECHNOLOGYTYPE ALS AS LS S VOLUME12 mA,24 mAI48 rnA 64 rnASink. True Outputs12 mA'24 rnA 48 rnA/64 rnASmk, Inverting OutputsVery low OC '16413·$tate3 StateVery Low 3 StateOCTAL BUS TRANSCEIVERS/MOS DRIVERS, 2 mAi24 mA'48 rnA'64 rnATECHNOLOGYSTDDESCRIPTION TYPE ALS AS LS S VOLUMETTL'2620Inverting Outputs, 3-5tate'2640'2623True Outputs, 3-5tate'2645OCTAL BUFFERS AND LINE DRIVERS WITH INPUT/OUTPUT RESISTORSTECHNOLOGYSTDDESCRIPTION TYPE ALS AS LS S VOLUMETTL'746'747'2540'2541Smk, True andInvertmg OutputsVery lowRegistered with Multiplex 3-$tate '64612 mA!24 mA!48 rnA'64 rnATrue OutPutsRegistered with Multiplexed 3·State '64812 mAI24 mA'48 rnA:64 rnAInverting OutputsOCUniversal Transceiverl3-$tate '852Port Controllers3 & lSI3 & LSI3 & LSI3 & LSI• Denotes available technology,... Denotes planned new products,A Denotes "A" suffix version available in the technology indicated,8 Denotes "8" suffix version available in the technology indicated,1-16 TEXAS -I/}INSTRUMENTSPOST OFFICE aOX 225012 • DALLAS, TExAS 75265

FUNCTIONAL INDEXFLIP-FLOPSDUAL AND SINGLE FLIP-FLOPSQUAO ANO HEX FLIP-FLOPSTECHNOLOGYTECHNOLOGYSTDNO, OFSTDDESCRIPTIONTYPEALS AS H L LS S VOLUME DESCRIPTIONOUTPUTS TYPE ALS AS LS S VOLUMETTLFFsTTL'73· ·A'174'76 A'78 A '378'103 D Type '171'1060, Q '175 c:'1070Dual J-K Edge-Triggered '108 '379'276 ".t='109 J,K Q'376 COA'112EA OCTAL, 9-BIT, AND 10-BIT D-TYPE FLIP-FLOPS'-A 0'113A .a.·TECHNOLOGY'to-NO, OFSTDA DESCRIPTIONOUTPUT TYPE ALS AS LS S VOLUME c:'114BITSTTL.a.'70True DataOctalSingle J-K Edge-Triggered '101Dual Pulse-TnggeredSingle Pulse-TriggeredDuat J-K with DatalockoutSingle J·K with DataLockout'102'73'76'78'107'71'72'104'105'111'110DualO-Type '74· · ·AInvertingTrue Data wIth ClearTrue with EnableInvertingInverting with ClearInverting with PresetTrueTrueInvertingTrueInvertingTrueInvertingTrueInvertingTrueInvertingOctalOctalOctalOctalOctalOctalOctal9·Blt9-81t10-81t10-8,tOctalOctal9-Bit9-Bit1O-8,t10-8,t3-$tate '374(ij3-$tate '574 '- Q)2-5tate '273 c:Q)3-5tate '5753-5tate '874CJ3-5tate '8782·$tate '3773-$tate '5343-$tate '5643-5tate '5763-$tate '5773-$tate '8793-5tate '8763-5tate '8253-$tate '8263-5tate '8233-5tate '8243-5tate '8213-5tate '8223-$tate '29825 .a.3-$tate '29826 .a.3-State '29823 .a.3-State '29824 .a.3-State '29821 .a.3-State '29822 .a.3 & LSI• Denotes available technology,.... Denotes planned new products,A Denotes" A" suffix version available in the technology indicated,B Denotes "S" suffix version available in the technology indicated,TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 .-DALLAS, TEXAS 752651-17

FUNCTIONAL INDEXLATCHES AND MUL TIVIBRATORSG)CD:::sCD.,~:::s~., o3Q),...0":::sDESCRIPTIONDual2-BltTransparentQUAD LATCHESOUTPUTTYPE2-Stat. '752-5tate '772-Stat. '3752-Stat. '279STDTTLTECHNOLOGYALS AS LRETRIGGERABLE MONOSTABLE MULTIVIBRATORSTECHNOLOGYSTDDESCRIPTION TYPE TIL ALS AS LS L VOLUME'122Single '130OualDESCRIPTIONEdge-Triggered Invertingand NoninvertingTransparent TrueTransparent NoninvertingTransparent with ClearTrue OutputsTransparent with ClearInverting Outputs'422'123'423D-TYPEOCTAL, 9-BIT, AND 10-BIT READ-BACK LATCHESNO, OFBITSOctalTYPE'996LSVOLUMETECHNOLOGYSTDALSAS LS S VOLUMETILAOctal9-Bit10-Blt'990'992'994Octal '991~:'::'::::~""::':~--+--=-+--I--+---1 3 & LSI9-Blt '99210-Bit '994Octal '666Octal '667DESCRIPTIONTransparentOCTAL, 9-BIT, AND 10-BIT LATCHESNO, OFOUTPUTBITSOctal'2683-5tate '3733-Stat. '5732-Stat. '100Oual4·BitOctal 2-Stat. '116Transparent3-Stat. 'B733-Stat. '533Inverting Transparent Octal 3-5tate '563 A3-5tate '580 ADual4-Bit3-5tate 'B80 AOctalInverting Transparent3-Stat. '604OC '60S2-lnput Multiplexed Octal3-Stat. '606OC '607Addressable Octal 2-5tate '259Multi-Mode Buffered Octal 3-5tate '412True Octal 3-Stat. 'B45Inverting Octal 3-Stat. 'B46 ATrue 9-Bit 3-Stat. 'B43Inverting 9-Bit 3-Stat. 'B44True 10-Bit 3-5tate 'B41Inverting 10-Bit 3-5tate 'B42TECHNOLOGYSTDTYPE ALS AS LS S VOLUMETTLMONOSTABLE MULTIVIBRATORS WITH SCHMITI-TRIGGER INPUTSTECHNOLOGYDESCRIPTION TYPE ~~~ IALSIASILSI S I LSingle '121 • T T T I I·Dual '221 • I I I· I I3 & LSIVOLUME2• Denotes available technology,A Denotes planned new products,A Denotes" A" suffix version available in the technology indicated,8 Denotes "8" suffix version available in the technology indicated,1-18 TEXAS ~INSTRUMENTSPOST OFFICE BOX 22501~ • bAL.~AS. TEltAS 15265

FUNCTIONAL INDEXREGISTERSSHIFT REGISTERSSIGN~PROTECTED REGISTERSTECHNOLOGYALS AS L S VOLUMe:DESCRIPTIONSign-ProtectedSign-Protected RegisterParallel-In.Parallel-Out,Parallel-In,Parallel-Out,RegisteredOutputsParallel-In,x XX X X X '671X X X X '672'199'96'95'178'179'195'295'299 1---+--+--t--t-'-+-+----1'323 I---+--+--t--t-'-+-+---=--IDESCRIPTION8 Words X 2 Bits4 Words x 4 BitsDual 16 Words x 4 Bits64 Words X 40 BitsDESCRIPTIONQuadruple Multiplexerswith StorageOUTPUTTYPETECHNOLOGYSTDVOLUME c:ALS AS LSTTl 03-5tate '172 "';:;oc '170CO3-5tate '6703-5tate '8703 & LSI ...3-5tate '8713-5tate '8834 ... LSIOTHER REGISTERSE0c:'PoC6...TECHNOLOGYSTDVOLUMETYPEALS AS L LS STTl Q)'98 c:'298'398Q)(!J'3998·Bit Universal ShiftRegisters'299...Quadruple Bus·BufferRegisters'173Parallel-In.Serial-OutOctal Storage RegisterDual·Rank a-BitShIft Registers8·Bit DiagnosticsJPipeline Registers'396'963 ...'964 ...3 & LSI'29818 ...'29819 ...SeTial-ln,SHIFT REGISTERS WITH LATCHESNO,TECHNOLOGYDESCRIPTION OF OUTPUTS TYPE VOLUMEALS AS LSBITSParallel-In. Parallel-Out3~State '671with Output Latches3~State '672162~State '673Serial~ln, Parallel~OutBuffered '594with Output latches3~State '595oc '596OC '599Parallel-In, Serial·Out.2~State '597with Input Latches3~State '589Parallel 1/0 Ports withInput Latches, Multiplexed3~State '596Serial Inputs• Denotes available technology,A Denotes planned new products,A Denotes" A" suffix version available in the technology indicated,S Denotes "S" suffix version available'in the technology indicated,TEXAS ."INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752651-19

FUNCTIONAL INDEXCOUNTERSSYNCHRONOUS COUNTERS -POSITIVE-EOGE TRIGGEREDASYNCHRONOUS COUNTERS IRIPPLE CLOCK I -NEGATIVE-EDGE TRIGGEREDG)CD:sCD""l~:s ....0""l3Q)r+0":s.PARALLELDESCRIPTIONTYPEUlADSync '160Sync '162DecadeSync '560Sync '668Sync '690Sync '692Sync '168Async '190Decade Up/DownAsync '192Sync '568Sync '696Sync '698AsyncDecade Rate 1'167Multipler, Nl0 Set-to-9Sync '161Sync '1634-Bit BinarySync '561STDTTlTECHNOLOGYVOLUMEALS AS L LS S·A·B.·ATECHNOLOGYPARALLELDESCRIPTIONTYPE STDLOADALS AS L LS STTL5et-to-9 '90'68Decade Yes '176Yes '196Set-to-9 '290None '93'694-8it Binary Yes '177Yes '197None '293Dlvlde-by-12 None -92None '390Dual Decade5et-to-9 '490Dual 4- Bit Binary None '3938-BIT BINARY COUNTERS WITH REGISTERSTYPETECHNOLOGYOF TYPEDESCRIPTIONALS AS LSOUTPUTParallel Register 3-State '590Outputs OC '591Parallel Register Inputs 2-State '592Parallell/Q 3-State '593VOLUMEVOLUMESync '669Sync '691Sync '693Sync '169Async '1914-Bit BinaryUp/Down Async '1938·FREQUENCY DIVIDERS, RATE MULTIPLIERSTECHNOLOGYTYPE STDDESCRIPTIONALS AS LSTTl50-to-1 Frequency Divider '5660-to-1 Frequency Divider '5750-Bit Binary Rate Multiplier '97Decade Rate Multiplier '167VOLUMESync '569Sync '697Sync '6996-Bit Binary 1Rate Multipler,S-Bit Up!OownN2'97Async CLR '867Sync CLR 'S693 & LSI• Denotes available technology_A Denotes" A" suffix version available in the technology indicated.8 Denotes "8" suffix version available in the technology indicated,1-20 TEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

FUNCTIONAL INDEXDECODERS, ENCODERS, DATA SELECTORS/MULTIPLEXERS AND SHIFTERSDATA ~ELECTDRS/MULTIPLEXERSDECODERS/DEMULTIPLEXERSTYPE TECHNOLOGY TYPE TECHNOLOGYDESCRIPTION OF TYPE STDVOLUME DESCRIPTION OF TYPE STDALS AS L LS SALS AS L LSOUTPUT TTL OUTPUT TTL2-5tate '150 . 3-5tate '1544-to-16·S3-State '250 OC '15916-to-l3-5tate '850 3 & LSI 4-to- 10 BCD-to-Decimal 2-5tate '42 A3-5tate '851 4-to-10 Excess 3-to-2-State '43 ADuaI8-to-' 3-5tate '351 . DeCimal4-to-10 Excess 3-Grayto-Decimal2-5tate '1512-5tate '44 A2-5tate '152 A'131 ...3-to-8 with AddressA-8-to-l3-5tate '251A-Latches2-5tate '1373-5tate '354 A-2-5tate '355 3-to-82-5tate '138DuaI4-to-'3-5tate '356 3-5tate '538 ...OC '357 ...2-5tate '1392-5tate '153 Dual 2-to-43-5tate '2532-State '3522-5tate '155·OC '156·Dual 1-to-4 Decoders 3-State '539 A-CODE CONVERTERS3-5tate '353 TECHNOLOGY3-5tate '604DESCRIPTION TYPE STDTTLOC '605Octal 2-to-' with Storage3-$tate '6066-line-BCD to 6-line Binary, or 4-Llne to 4-Line'184BCD 9'5/8CO 10's ConvertersOC '6076-Bit-Binary to 6-Bit BCD Converters '1852-5tate '98BCD-to-Binary Converters '484 AQuad 2-to-1 with Storage2-State '298 Binary-to-BCD Converters '485Quad 2-to-l6-to-1 UniversalMultiplexer2-State '3982-State '3992-State '1572-State '1583-State '2573-State '2583-State '8578 CascadableB . 4-8itPRIORITY ENCODERS/REGISTERSA .TECHNOLOGYDESCRIPTION TYPE STDVOLUMEALS AS LSTTLFull BCD '147Octal '148Cascadable Octal with 3-State Outputs '348Cascadable with Registers'278DESCRIPTION4-8it Sh.fterParallel 16-B.tMulti-ModeBarrel Shifter32-Bit Barrel Sh.fterOUTPUT3-State3-State3-StateSHIFTERSTYPE STDTTL'350'897'8838 ...VOLUMEVOLUME' 2TECHNOLOGYVOLUMEALS AS L LS SLSII:0.~mE ...0\t-I:ca ...(1)I:(1)~• Denotes available technology,... Denotes planned new products,A Denotes" A" suffix version available in the technology indicated,8 Denotes "8" suffix version available in the technology indicated,TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752651-21

FUNCTIONAL INDEXDISPLAY DECODERS/DRIVERS, MEMORY/MICROPROCESSOR CONTROLLERS,AND VOLTAGE-CONTROLLED OSCILLATORSOPEN-COLLECTOR OISPLAY DECODERS/DRIVERSMEMORY/MICROPROCESSOR CONTROLLERSG')CD:::JCD..!... o:::J....3Q),...0':::JOFF-STATETECHNOLOGYTECHNOLOGYDESCRIPTIONTYPEDESCRIPTION OUTPUT TYPE STD VOLUME ALS AS LS SALS AS L LSVOLTAGETTLSystem Controllers (Universal or for '8881 '890BCD-to-OecimalBCD-to-Seven-Segment15 V '4713-State '612Memory Mappers5.5 V '48 I DC '6135.5 V '49 Memory Mappers I 3-State '61030 V '246 with Output Latches I DC '61115 V '247 Multi-Mode latches IBOBOA Applications) '4127 V '347 I 16K, 64K, 2967•7V '447tDynamic Memory ControlierO256K '29685.5 V '24816K,64K '6301 5.5 V '249 256K, 1 MEG '6302•OPEN COLLECTOR DISPLAY DECODERS/DRIVERS WITH COUNTERS/LATCHTECHNOLOGYCLOCK GENERATOR CIRCUITSDESCRIPTION TYPE STDALS AS VOLUMETECHNOLOGYTTLDESCRIPTION TYPE STD VOLUMEALS AS LS SBCD Counter/4-8it Latch/BCD-to-DecimalTTL'142Decoder/DriverQuadruple Complementary-Output'265BCD Counter/4-BitLogic ElementsLatch/BCO-to-Seven-$egmentDecoder/LEO DriverBCD Counter/4-BltLatch/BCD-to-$even-5egmentDecoder/Lamp Driver'143'144Dual Pulse Synchronizers/Drivers '120Crystal-Controlled Oscillators'320'321DigItal Phase-Lock Loop '297Programmable Frequency '292Dlviders!Digltal Timers '294VOLTAGE-CONTROLLED OSCILLATORS Triple 4-lnput AND/NAND Drivers '800DESCRIPTIONTECHNOLOGYTriple 4-lnput OR/NOR Drivers '802Dual VCO '124•VOLUMELSILSILSITYPENo. COMP'L RANGE f maxENABLERextVCO. ZOUTINPUT MHzSingle Yes Yes Yes No 20 '624Single Yes Yes Yes Yes 20 '628Dual No Yes Yes No 60 '124oDual Yes Yes No No 20 '626Dual No No No No 20 '627Dual No Yes Yes No 20 '629LSVOLUMERESULTANT DISPLAYS USING '46A, '47A, '48, '49, 'L46, 'L47, 'LS47, 'LS48, 'LS49, 'LS347o 2 3 4 5 6 7 8 9 10 '11 12 13 14RESULTANT DISPLAYS USING '246, '247, '248, '249, 'LS247, 'LS248, 'LS249, 'LS447o 2 3 4 5 6 7 8 9 10 11 12 13 141;:1o 2 3 4RESULTANT-DISPLAYS USING '143, '144• Denotes available technology,"'Denotes planned new products,A Denotes" A" suffiX version available in the technology indicated .5 6 7 8 91-22 . TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

FUNCTIONAL INDEXCOMPARATORS AND ERROR DETECTION CIRCUITS4-BIT COMPARATORSPARITY GENERATORS/CHECKERS.ERROR DETECTION AND CORRECTION CIRCUITS20-knPull UpStandardP-Q p .. aS-SIT COMPARATORSP>Q P

FUNCTIONAL INDEXARITHMETIC CIRCUITS AND PROCESSOR ELEMENTSG')CD::::JCDQ) "'"::::J....o3 "'"Q)r-+0'::::JPARALLEL BINARY ADDERSDESCRIPTION TYPE STD'802·81t '82'83'283Dual l·Bit Carry-Save '183DESCRIPTION4-81t Parallel Binary Accumulators4 Bit Arithmetic LogiC UnitsFunction Generators4 Bit Arithmetic LogiC Unitwith Rlppl8 CarryLook Ahead C;rry 116 BitGeneratorsTTLTECHNOLOGYALS AS H LS SACCUMULATORS, ARITHMETIC LOGIC UNITS,LOOK·AHEAD CARRY GENERATORSTYPE'281'G81STDTTLTECHNOLOGYALS AS LS SVOLUMEVOLUME'181 f----+--+--,-+---+---1f-----+1--+--f-+-+-f-4 3 & LSI'1181'381 f----+--+--,-+---+---1'881'3B2'182.a.'282 .a.3 & LSIjr: -=-2-=-B,-t----+~:::..+--t---t-=--t--+--t--::-:__:_::c:_l3 882 3 & LSIQuad Serial Adder'Subtractor '385OTHER ARITHMETIC OPERATORSTECHNOLOGYDESCRIPTION TYPE STDALS AS H.LTTLOuad 2 Input Exclusive-OR'86Gates with Totem-PoleOutputs '386Quad 2-1nput Exclusive-ORGates with Open-Collector '136OutputsQuad 2·lnput Exclusive '266NOR Gates '810 .a.Quad 2-lnput Exclusive NOR.a.Gates with Open-Collector '811OutputsQuad E)(clusive OR/NOR'135Gates4 Bit True/Complement'87ElementBIPOLAR BIT·SlICE PROCESSOR ELEMENTSCASCADAOLETECHNOLOGYDESCRIPTIONTO TYPEALS AS LS SN·BITSNo '8878·Blt SliceYes '888Yes '895 .a..LSASVOLUMEVOLUMELSIMULTIPLIERSTECHNOLOGYDESCRIPTION TYPE STDALS AS LS STTL2-Blt-by-4-Slt Parallel Binary Multipliers'261'284 •4-Blt-by-4-Blt Parallel Binary Multipliers'285 •25-MHz 6-Bit Binary Rate Multi~llers '97 •25-MHz Decade Rate Multipliers '167 •8-Blt x 1·Blt 2's Complement Multipliers '384VOLUME• Denotes available technology,"'Denotes planned new products.A Denotes" A" suffix version available in the technology indicated.1-24 TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

FUNCTIONAL INDEXMEMORIESUSER-PROGRAMMABLE READ·ONLY MEMORIES !PROMs)REGISTERED PROMsSTANDARD PROM.DESCRIPTION TYPE ORGANIZATIONTBP285166 2048W x 88TBP3BS165 204SW x SBTBP385166 2048W x S816K-Bit Arrays TBP3S5A165 204SW x S8TBP385A166 2048W x 8BTBP345162 4096W x 4BTBP345A162 4096W x 4BTBP24581 2048W x 4BTBP245A81 2048W x 4BTBP28585A 1024W x SBTBP28586A 1024W x SB8K-Bit Arrays TBP285A86A 1024W x 88TBP3S585 1024W x SSTBP3S5S6 1024W x SBTBP385A85 1024W x SBTBP385A86 1024W x SBTBP24541 1024W x 4BTBP245A41 1024W x 48TBP28542 512W x SB4K-Blf ArraysTBP285A42 512W x 88TBP28546 512W x 88T8P285A46 512W x 88T8P38522 256W x 882K-Bit ArraysT8P385A22 256W x 88TBP24510 256W x 48TBP245Al0 256W x 48lK-Bit ArraysTBP34510 256W x 48TBP34SA10 256W x 48TBP1SS030 32W x S8TBP1SSA030 32W x 88256-Bit ArraysTBP385030 32W x 8BTBP3S5A030 32W x 88TYPEOUTPUT3-5101.3-State3·5101'OCOC3-StateOC.to.3-StateOC3-State .to.3-5101.OC3-5101 • .to.3-5101 • .to.OC.to.OC.to.3-5101.OC3-StateOC3-StateOC3-StateOC3-StateOC3-5101.OC3-S101.OC3-StateOCVOLUMEDESCRIPTION16K-Bit ArraysDESCRIPTION256-81t Arrays64·8,t Arrays16-811 Multiple-PortRegister File16·811 Register FileDual 64-81tRegister FilesDESCRIPTIONTYPETYPEORGANIZATIONOUTPUTTBP34R162 4096W x 4B 3-StateTBP345R165 4096W x 4B 3-5101' .to.TBP38R165 2048W x 8B 3-StateRANDOM-ACCESS READ-WRITE MEMORIES (RAMs)VOLUMEORGANIZA nON OF VOLUMEALS AS LS SOUTPUT3-$tate '2013-$tate16 x 4 3-$tate '219DC '289DC '3193-$lale '172DC3-$lale '670'S703-$tate'871FIRST-IN FIRST-OUT MEMORIES (FIFOs)OFOUTPUT3-5tate3-51ale3-$tate3-$tate3·$lale3-State 225TECHNOLOGYALS AS LS SVOLUMELSI3 & lSIt:0.~COE ...0....t:ca ...Q)t:Q)t!'LOW-POWER PROMs3-Slate 2293-$!ate3 & lSIDESCRIPTION TYPE ORGANIZATION16K-Bit ArraysSK-Blt Arrays4K-Bit ArraysTBP28L166 2048W x 88TBP38L 165 2048W x 88TBP38L 166204SW x 8BTBP34L162 4096W x 48TBP28L85A 1024W x 88T8P28L86ATBP38L85TBP38L861024W x 8B1024W x 8B1024W x 8BTBP28L42 512W x 88T8P2SL46 512W x 88TBP28L22 256W x 882K-Blt Arrays TBP28LA22 256W x SBTBP38L22256W x 8BlK-Blt Arrays TBP34L10 256W x 48256-8;t Arrays TBP3SL030 32W x 88TYPEOUTPUT3-State3-State3-5101.3-5101. A3-State .to.3-State3-State .to.3-State3-State3-State3-S101'OC3-State .to.3-State3-State .to.VOLUME• Denotes available technology.A Denotes planned new products.A Denotes" A" suffix version available in the technology indicated.B Denotes "8" suffix version available in the technology indicated.TEXAS ..INSTRUMENTSPOST OFF(CE BOX 225012 • DALLAS, TEXAS 752651-25

FUNCTIONAL INDEXPROGRAMMABLE LOGIC ARRAYSPROGRAMMABLE lOGIC ARRAYSDESCRIPTIONINPUTSNO.OUTPUTSTYPEAlSNO. OFG)CD::sCD~!.::s-h0~3Q)r+0"::sActive-Low 'T1BPAL l6l8·' 54 'TIBPAL16R4·15Impact PAL'----s Registered 'TIBPAL 16R6·15~ 'TIBPAL l6RS-' 5Actrve-Low 'TIBPAL 16LBA4 'TIBPAL16R4AHigh-Performance PAL' 16----s Registered 'TIBPAL16R6A----s'TlBPAl16RBAActive-low 'TIBPAl16lBA·24 'TlBPAl16R4A·2Half-Power PAL' 16----s Registered 'TIBPAL 16RGA-2Hlgh·Performance PAL'Half·Power PAL' 20----sBActive-low----s Registered"'""""84 'PAL20R4AActive-Low 'PAL20LBA·24 'PAl20R4A·2"'""""8 Registered 'PAL20RGA·2"'""""84'PAl20ABA-2'TlBPAL20l10-20Exclusive-OR PAL' 20--a Registered--;-0 'TIBPAL20X 1 0-20Active-low 'TIBPAL20L1 0·354 'TlBPAL20X4·35Exclusive-OR PAL' 20--a Registered 'TIBPAl2QXS·35--;-0 'TIBPAl20X 10-35BActive-low 'TIBPALR19LB·254 'TIBPAlR19A4·25Registered-Input PAL' 19----e Registered 'TIBPAlR19R6-25--a'TIBPAlR19RB-25Active-low 'TIBPAlR 19l5-404 'TIBPAlR19R4-4QRegistered-Input PAL' 19----e Registered 'TIBPAlR19R6-4Q--a'TIBPAlR19R8-4Qlatched-Input PAL· 19latched-Input PAll 19r-s Registered'TlBPALT19LB·254 'TIBPAlTl9R4-25"'""""8'TIBPAl T19R6-25'TIBPAl T19R8-25Active-low 'TIBPAl Tl9lS-40r-s Registered4 'TIBPAL Tl9R4-40r-s'TIBPAl Tl9R6-40'TIBPAl T19R8-40Field-Programmable 3-State 'TIFPlA83914 x 32 x 6 logiC Arrays OC 'TIFPLA840·····24242024• PAL is a registered trademark of Monolithic Memories Incorporated .• Denotes available. technology,.Denotes planned new products.1-26 TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

General InformationNumerical IndexGlossaryExplanation of Function TablesParameter Measurement InformationFunctional IndexLSI Devices. Application ReportsAdvanced Schottky FamilyError Detection and CorrectionMemory MappingBit-Slice Processor 8-Bit FamilyExcerpt - SN74AS888, SN74AS890Bit-Slice Processor User's GuideMechanical Data2-1

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SN54AS181A, SN54AS881A, SN74AS181A, SN74AS881AARITHMETIC LOGIC UNITS/FUNCTION GENERATORS02661, DECEMBER 19B2 - REVISED AUGUST 19B5• Package Options Include the 'AS 181 A inCompact 300-mil or Standard 600-mil DIPs.The 'AS881A is Offered in 300-mil DIPS,Both Devices are Available in Both Plasticand Ceramic Chip Carriers• Full Look-Ahead for High-Speed Operationson Long WordsoArithmetic Operating Modes:AdditionSubtractionShift Operand A One PositionMagnitude ComparisonPlus Twelve Other Arithmetic Operations• Logic Function ModesExclusive-ORComparatorAND,NAND,OR,NOR'AS881A Provides Status Register ChecksPlus Ten Other Logic OperationsoDependable Texas Instruments Quality andReliabilitySN54AS181A, , , JT OR JW PACKAGESN54AS881A, , , JT PACKAGESN74AS181A, , , NT OR NW PACKAGESN74AS881A, , , NT PACKAGE(TOP VIEW)80 veeAOAl53 B152 A251 B250 A3en 83MGFO en +41'1 PF2GNDA=BF3SN54AS181A, SN54AS881A , , , FK PACKAGESN74AS181A, SN74AS881A , , , FN PACKAGE(TOP VIEW)logic symbolSO 161S 1 ~ 5 ,S2 141S3 131M 181C 171 nO}M.2..3141010.104 3 2 282726S2 5 25 A2S1 6 24 82SO 7 23 A3NC 8 22 NCen 9 21 133M 10 20 GFO 11 19 Cn +121314151617184~ N 0 U C") III 10..Iu..lu.. Z zlu.. "~«NC - No internal connectionPin numbers shown are JT, JW, NT, and NW packages.TYPICAL ADDITION TIMES (CL = 15 pF RL = 280 Q 'T A = 25°C)NUMBERADDITION TIMESPACKAGE COUNTCARRY METHODOF USING 'AS881A USING 'AS181A USING'S181 ARITHMETIC LOOK-AHEADBETWEENBITS AND'AS882 AND 'AS882 AND'S182 LOGIC UNITS CARRY GENERATORS ALUs1 to 4 5 ns 5 ns11 ns 1NONE5 to 8 10 ns 10 ns18 ns 2RIPPLE9 to 16 14 ns 14 ns19 ns 3 or 41 FULL LOOK-AHEAD17 to 64 19 ns 19 ns28 ns 5 to 162 to 5 FULL LOOK-AHEADPRODUCTION DATA documents contain informationcurrent as of publication date, Products conform tospecifications per the terms of Texas Instruments~~aC~~~~~i~a{~~,"u1J~ ~~~~i~~ti~f :llo~:~:~~t:~s~s notTEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265Copyright © 1982, Texas Instruments Incorporated2-3

SN54AS181A, SN54AS881A, SN74AS181A, SN74AS881AARITHMETIC LOGIC UNITS/FUNCTION GENERATORSdescriptionIThe' A5 181 A and' A5881 A are arithmetic logic units (ALU)/function generators that have a complexityof 75 and 77 equivalent gates, respectively, on a monolithic chip. These circuits perform 16 binary arithmeticoperations on two 4-bit words as shown in Tables 1 and 2. These operations are selected by the fourfunction-select lines (50, 51,52,53) and include addition, subtraction, decrement, and straight transfer.When performing arithmetic manipulations, the internal carries must be enabled by applying a low-levelvoltage to the mode control input (M). A full carry look-ahead scheme is made available in these devicesfor fast, simultaneous carry generation by means of two cascade-outputs (pins 15 and 17) for the fourbits in the package. When used in conjunction with the 5N54A5882 or 5N74A5882 full carry look-aheadcircuits, high-speed arithmetic operations can be performed. The typical addition times shown previouslyillustrate the little additional time required for addition of longer words when full carry look-ahead isemployed. The method of cascading' A5882 circuits with these ALUs to provide multilevel full carry lookaheadis illustrated under signal designations.If high speed is not of importance, a ripple-carry input (en) and a ripple-carry output (en + 4) are available.However, the ripple-carry delay has also been minimized so that arithmetic manipulations for small wordlengths can be performed without external circuitry.The' A5 181 A and' A5881 A will accommodate active-high or active-low data if the pin designations areinterpreted as follows:rC/)cCD

SN54AS1B1A, SN54ASBB1A, SN74AS1B1A, SN74ASBB1AARITHMETIC lOGIC UNITS/FUNCTION GENERATORSdescription (continued)The' AS881 A has the same pinout and same functionality as the' AS 181 A except for the P, (3, and Cn + 4outputs when the device is in the logic mode (M = H).In the logic mode the' AS881 A provides the user with a status check on the input words A and 8, andthe ouput word F. While in the logic mode the fl, (3, and Cn + 4 outputs supply status information basedupon the following logical combinations:P=FO+F1 +F2+F3G=HC n +4=PCnFUNCTION TABLE FOR INPUT BITS EQUAL/NOT EQUALSO-S3-H. SI-S2-L. and M-HFUNCTION TABLE FOR INPUT PAIRS HIGH/NOT HIGHSO-SI-S3-L. S2-H • .and M-Hc nHLXXXXOUTPUTSOUTPUTSDATA INPUTSC nDATA INPUTSG P Cn +4G P Cn +4AO=BO Al =Bl A2=B2 A3=B3 H L H AO or BO = L Al or Bl = L A2 or B2 = L A3 or B3 = L H L HAO=80 Al =81 A2=82 A3=83 H L L AO or BO = L AlorBl = L A2 or B2 = L A3 or 83 = L H LAO*80 X X H H X AO=BO=H X X X H HX Al *81 X X H H X X Al=Bl=H X X H HX A2*B2 X H H X X X A2=82 =H X H HX X A3*B3 H H X X X A3=B3=H H HThe combination of signals on the S3 through SO control lines determine the operation performed on thedata words to generate the output" bits Fi. 8y monitoring the P and Cn + 4 outputs, the user can determineif all pairs of input bits are equal (see table above) or if any pair of inputs are both high (see table above).The' AS881 A has the unique feature of providing an A = 8 status while the exclusive-OR( e) functionis being utilized. When the control inputs (S3, S2, S1, SO) equal H, L, L, H; a status check isgenerated to determine whether all pairs (Ai, Bi) are equal in the following manner:P = (AO e 80) + (A 1 e 81) + (A2 e 82) + (A3 e 83). This unique bit-by-bit comparison of the datawords, which is available on the totem-pole P output, is particularly useful when cascading' AS881 s. Asthe A = 8 condition is sensed in the first stage, the signal is propagated through the same ports usedfor carry generation in the arithmetic mode (P and G). Thus the A = 8 status is transmitted to the secondstage more quickly without the need for external multiplexing logic. The A = 8 open-collector output allowsthe user to check the validity of the bit-by-bit result by comparing the two signals for parity.If the user wishes to check for any pair of data inputs (Ai, Bi) being high, it is necessary to set the controllines (S3,S2,S1 ,SO) to L, H, L, L. The data pairs will then be ANDed together and the results ORed inthe following manner: P = AOBO+A"B1 +A2B2+A3B3.signal designations53 I 52 I 51 I 50 I M I P = FO+F1 +F2+F3L 1 H I L I L I H I A080+A1B1 +A2B2+A383H I L I L I H L H I (AO EB 80)+(A1 EB 81)+(A2 EB 82)+(A3 ED 83)In both Figures 1 and 2, the polarity indicators (I::::::.. ) indicate that the associated input or output is activelowwith respect to the function shown inside the symbol and the symbols are the same in both figures.The signal designations in Figure 1 agree with the indicated internal functions based on active-low data,and are for use with the logic functions and arithmetic operations shown in Table 1. The signal designationshave been changed in Figure 2 to accommodate the logic functions and arithmetic operations for the activehighdata given in Table 2. The 'AS181A and 'AS881A together with 'AS882 and 'S182 can be usedwith the signal designation of either Figure 1 or Figure 2.TEXAS ~, INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-5

SN54AS181A, SN54AS881A, SN74AS181A, SN74AS881AARITHMETIC LOGIC UNITS/FUNCTION GENERATORSso 1611S1Sl141S2S3 131181MC n (71'AS181A'AS881AALUl'10 .. 151 CP10 .. 151 CG3161PoQIQ4 10. .151 CO1151117\ G"1141 A-B1161 C +4 n'AS181A'AS881AALUSO 161151l'1151 X10 .. 151 CP141S2 10 151 CG "71 Y31S3 131(14) A=H61PoQIO181M 4 (16)

~~SN54AS181A, SN74AS181AARITHMETIC LOGIC UNITS/FUNCTION GENERATORSlogic diagram (positive logic)'AS181A53 (3)52 (4)51 (5)50~J.!.!!lH>(19)~fr5»-~~rI~~~F==l \. _/=t....-I----===f\(17)(16)(15)))"./(13)~~(20)- ~(21)~r-v~~IlL./->-~I.....-(11)(14) A=BEllenQ)(JoS;cQ)en....IJ(23)(1)130 ~--~AO (2)II11 ./ "----n-)~~~to"(10)(9)FOM (8)(7)TEXAS l!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-7

SN54AS881A, SN74AS881AARITHMETIC LOGIC UNITS/FUNCTION GENERATORSlogic diagram (positive logic)'A5881AS3 ...:.;(3;,:..) ___ -,S2 (4)51 (5)50 (S)(17) G1_ (20)B2ren~ ___(l_S)_ C +4 n(15) Ii>++++---- F3_ (1)BOAO...:.,.(2...:....) ____ ~(9) FO2-8TEXAS -1!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54AS1B1A, SN54ASBB1A, SN74AS1B1A, SN74ASBB1AARITHMETIC lOGIC UNITS/FUNCTION GENERATORSabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltagE!, Vee ........................................... '. . . . . . . . . . . . .. 7 VInput voltage .............................................................. 7 VOff-state output voltage (A = B output only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VOperating free-air temperature range: SN54AS181A, SN54AS881A .......... -55 D e to 125 D eSN74AS181A, SN74AS881A .............. Doe to 70 D eStorage temperature range ......................................... - 65 De to 150 Derecommended operating conditionsVeeVIHVILVOHIOHIOLTASupply voltageHigh-level input voltageLow-level input voltageHigh-level output voltageHigh-level output currentLow-level output currentOperating free-air temperatureA = B output onlyAll outputs exceptA=8 and GGAll outputsexcept GGSN54AS'SN74AS'MIN NOM4.5 52-55MAX MIN NOM MAXUNIT5.5 4.5 5 5.5 V2 V0.8 0.8 V5.5 5.5 V-2 -2 rnA-3 -3 rnA20 20 rnA48 48 rnA125 0 70 °eCJ)Q)(.)os:Q)C(IJ...ITEXAS l!}INSTRUMENTSPOST OFFice BOX 22501~ • OAL.I.AS, TEXAS 752552-9

SN54AS181A, SN54AS881A, SN74AS181A, SN74AS881AARITHMETIC LOGIC UNIT~/FUNCTION GENERATORSIIrtilCCD

SN54AS181A, SN54AS881A, SN74AS181A, SN74AS881AARITHMETIC LOGIC UNITS/FUNCTION GENERATORSswitching characteristics (see Note 1)Vcc= 5 V,CL=15pF, VCC=4.5 V to 5.5 V,RL = 500 QCL = 50 pF (1 5 pF for A = BI.FROM TO TEST (280 Q for A=BI. RL = 500 Q (280 Q for A = BI.PARAMETER (INPUT) (OUTPUT) CONDITIONS TA=25°C TA=MIN to MAX'AS181A SN54AS181A SN74AS181A'AS881A SN54AS881A SN74AS881AMIN Typt MAX MIN Typt MAX MIN Typt MAXtpd Cn Cn +4 5 2 7 11 2 7 9tpdAnyM-O V. 51 -52-0 V.A or BCn +450 = 53 = 4.5 V 15UM model6 2 8 14 2 8 12tpdAnyM=O V. 50=53=0 V.A odiCn +451 =52=4.5 V (DiFrmodel72 8 20 2 8 16tpd C n . Any F M = 0 V 15UM or DIFF model 5 3 6 11 3 6 9tpdAnyM-O V. 51 -52-0 V,GA or B50=53=4.5 V 15UM model4 2 5 9 2 5 7tpdtpdtpdtpdtpdtpdtpdAnyA or BGM = 0 V. 50 = 53 = 0 V.51 =52=4.5 V IDIFF modelAnypM=O V. 51 =52=0 V.AorB50 = 53 = 4. 5 V 15UM modelAnypM=OV.50=53=OV.AorSAi orBiAi orBiAi orBiAny Aor BFiFi51 =52=4.5 V IDIFF modelM=OV. 51 =52=OV.50=53=4.5 V 15UM modelM=OV,50=51=OV.51 =52=4.5 V (5TFFmodel5 2 6 12 2 6 95 2 6 11 2 6 852 6 13 2 6 105 2 5 11 2 5 85 2 6 12 2 6Fi M=4.5 V ILOGIC model 6 2 6 16 2 6 11A=BM=OV.50=53=OV.51 =52=4.5 V IDIFF model12 4 14 26 4 14 2110UNITnsnsnsnsnsnsnsnsnsnsnsnsII(IJQ)(.)oS;Q)cen..Jadditional • AS881 A switching characteristics involving status checks (see Note 1)VCC= 5 v,CL = 15 pF,FROM TO TEST RL=500 Q,PARAMETER (INPUT) (OUTPUT) CONDITIONS TA=25°CtpdtpdtpdtpdAnyAorBAnytiorS'AS881AMIN Typt MAXCn =4.5V. M=4.5 V.P 50=53=4.5 V. 51 =52=0 V. 8Equality IAi = Bi or AiT'BilCn =4.5 V. M=4.5 V,Cn +4 50=53=4.5 V. 51 =52=0 V, 10Equality IAi = Bi or AiT'BilC n =4.5 V. M =4.5 V,AnyAorBP 52 =4.5 V, 50=51 =53 =0 V. 8IAi = iii = H or Ai or iii = l)AnyA or BC n =4.5 V. M=4.5 V,Cn +4 52=4.5 V. 50=51 =53=0 V. 11IAi=Bi=H or Ai or Bi=l)~d = tpHL or tpLHAll typical values are at Vce = 5 V, T A = 25°C.NOTE 1: Load circuit and voltage waveforms are shown in Section 1.VCC=4.5 V to 5.5 v,CL = 50 pF,RL =500 Q,TA=MIN to MAXSN54AS881A SN74AS881AMIN Typt MAX MIN Typt MAX2 10 19 10 152 12 24 2 12 182 10 19 10 1513 25 2 13 19UNITnsnsnsnsTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-11

SN54AS181A, SN54AS881A, SN74AS181A, SN74AS881AARITHMETIC LOGIC UNITS/FUNCTION GENERATORSPARAMETER MEASUREMENT INFORMATIONIr- tPLHenSuM MODE TEST TABLEFUNCTION INPUTS: SO-S3-4.5 V. S1-S2-M-O VOTHER INPUTINPUT OTHER DATA INPUTS OUTPUT OUTPUTSAME BITPARAMETER UNDER UNDER WAVEFORMAPPLY APPLY APPLY APPLYTEST TEST (SEE NOTE 114.5 V GND 4.5 V GNDtplHRemainingAi Bi NonetpHlA and Ben Fi In-PhasetPLHRemainingBi Ai NonetpHL A and 8en Fi In-PhasetPLHRemainingAi Bi None NonetpHLA and B. enp In-PhasetpLHRemainingBi Ai None NonetpHLA and B. enp In-PhasetpLHRemaining RemainingAi None BitPHL 8 A. enG In-PhasetpLHBi None AiRemaining RemainingtPHL B A, enG In-PhasetPLHen None NoneAll All Any FtpHL A B or en + 4tPLHRemaining RemainingAi None BitpHL B A, enCn +4Remaining RemainingBi None AitpHL B A, C nCn +4C(t)DIFF MODE TEST TABLE< FUNCTION INPUTS: S1 ~S2-4,5 V. SO-S3-M-O Vo·In-PhaseOut-ai-PhaseOut-ai-Phase(t)OTHER INPUTfIj INPUT OTHER DATA INPUTS OUTPUT OUTPUTSAME BITPARAMETER UNDER UNDER WAVEFORMAPPLY APPLY APPLY APPLYTEST TEST (SEE NOTE 114.5 V GND 4.5 V GNDtPLHRemaining RemainingAi None 8itpHL A B, C nFi In-PhasetPLHRemaining RemainingBi Ai NonetpHL A B, C nFi Out-ai-PhasetpLH,RemainingAi None Bi NonetpHLA and B, Cn15 In-PhasetpLHRemainingBi Ai None NonetpHLA andB, Cnp- Out-aI-PhasetPLHRemainingAi Bi None NonetpHLA and B, CnG In-PhasetPLHRemainingSi None Ai NonetpHLA and S, CnG Out-aI-PhasetpLHAi None BiRemaining remainingA = B In-PhasetpHL A S, entpLHRemaining RemainingSi Ai NonetPHL A S, C nA = B Out-ai-PhasetpLH All Cn + 4Cn None NoneNonetpHLA and Bor any FtPLHRemainingAi Bi None NonetpHLA, S, C nCn +4tpLHRemaining81 None Ai NonetPHLA, S, C nCn +4In-PhaseOut-ai-PhaseIn-PhaseNOTE 1: Load circuit and voltage waveforms are shown in Section 1.2-12 TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54LS222, SN54LS224, SN54LS227, SN54LS228SN74LS222, SN74LS224, SN74LS227, SN74LS22816 X 4 SYNCHRONOUS FIRST·IN FIRST·OUT MEMORIESJANUARY 1981 REVISED MARCH 1985• Independent Synchonous Inputs andOutputs• 16 Words of 4 Bits Each• 3·State Outputs Drive Bus Lines Directly• Data Rates from 0 to 10 MHz• Fall·Through Time ... 50 ns Typ• Data Terminals Arranged for Optimum PCBoard Layout• Expandable Using External GatingdescriptionThese 64-bit memories are Low-Power Schottkymemory arrays organized as 16 words of 4 bitseach. They can be expanded in multiples of15m + 1 words or 4n bits, or both, (where n isthe number of packages in the vertical array andm is the number of packages in the horizontalarray) however some external gating is required(see Figure 1). For longer words using the'LS224 or 'LS228, the IR signals of the first-rankpackages and OR signals of the last-rankpackages must be ANDed for propersynchronization.TYPEoperationINPUT-READY ENABLE ANDOUTPUT-READY ENABLEOUTPUT'LS222 Yes 3·State'LS22"4 No 3-State'LS227 Yes Open·collector'LS228 No Open-collectorSN54LS222. SN54LS227 ... J PACKAGESN74LS222. SN74LS227 ... J OR N PACKAGE(TOP VIEW)OEVCCIREUNCKIRORELOCKOR00 00NCNC01 0102 0203 03GNOCLRSN54LS224. SN54LS228 ... J PACKAGESN74LS224. SN74LS228 ... J OR N PACKAGE(TOP VIEW)OEVCCIRUNCKLOCKOR00 0001 0102 02D3 03GNDCLRNC ~ No internal connectionFor chip carrier informationcontact the factory.EllCJ)Q)(J'S;Q)cen....IA FIFO memory is a storage device that allows data to be written into and read from its array at independentdata rates. These FIFOs are designed to process data at rates from 0 to 10 MHz in a bit-parallel format,word by word. Data is written into the memory on a high-to-Iow transition at the load clock input (LOCK)and read out on a low-to-high transition at the unload clock input (UNCK).The memory is full when the number of words clocked in exceeds the number of words clocked out by16. When the memory is full, LOCK signals have no effect. When the memory is empty, UNCK signalshave no effect.Status of the FIFO memory (see timing diagram) is monitored by the input ready (IR) and output ready(OR) flags that indicate "not full" and "not empty" conditions. The IR output will be high only when thememory is not full and the LOCK input is low. The OR output will be high only when the memory is notempty and UNCK is high.A low level at the clear (CLR) input resets the internal stack control counters and also sets IR high andOR low to indicate that old data remaining at the data outputs is invalid. Data outputs are non invertingwith respect to the data inputs and are at high impedance when output enable (OE) is low. OE does notaffect the IR and OR outputs.PRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments~~~~~~~~i~a{~~I~'J~ ~!~:i~~ti:r ~1\O~:~:~~t~rOs~s notTEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1979. Texas Instruments Incorporated2-13

SN54LS222, SN54LS224, SN54LS227, SN54LS228SN74LS222, SN74LS224, SN74LS227, SN74LS22816 X 4 SYNCHRONOUS FIRST·IN FIRST·OUT MEMORIESIfunctional block diagram (positive logic)OE (1)[1]_(11)[9]CLR~~~----~~~------------------.LOCK (4)[3]RING COUNTERCTR DIV 16COMPWRITEADDRESS16O=P+1CT=1oP=O+1P=OEMPTY(3)[2]1R(171[14]ORIIrencCD

SN54LS222, SN54LS224, SN54LS227, SN54LS228SN74LS222, SN74LS224, SN74LS227, SN74LS22816 X 4 SYNCHRONOUS FIRST·IN FIRST·OUT MEMORIESlogic symbols t'LS222FIFO 16 X4'LS224FIF016X4(3)IR(17) ORDO (5)10 6.7\7(16) 00DO01 (7)02 (8)03 (9) 'LS227FIF016X4CTREN72.3(14)01(13)02(12) 03(3) IR(17) OR'LS228(2)IR(14)OREllfJ)Cl)(.)oS;cCl)en..oJDO (5)01 (7)02 (8)(9)0310 6.70(16) 00(14)01(13)02(12)03DO010203(7)4.50 (13) 001------------1 (12) 01(11) 02(10) 03t These symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.These symbols are functionally accurate but do not show the details of implementation; for these, see the functional block diagram. Thesymbol represents the memory as if it were controlled by a single counter whose content is the number of words stored at that time. Outputdata is invalid when the counter ~ontent is O.absolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, Vee (See Note 1) ................................... : ........... 7 VInput voltage .............................................................. 7 VOff-state output voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VOperating free-air temperature range:SN54LS222, SN54LS224, SN54LS227, SN54LS228 . . . . . . . . . . . . . . . . .. - 55 De to 125°eSN74LS222, SN74LS224, SN74LS227, SN74LS228 ...................... ODeto 70 0 eStorage temperature range ......................................... - 65 De to 150 °eNOTE 1: Voltage values are with respect to network ground terminal.TEXAS ..J!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-15

SN54LS222, SN54LS224, SN74LS222, SN74LS22416 X 4 SYNCHRONOUS FIRST·IN FIRST·OUT MEMORIESWITH 3·STATE OUTPUTSrecommended operating conditions•rencCD

SN54LS222, SN54LS224, SN74LS222, SN74LS22416 X 4 SYNCHRONOUS FIRST-IN FIRST-OUT MEMORIESWITH 3-STATE OUTPUTSswitching characteristics. Vee5 V. TAPARAMETER FROM TO TEST CONDITIONS'LS222MIN TYP MAXtpLH IREf IR 23 35tpHL IREI IR 9 15tpLH OREf OR 22 35tpHL OREI OR 9 15tpLH LDCKI IR 25 40RL = 2 kfl,tpHL LDCKf IR36 50CL = 15 pF,tpLH LDCKI OR48 70See Note 2tpLH UNCKf OR 29 45tpHL UNCKI OR 28 45tpLH UNCKf IR 49 70tpLH CLRI IR 36 55tpHL CLRI OR 25 40tpHL LDCKI Q 34 50tpLH UNCKf Q RL = 667 n, 54 80tpHL UNCKf Q CL = 45 pF, 45 70tpZL OEf Q See Note 2 22 35tpZH OEf Q 21 35tpLZ OEI Q RL = 667 n, CL = 5 pF, 16 30tpHZ OEI Q See Note 2 18 30NOTE 2: Load circuits and voltage waveforms are shown in Section 1.schematics of inputs and outputsEQUIVALENT OF CLEAR ANDEQUIVALENT OF. OUTPUT READY ENABLE INPUTS OTHER INPUTSVCCINPUT---~-+--13 kn NOMVCC---~---INPUT19kn NOM-..,. ...... -.-TYPICAL OF INPUT READY ANDOUTPUT READY OUTPUTS------...---VCC'LS224UNITMIN TYP MAXnsnsnsns25 40 ns36 50 ns48 70 ns29 45 ns28 45 ns49 70 ns36 55 ns25 40 ns34 50 ns54 80 ns45 70 ns22 35 ns21 35 ns16 30 ns18 30 nsTYPICAL OF Q OUTPUTS---......-VCCenQ)()"S;Q)CrJ)...JTEXAS -1!1INSTRUMENTSPOST OFFICE aox 225012 • DA~~AS, HXAS 752652-17

SN54LS227, SN54LS228, SN74LS227, SN74LS22816 X 4 SYNCHRONOUS FIRST·IN FIRST·OUT MEMORIESWITH OPEN·COLLECTOR OUTPUTSrecommended operating conditionsSN54LS'SN74LS'MIN NOM MAX MIN NOM MAXUNITVee Supply voltage4.5 5 5.5 4.75 5 5.25 VVIH High-level input voltage22 VVIL Low-level input voltage0.7 0.8 VVOH High-level Qutput voltage Q5.5 5.5 VIOH High-level output current IR. OR-0.4 -0.4IOL Low-level output currentQ12 24IR. OR4 8mALDCK highLDCK low601560·15tw Pulse duration UNCK low3030 nsUNeK higheLR lowD to LDCK~302050302050tsu Setup time LDCK~ before UNeK~5050 nsUNCK f before LDCK f5050th Hold timeID from LDCK~ 0 0 nsTA Operating free-air temperature - 55 125 0 70 °celectrical characteristics over recom~ended operating free-air temperature range (unless otherwise~ noted)SN54LS'SN74LS'PARAMETERTEST CONDITIONStMIN TYP~ MAX MIN TYP~ MAXVIK Vce = MIN. 11= -18 mA - 1.5-1.5IOH Q Vee = MIN. VOH = 5.5 V 0.10.1VOH IR. OR Vee = MIN. IOH = -0.4 mA 2.5 3.4 2.7. 3.4Vec = MIN. IOL = 12 mA 0.25 0.4 0.25 0.4QVee = MIN. IOL = 24 mA 0.35 0.5VOLVee = MIN. IOL = 4 mA 0.25 0.4 0.25 0.4IR. ORVee = MIN. IOL = 8 mA 0.35 0.5IOZH Q Vee = MAX. Vo = 2.7 V 2020IOZL Q Vee = MAX. Vo = 0.4 V -20-20II Vee = MAX. VI = 7 V 0.10.1IIH Vee = MAX. VI = 2.7 V 2020IlL Vee = MAX. VI = 0.4 V -0.4-0.4IOS§ IR. OR Vee = MAX -20 -100 -20 -100I Outputs high 84 135 84 135155155lee Vee = MAX I Outputs low 87 155 87I Outputs disabled 89 155 89UNITVmAVV/lA/lAmA/lAmAmAmAtFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.tAli typical values are at Vee = 5 V. TA = 25°e.§Not more than one output should be shorted at a time. and duration of the short-circuit should not exceed one second.2-18 TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54LS227, SN54LS228, SN74LS227, SN74LS22816 X 4 SYNCHRO~JOUS FIRST·IN FIRST·OUT MEMORIESWITH OPEN·COLLECTOR OUTPUTSswitching characteristics. Vee5 V. TA'LS227'LS228PARAMETER FROM TO TEST CONDITIONS UNITMIN TVP MAX MIN TVP MAXtpLH IRET IRtpHL IREl IRtPLH ORET ORtPHL OREl ORtPLH LOCKl IRtpHL LOCKT IRtPLH LOCKl ORtpLH UNCKT ORtPHL UNCKl ORtpLH UNCKT IRtpLH CLRl IRtPHL CLRl ORtpHL LOCKI QRL = 2 k!2,CL=15pF,See'Note 2tpLH UNCKT Q RL = 667 !2,tpHL UNCKT Q CL = 45 pF,tpLH OEI Q See Note 2tpHL OET QNOTE 2: Load circuits and voltage waveforms are shown in Section 1,schematics of inputs and outputsEQUIVALENT OF CLEAR ANDOUTPUT READY ENABLE INPUTSVCC----...... -INPU:...;T .......-,J........_13 kn NOMEQUIVALENT OFOTHER INPUTSVCC--....... ~--19 kn NOMINPUc...:T......, ....... _~23 35 ns9 15 ns22 35 ns9 15 ns25 40 25 40 ns36 50 36 50 ns48 70 48 70 ns29 45 29 45 ns28 45 28 45 ns49 70 49 70 ns36 55 36 55 ns25 40 25 40 ns34 50 34 50 ns54 80 54 80 ns45 70 45 70 ns21 30 21 30 ns20 35 20 35 nsTYPICAL OF INPUT READY AND TYPICAL OF Q OUTPUTSOUTPUT READY OUTPUTSVCCOUTPUT--~EJIenQ)(,)"SQ)cen-ITEXAS ~INSTRUMENTSPOST OF~ICE BOX 225012 • DALLAS, reXAS 752652-19

~SN54lS222, SN54lS224, SN54lS227, SN54lS228SN74lS222, SN74lS224, SN74lS227, SN74lS22816 X 4 SYNCHRONOUS FIRST·IN FIRST·OUT MEMORIESlOADClK -•.,b CLR"- LOCKINPUTREADY"'IR- IRE...DO010203TYPICAL APPLICATIONS INFORMATIONLLOE ~sv CLR OECLR~UNCK IR UNCK l~... .. IR"'ORE I-+- sv-r- IRE ORE ~5V-f- IREOR~~.::J " LOCK OR ~ "- LOCK.., .,00 DO 00 DO01 01 01 0102 02 02 0203 03 03 03OE ~ORUNCK ...ORE f41:00010203OUTPUT""'-E NABlEUNLOADr-ClKOUTPUTREADYEIreno(I) LOCK OR OPEN ~ I> LOCKUNCKIR UNCK"'... IRORE -4-5V- - IRE ORE f-+-5V t--- IRE,. .., ,00 DO 00 DO01 01 01 0102 02 02 0203 03 03 03DE ~HOR r-UNCK..."'ORE 1+ . ,.00010203OE ~-4OR r-UNCK...ORE~r00010203l.b. CLR......LOCK~ IRSV- IRE.,DO010203lLDE SV CLRr+OE f-+SV CLROR I-OPEN ~ ;> LOCK OR I-OPEN ~ ~LOCKUNCK

SN74S22516 x 5 ASYNCHRONOUS FIRST-IN FIRST-OUT MEMORYD1733. SEPTEMBER 1976-REVISED SEPTEMBER 1985• Independent Asynchronous Inputs andOutputs• Organized as 16-Words of 5 BitsooDC to 10-MHz Data Rate3-State Data Outputs• 20-Pin. 300-mil. High-Density PackagedescriptionThis aO-bit active-element memory is amonolithic Schottky-clamped transistortransistorlogic (STTL) array organized as 16words of five-bits each. A memory system usingthe SN74S225 can easily be expanded inmultiples of 16 words or of 5 bits as shown inFigure 2. The three-state outputs controlled bya single enable, OE, makes bus connection andmultiplexing easy.operationSN74S225 ... J OR N PACKAGE(TOP VIEW)ClK AVCCIRClK BUNCK OUTClRDOORD1UNCKIND2 00D3 01D4 02OE 03GND 04A FIFO is a memory storage device that allows data to be written into and/or read from its array atindependent data rates. The 'S225 FIFO will process data at any desired clock rate from DC to 10 MHz.The data is processed in a parallel format, word by word.Reading or writing is done independently utilizing separate asynchronous data clocks. Data may be writteninto the array on the low-to-high transition of either load clock input. Data may be read out of the arrayon the low-to-high transition of the unload clock input (normally high). Writing data into the FIFO maybe accomplished in one of two manners: 1) In applications not requiring a gated clock control. best resultswill be achieved by applying the clock input to one of the clocks while tying the other clock input high.2) In applications needing a gated clock, the load clock (gate control) must be high in order for the FIFOto load on the next clock pulse. The clock A and B inputs can be used interchangeably for either clockgate control or clock input.Status of the 'S225 is provided by three outputs. Input ready monitors the status of the last word locationand signifies when the memory is full. This output is high whenever the memory is available to acceptany data. The unload clock output also monitors the last word location. This output generates a low-Iogiclevelpulse (synchronized to the internal clock pulse) when the location is vacant. The third status output,output ready, is high when the first word location contains valid data and unload clock input is high. Whenunload clock input goes low, output ready will go low and stay low until new valid data is in the first wordposition. The first word location is defined as the location from which data is provided to the outputs.The data outputs are noninverted with respect to the data inputs and are three-state with a common controlinput, output enable. When output enable is low, the data outputs are enabled to function as totem-poleoutputs. A high-logic-level forces each data output to a high-impedance state while all other inputs andoutputs remain active.The clear input invalidates all data stored in the memory array by clearing the control logic and settingoutput ready to a low-logic-level on the high-to-Iow transition of a low-active pulse.IIenQ)CJoS;Q)cen....IPRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments~~aC~~~~~i~ar~~I~tJ~ ~~~:i~~ti~; fllo~:~:~~t:ros~s not. TEXAS "-!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1979. Texas Instruments Incorporated2-21

SN74S22516 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORYFUNCTION TABLESTABLE 1 INPUT FUNCTIONSInput Pin DescriptionClK A 1 load Clock AOO-D4 4-8 Data InputsOE 9 Output EnableUNCK IN 16 Unload ClockClR 18 ClearClK B 19 load Clock BGND 10 Ground pinVCC 20 Supply VoltageTABLE 2 OUTPUT FUNCTIONSOutput Pin DescriptionIR 2 Input ReadyUNCK OUT 3 Unload ClockQ4-DO 11-15 Data OutputsOR 17 Output Readyschematics of inputs and outputsEQUIVALENT OF ALL INPUTSEXCEPT DATA INPUTSVcc-------.----.--EQUIVALENT OF DATA INPUTSVcc---.---TYPICAL OF ALL OUTPUTS'----~---VCCIIrenc(1)~.nentJ)INPUT -_-...... ---+---1INPUTOUTPUTlogic symbol tFIFO 16X5CTRCT

SN74S22516 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORYfunctional block diagram0en...

SN74S22516 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORYIIrencCD

SN74S22516 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORYswitching characteristics over recommended operating ranges of T A and Vee(unless otherwise noted)PARAMETERstf maxf maxf maxtwtdistentplHtpHltPlHtplHtpHltpHltpHltpHltpHltplHtPlHtplHFROMClK AClK BUNCK INUNCK OUTOEUNCK INClK AorClK BUNCK INClRClK AorClK BUNCKINClK AorClK BUNCK INClRORiTOAny QAny QORORORUNCK OUTUNCK OUTIRIRIRAny Qtfmax '" maximum clock frequencytw '" pulse width (output)II == The arrow indicates that the low-to-high (I) or high-to-Iow (I) transition of the output ready (OR) output is used for reference.tplH '" propagation delay time. low-to-high-Ievel output.tpHl == propagation delay time. high-to-Iow-Ievel output.tAli typical values are at VCC = 5 V. TA = 25°C.NOTE 4: load circuit and voltage waveforms are shown in Section 1.TESTCONDITIONSMIN10Cl = 30 pF. 10See Note 4 10Cl = 5 pFCl = 30 pF.See Note 47TYP* MAX UNIT20 MHZ20 MHz20 MHz14 ns10 2525 40ns50 7550 75ns190 300 ns40 60ns30 4535 60 ns25 45 ns270 400 ns55 75 ns255 400 ns16 35 ns10 20 nsenQ)CJ"SQ)cen...J, TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-25

SN74S22516 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORYTYPICAL WAVEFORMS FOR A 16-WORD FIFOINPUTSClRClKA1ClK:UNCKIN~--------------~~--------------~~ORD2\1I:~3:~~~ (1 LJ LJ (OUTPUTS1UNCK::T~ ~o ---------.,WOROl WORD 1 iWORD2 IWORD3--------- • lOADI UNLOADf---j ....._-'WORD 16WORD 3-15 WORD 1I I I I I I II I I I I I I ICLEAR lOAD lOAD lOAD UNLOAD UNLOAD UNLOADWORD 1 WORD2 WORD 16 WOR02 WORD 3-15 WORD 16~ CROSS HATCHING INDICATES IRRELEVANT INPUT CONDITIONSFiGURE 1. TYPICAL WAVEFORMS FOR A 16-WORD FIFOrencCD

SN54ALS229A, SN74ALS229A16 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORIESD2876, MARCH 1986-REVISED APRIL 1986• Independent Asychronous Inputs andOutputs• 16 Words by 5 Bits EachoData Rates from 0 to 30 MHz• Fall-Through Time ... 24 ns Typ• 3-State OutputsdescriptionThese aO-bit memories utilize Advanced LowPower Schottky technology and feature highspeed and fast fall-through times. They areorganized as 16 words by 5 bits each.A FIFO memory is a storage device that allowsdata to be written into and read from its arrayat independent data rates. These FIFOs aredesigned to process data at rates from a to 25megahertz in a bit-parallel format, word by word.Data is written into memory on a low-to-hightransition at the load clock input (LOCK) and isread out on a low-to-high transition at the unloadclock input (UNCK). The memory is full when thenumber of words clocked in exceeds by 16 thenumber of words clocked out. When the memoryis full, LOCK signals will have no effect. Whenthe memory is empty, UNCK signals have noeffect.Status of the FIFO memory is monitored by theFULL, EMPTY, FULL - 2, and EMPTY + 2 outputflags. The FULL output will be low whenever thememory is full, and high whenever not full. TheFULL - 2 output will be low whenever thememory contains 14 data words. The EMPTYoutput will be low whenever the memory isempty, and high whenever it is not empty. TheEMPTY + 2 output will be low whenever 2 wordsremain in memory.SN54ALS229A , . , J PACKAGESN74ALS229A ... OW OR N PACKAGE(TOP VIEW)OEVCCFULL - 2 EMPTY +2FULLUNCLKLOCKEMPTY00 0001 0102 0203 0304 Q4GNORSTSN54ALS229A ... FK PACKAGESN74ALS229A ... FN PACKAGE(TOP VIEW)INN +I >-5...J...J 5 U b:1 w u ~LL.LL.O>w3 2 1 20194 18 UNCLK5 17 EMPTY6 16 007 15 018 14 029 1011 12 13

SN54ALS229A. SN74ALS229A16 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORIESlogic symbol tFIFO 16X 5CTRRST CT=O (CT=16)G1 FULLFULL-2(4)LOCK1(+/C2)EMPTY+2UNCK (18) 3- EMPTYIIrC/)0,CD

SN54ALS229A, SN74ALS229A16 x 5 ASYNCHRONOUS FIRST~IN FIRST·OUT MEMORIESlogic diagram (positive logic)OE 0)RING COUNTERCTR DIV 16 1LOCKUNCKRST (11)WRITE 9ADDRESS 101112CT=l 13141516RING COUNTERCTR DIV 16 1245READADDRESS 910111213CT=l 141516EllenQ)CJ'S;Q)Cen-IDO (5)01 (6)02 :~i03 (9)04(16) 00:~:i ~~(13) 03(12) 0416 16CaMPp=o~--------4---------------~(17)EMPTYoP=0+2 I-----.~P=0-2 ~----If----___ ---l(3)FULl(2)FUi:1:'=2(19)EMPTY+2TEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-29

SN54ALS229A, SN74ALS229A16 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORIEStiming diagramRST~ ,IUNCKrencCD~.oCDen00·03EMPTYEMPfY+2FuLiFULL-2INITIALIZEPOINTERSIIII~ LJIIILOAD UNLOAD EMPTYW1W2WORD 1L-JLJIIIFULLabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, Vee ......................................................... 7 VInput voltage ............................................................... 7 VVoltage applied to a disabled 3-state output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VOperating free-air temperature range: SN54ALS229A ..................... - 55 °e to 125 °eSN74ALS229A ......................... ooe to 70 0 eStorage temperature range ......................................... - 65 °e to 150 °erecommended operating conditionsSN54ALS229A SN74ALS229AMIN NOM MAX MIN NOM MAXUNITVCC Supply voltage 4.5 5 5.5 4.5 5 5.5 VVIH High·level input voltage 2 2 VVIL Low·level input voltage ,0.8 0.8 VIOH High·level output currentQ outputs -1.0 -1.6Status flags -0.4 -0.4mAIOL Low·level output currentQ outputs 12 24Status flags 4 8mAfclock Clock frequencyLOCK 0 25 0 30UNCK 0 25 0 30MHzRST low 20 15LOCK low 15 10tw Pulse duration LOCK high 25 20 nsUNCK low 15 10UNCK high 25 20I Data before LOCKt 10 10tsu Setup timensIRST (inactive) before LOCKt 5 5th Hold time I Data after LDCKi 5 5 nsTA Operating free·air temperature -55 125 0 70 °c2-30TEXAS'.INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54ALS229A, SN74ALS229A16 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORIESelectrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)PARAMETERTEST CONDITIONSSNS4AlS229A SN74AlS229AMIN Typt MAX MIN Typt MAXVIK Vee = 4.5 V, II = -18 rnA -1.2 -1.2 VStatus flags Vee = 4.5 V to 5.5 V, 10H = -0.4 rnA Vee- 2 Vee- 2Vee = 4.5 V, 10H = -1 rnA 2.4 3.3VOH Q outputs VVee = 4.5 V, 10H = -2.6 rnA 2.4 3.2VOLQ outputsStatus flagsVee = 4.5 V, 10l = 12 rnA 0.25 0.4 0.25 0.4Vee = 4.5 V, 10l = 24 rnA 0.35 0.5Vee = 4.5 V, 10L = 4 rnA 0.25 0.4 0.25 0.4Vee = 4.5 V, 10L = 8 rnA 0.35 0.5IOZH Vee = 5.5 V, Va = 2.7 V 20 20 /lAIOZL Vee = 5.5 V, Va = 0.4 V -20 -20 /lAII Vee = 5.5 V, VI = 7 V 0.1 0.1 rnAIIH Vee = 5.5 V, VI = 2.7 V 20 20 /lAIlL Vee = 5.5 V, VI = 0.4 V -0.2 -0.2 rnAlot Vee = 5.5 V, Vo = 2.25 V -30 -112 -30 -112 rnAlee Vee = 5.5 V 95 150 95 140 rnAt All typical values are at Vee = 5 V, T A = 25°e.t The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.switching characteristics (see Note 1)PARAMETERf maxFROM(INPUT)TO(OUTPUT)VCC ~ S v, VCC - 4.S V to S.5 v,CL - so pF, CL - so pF,R1 - sao n, R1 ~ soo n,UNITR2 - 500 n, R2 = soo n, UNITTA = 2SoCTA = MIN to MAX'AlS229A SNS4ALS229A SN74AlS229AMIN TYP MAX MIN MAX MIN MAXLDCK 25 30UNCK 25 30tpd LDCKt Any Q 24 47 7 54 7 50 nstpd UNCKt Any Q 19 29 9 35 9 33 nstpLH LDCKt EMPTY 18 26 9 32 9 30 nstpHL UNCKt EMPTY 18 25 9 32 9 29 nstpHL RSn EMPTY. 15 21 6 26 6 24 nstpd LDCKt EMPTY+2 23 33 10 40 10 38 nstpd UNCKt EMPTY+2 20 29 9 38 9 35 nstpLH RSn EMPTY+2 20 28 9 35 9 33 nstpd LDCKt FULL-2 23 33 10 40 10 38 nstpd UNCKt FULL- 2 20 29 9 38 9 35 nstpLH RSn FULL- 2 20 28 9 35 9 33 nstPHL LDCKt FULL 21 28 10 35 10 33 nstpLH UNCKt FULL 17 23 8 29 8 27 nstpLH RSn FULL 18 27 8 33 8 31 nsten OEt Q 8 13 1 16 2 1S nstdis OE! Q 8 14 2 20 2 17 nsNOTE 1: Load circuit and voltage waveforms are shown in Section 1.VMHzEllTEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-31

IrC/)cCD

SN54ALS232A, SN74ALS232A16 x 4 ASYNCHRONOUS FIRST·IN FIR.ST·OUT MEMORIESD2876. OCTOBER 1985-REVISED APRIL 1986o Independent Asynchronous Inputs andOutputso 16 Words by 4 Bits Eacho Data Rates From 0 to 30 MHzo Fall· Through Time ... 24 ns Typo 3-5tate OutputsdescriptionThese 64-bit memories use Advanced LowPower Schottky technology and feature highspeed and fast fall-through times. They areorganized as 16 words by 4 bits each.A FIFO memory is a storage device that allowsdata to be written into and read from its arrayat independent data rates. These FIFOs aredesigned to process data at rates from 0 to 25megahertz in a bit-parallel format, word by word.Data is written into memory on a low-to-hightransition at the load clock input (LOCK) and isread out on a low-to-high transition at the unloadclock input (UNCK). The memory is full when thenumber of words clocked in exceeds by 16 thenumber of words clocked out. When the memoryis full, LOCK signals have no effect on the dataresiding in memory. When the memory is empty,UNCK signals have no effect.SN54ALS232A ... J PACKAGESN74ALS232A ... D OR N PACKAGE(TOP VIEWIDEVCCFULLUNCKLOCKEMPTY00 0001 0102 0203 03GNORSTSN54ALS232A ... FK PACKAGESN74ALS232A ... FN PACKAGELOCK 400 5NC 601 702 8(TOP VIEWI~I ~u. U U..JUJUUZOZ>=>2 1 20 199 10 11 12 13o U II- MM0 Z Z CJl 0-(!) a::NC-No internal connection.1817161514EMPTY00NC0102Status of the FIFO memory is monitored by the FULL and EMPTY output flags. The FULL output will below when the memory is full, and high when the memory is not full. The EMPTY output will be low whenthe memory is empty, and high when it is not empty.(J)Q)CJ":;Q)C(J)-'A low level on the reset input (RST) resets the internal stack control pointers and also sets EMPTY lowand sets FULL high. The outputs are not reset to any specific logic levels. The first low-to-high transitionon LOCK, either after a RST pulse or from an empty condition, will cause EMPTY to go high and the datato appear on the Q outputs. It is important to note that the first word does not have to be unloaded. Dataoutputs are noninverting with respect to the data inputs and are at high impedance when the output-enableinput (OE) is low. OE does not affect either the FULL or EMPTY output flags. Cascading is easilyaccomplished in the word-width direction, but is not possible in the word-depth direction.PRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments~~~~~:~~i~ar::,~lJ~ ~!~~~~ti~r ~Io~:~;~~t:~~s notTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1984, Texas Instruments Incorporated2-33

SN54ALS232A, SN74ALS232A16 x 4 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORIESlogic symbol tRSTLOCKUNCKFIFO lSX4CTRFULLEMPTYOEDO 20 0001(12)0102 (S) (11) 0203 (7) (10) 03tThis symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. The symbol is functionally accurate butdoes not show the details of implementation; for these, see the logic diagram. The symbol represents the memory as if it were controlled·by a single counter whose content is the number of words stored at the time. Output data is invalid when the counter content ICT) is O.logic diagram (positive logic)renoCD,:;"

SN54ALS232A, SN74ALS232A16 x 4 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORIEStiming diagramRST -.JIILOCK: I r-Il-fl---I I ,UNCKI00 - 03 ~~~~Ir---W-O-RO-' -""""\',.---,\ r--""'\ JI:~~~ '-----W-OR-O-'--:----' ~~ r.:-:==,r:;==-EMPTYFULLINITIALIZEPOINTERSLOADW1UNLOADW2L--.JI,EMPTYL-JIFULLabsolute maximum ratings over operating free-air temperature (unless otherwise noted)Supply voltage, Vee ......................................................... 7 VInput voltage .............................................................. 7 VVoltage applied to a disabled 3-state

SN54ALS232A, SN74ALS232A16 x 4 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORIESlEIrC/)CCD

SN54ALS233A, SN74ALS233A16 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORIES02876. JANUARY 1986-REVISED APRIL 1986• Independent Asychronous Inputs andOutputso16 Words by 5 Bits Each• Data Rates from 0 to 30 MHzoodescriptionFall· Through Time ... 24 ns Typ3·State OutputsThese 80-bit memories utilize Advanced LowPower Schottky technology and feature highspeed and fast fall-through times. They areorganized as 16 words by 5 bits each.A FIFO memory is a storage device that allowsdata to be written into and read from its arrayat independent data rates. These FIFOs aredesigned to process data at rates from 0 to 25megahertz in a bit-parallel format, word by word.Data is written into memory on a low-to-hightransition at the load clock input (LOCK) and isread out on a low-to-high transition at the unloadclock input (UNCK). The memory is full when thenumber of words clocked in exceeds by 16 thenumber of words clocked out. When the memoryis full, LOCK signals will have no effect. Whenthe memory is empty, UNCK signals have noeffect.Status of the FIFO memory is monitored by theFULL, EMPTY, FULL - 1, and EMPTY + 1 outputflags. The FULL output will be low whenever thememory is full, and high whenever not full. TheFULL - 1 output will be low whenever thememory contains 15 data words. The EMPTYoutput will be low whenever the memory isempty, and high whenever it is not empty. TheEMPTY + 1 output will be low whenever oneword remains in memory.SN54ALS233A ... J PACKAGESN74ALS233A ... OW OR N PACKAGEDEFULL-1FULLLOCK(TOP VIEW)DO 0001 0102 0203 0304 04GNORSTVCCEMPTY+1UNCKEMPTYSN54ALS233A ... FK PACKAGESN74ALS233A ... FN PACKAGELOCKDO01020345678(TOP VIEW)I~I~I-+>-ua..w u~0 >w3 2 1 20 199 1011 12 13'

SN54ALS233A, SN74ALS233A16 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORIESlogic symbol tFIFO 16X 5CTRRST CT=O (CT=16)G1 FULLFULL-l(4)LOCK1(+/C2)EMPTY+lUNCK (18) 3- EMPTYIIrCJ)C~~.C')~enOE(1)EN400 (5) (16)20 4'\7 00(6) (15)010102 (7) (14) 0203 (8) (13) 0304 (9) (12) 04t This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. The symbol is functionally accurate butdoes not show the details of implementation; for these, see the logic diagram. The symbol represents the memory as if it were controlledby a single counter whose content is the number of words stored at the time. Output data is invalid when the counter content (CT) is O.2-38 TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54ALS233A, SN74ALS233A16 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORIESlogic diagram (positive logic)OE (1)RING COUNTERCTR DIV 16 1WRITEAODRESS 10111213141516RST (11)RING COUNTERCTR OIV 16 123READADDRESS10111213CT=l 141516'tnQ)(,)"SQ)cen..JDO (5)01 (6)02 :::~! (9)(16) 00:~:: ~~(13) 03(12) 0416 16COMPP=O~--------+---------------.(17)EMPTYoP=O+ll----e---1P=O-ll--------i----...... ---t(3)(2)FULLFULL=1(19)EMi'TY+1TEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-39

SN54ALS233A, SN74ALS233A16 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORIESIIrencCD

SN54ALS233A; SN74ALS233A16 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORIESrecommended operating conditionsSN54ALS233ASN74ALS233AMIN NOM MAX MIN NOM MAXVCC Supply voltage 4.5 5 5.5 4.5 5 5.5 VVIH High-level input voltage 2 2 VVIL Low-level input voltage 0.8 0.8 VQ outputs -1 -1.6IOH High-level output current mAStatus flags -0.4 -0.4Q outputs 12 24IOL Low-level output current mAStatus flags 4 8LDCK 0 25 0 30fclock Clock frequency MHzUNCK 0 25 0 30RST low 20 15LDCK low 15 10tw Pulse duration LDCK high 25 20 nstsuSetup timeUNCK low 15 10UNCK high 25 20Data before LDCKt 10 10RST inactive before LDCKt 55th Hold time Data after LDCKi 5 5 nsTA Operating free-air temperature -55 125 0 70 °celectrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)PARAMETERTEST CONDITIONSSN54ALS233A SN74ALS233AMIN Typt MAX MIN Typt MAXVIK VCC = 4.5 V, II = -18 mA -1.2 -1.2 VStatus flags VCC = 4.5 V to 5.5 V, 10H = -0.4 mA VCC- 2 VCC-2VOH VCC = 4.5 V, 10H = -1 mA 2.4 3.3 VQ outputsVCC = 4.5 V, 10H = -2.6 mA 2.4 3.2VOLQ outputsStatus flagsVCC = 4.5 V, 10L = 12 mA 0.25 0.4 0.25 0.4VCC = 4.5 V, 10L = 24 mA 0.35 0.5VCC = 4.5 V, 10L = 4 mA 0.25 0.4 0.25 0.4VCC = 4.5 V, 10L = 8 mA 0.35 0.510ZH VCC = 5.5 V, Vo = 2.7 V 20 20 p.A10ZL VCC = 5.5 V, Vo = 0.4 V -20 -20 p.AII VCC = 5.5 V, VI = 7 V 0.1 0.1 mAIIH VCC = 5.5 V, VI = 2.7 V 20 20 p.AIlL VCC = 5.5 V, VI = 0.4 V -0.2 -0.2 mAlOt VCC = 5.5 V, Vo = 2.25 V -30 -112 -30 -112 mAICC VCC = 5.5 V 88 143 88 133 mAUNITnsUNITVEllCJ)Q)(,)oSQ)CCJ)...Jt All typical values are at VCC = 5 V, T A = 25°C.t The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.TEXAS -It}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-41

SN54ALS233A,SN74ALS233A16 x 5 ASYNCHRONOUS FIRST·IN FIRST·OUT MEMORIESlEIrtf)CCD~.(")CDtJ)switching characteristics (see Note 1)PARAMETERf maxtpdtpdtpLHtpHLtpHLtpdtpdtpLHtpdtpdtPLHtpHLtpLHtpLHtentdisVcc - 5 V. Vce - 4.5 V to 5.5 V.CL - 50 pF. CL - 50 pF.FROM TO R1 - 500 fl. R1 - 500 fl.(INPUT) (OUTPUT) R2 - 500 fl.R2 - 500 fl.LDCKUNCKLDCKi Any QUNCKi Any QLDCKi EMPTYUNCKi EMPTYRSn EMPTYLDCKi EMPTY + 1UNCKi EMPTY + 1RSn EMPTY + 1LDCKi FULL-1UNCKi FULL-1RSn FULL-1LDCKi FULLUNCKi FULLRSnFULLOEiQOEtQNOTE 1: Load circuit and voltage waveforms are shown in Section 1.TA - 25°C TA - -MIN to MAX'ALS233A SN54ALS233A SN74ALS233AMIN TYP MAX MINMAX MIN MAX40 253040 253024 44 752 7 4819 29 935 9 3318 25 930 9 2818 25 933 10 3013 19 624 6 2222 31 1040 10 3722 31 940 10 3719 27 832 8 3123 32 1138 12 3623 32 1139 12 3620 28 1034 11 3221 28 1035 12 3317 24 829 9 2718 27 832 9 308 13 116 2 158 12 220 2 17UNITMHznsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns2-42 TEXAS -1.!1INSTRUMENTSPOST OFFICE BOX 225012 • OALLAS. TEXAS 75265

SN74AS2501·0F·16 DATA GENERATORS/MULTIPLEXERSWITH 3·STATE OUTPUTSD2910, DECEMBER 1983-REVISED JANUARY 1986• 4·Line to 1·Line Multiplexer that can Select1 and 16 Data InputsooApplications:Boolean Function GeneratorParallel·to·Serial ConverterData Source SelectorBuffered 3·State Bus Driver Inputs PermitMultiplexing from N Lines to One Lineo Dependable Texas Instruments Quality andReliabilitydescriptionThe 'AS250 provides full binary decoding toselect one of sixteen data sources with aninverting Vii output. The selected sources arebuffered with symmetrical propagation delaytimes. This reduces the possibility of transientsoccurring at the output.A buffered enable output (G) may be used forn-line-to-one-line cascading. Taking the G highwill place the output in a high-impedance state.In the high-impedance state, the output neitherloads nor drives the bus lines significantly.The enable (G) does not affect the internaloperations of the data selector/multiplexer. Newdata can be set up while the outputs aredisabled.The SN74AS250 is characterized for operationfrom ooe to 70°C.SN74AS250 ... ow OR NT PACKAGENCE1E7E6E5E4E3E2DGND(TOP VIEW)-""__.....J-VeeE8E9E10E11E12E13E14E15ABSN74AS250 ... FN PACKAGE(TOP VIEW)4 3 2827265256247238229211020111912 1314151617 18eULOtOr--UUCOC'lLULULUZ>LULUI~ 0 ~ ~ U c:l ~t!JNC- No internal connectionE10E11E12NCE13E14E15PRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments~~~~~~~~i~at~:I~tJ~ ~!~~i~~ti:r fl\O~:~:~~t~~s~s notTEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • OALLAS. TEXAS 75265Copyright © 1983, Texas Instruments Incorporated2-43

SN74AS2501·0F·16 DATA GENERATORS/MULTIPLEXERSWITH 3·STATE OUTPUTSlogic symbol tlogic diagram (positive logic)renCCD

SN74AS2501·0F·16 DATA GENERATORS/MULTIPLEXERSWITH 3·STATE OUTPUTSGLLLLLLLLLLLLLLLLHALHLHLHLHLHLHLHLHXFUNCTION TABLEINPUTOUTPUTB C 0 Ei WL L L EO EOL L L E1 E1H L L E2 E2H L L E3 E3L H L E4 E4L H L E5 E5H H L E6 E6H H L E7 E7L .L H EB EBL L H E9 E9H L H E10 E10H L H E11 E11L H H E12 E12L H H E13 E13H H H E14 E14H H H E15 E15X X X X Zabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, Vee ....... , ................................................. 7VInput voltage .............................................................. 7 VOperating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 DC to 70°CStorage temperature range ......................................... - 65°C to 150°Crecommended operating conditionsMIN NOM MAX UNITVee Supply voltage 4.5 5 5.5 VVIH High-level input voltage 2 VVIL Low-level input voltage O.B VIOH High-level output current -15 mAIOL Low-level output current 4B mATA Operating free-air temperature 0 70 DeEll(J)Q)(JoS;cQ)en..oJTEXAS -Ij}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-45

SN74AS2501·0F·16 DATA GENERATORS/MULTIPLEXERSWITH 3·STATE OUTPUTSIIrenc~

SN54ALS280, SN54AS280, SN74ALS280, SN74AS2809-81T PARITY GENERATORS/CHECKERS02661, DECEMBER 1982 - REVISED AUGUST 1985• Generates Either Odd or Even Parity forNine Data LinesoCascadable for n-Bits Parity• Can Be Used to Upgrade Existing SystemsUsing MSI Parity CircuitsooPackage Options Include Both Plastic andCeramic Chip Carriers in Addition to Plasticand Ceramic DIPsdescriptionDependable Texas Instruments Quality andReliabilityThese universal, monolithic, nine-bit paritygenerators/checkers utilize Advanced Schottkyhigh-performance circuitry and feature odd andeven outputs to facilitate operation of either oddor even parity application. The word-lengthcapability is easily expanded by cascading.These devices can be used to upgrade theperformance of most systems utilizing the' 180parity generator/checker. Although the' ALS280and' AS280 are implemented without expanderinputs, the corresponding function is provided bythe availability of an input at pin 4 and theabsence of any internal connection at pin 3. Thispermits the ' ALS280 and ' AS280 to besubstituted for the' 180 in existing designs toproduce an identical function even if the devicesare mixed with existing '180's. .All ' AS280 inputs are buffered to lower the driverequirements.The SN54' family is characterized for operationover the full military temperature range of- 55°C to 125°C. The SN74' family ischaracterized for operation from OOC to 70°C.SN54ALS280, SN54AS280 ... J PACKAGESN74ALS280, SN74AS280 ... 0 OR N PACKAGEGHNC(TOP VIEW)VCCFED~ EVEN C~ ODD BGNDASN54ALS280, SN54AS280 ... FK PACKAGESN74ALS280, SN74AS280 ... FN PACKAGE(TOP VIEW)Uu uIt9Z>u...1 20 1918 ENC 5 17 NCI 6 16 DNC 15 NC~ EVEN 8 14 C9 1011 12 1300 U

SN54ALS280, SN74ALS2809-BITPARITY GENERATORS/CHECKERSlogic diagramr-~ 000cCD

SN54ALS280, SN74ALS2809·81T PARITY GENERATORS/CHECKERSelectrical characteristics over recommended operating free-air temperature range (unless otherwisenoted) .PARAMETERTEST CONDITIONSSNS4ALS280 SN74ALS280MIN Typt MAX MIN Typt MAXVIK Vee = 4.5 V, II = -18 mA -1.2 -1.2 VVee = 4.5 V to 5.5 V, 10H = -0.4 mA vcc- 2 Vcc- 2VOH Vee = 4.5 V, 10H = -1 mA 2.4 3.3 VVOLVee = 4.5 V, 10H = -2.6 mA 2.4 3.2Vee = 4.5 V, 10L = '12 mA 0.25 0.4 0.25 0.4Vee = 4.5 V, 10L = 24 mA 0.35 0.5II Vee = 5.5 V, VI = 7 V 0.1 0.1 mAIIH Vee = 5.5 V, VI = 2.7 V 20 20 /LAIlL Vee = 5.5 V, VI = 0.4 V -0.1 -0.1 mA10i Vee = 5.5 V, Vo = 2.25 V -30 -112 -30 -112 mAlee Vee = 5.5 V 10 16 10 16 mAt All typical values are at Vee = 5 V, T A = 25 De.iThe output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.switching characteristics (see Note 1)PARAMETERVCC = S v, vcc = 4.S V to S.5 V,CL - 50 pF, CL - SO pF,FROM TO RL = SOO n, RL - SOO n,(INPUT) (OUTPUT) TA = 25°C TA = IVIIN to MAX'ALS280 SNS4ALS280 SN74ALS280MIN TYP MAX MIN MAX MIN MAXtpLH 12 16 3 24 3 20Any E Even nstpHL 12 17 3 24 3 20tPLH 12 16 3 24 3 20Any E Odd nstpHL 13 18 4 26 4 22NOTE 1: Load circuit and voltage waveforms are shown in Section 1.UNITVUNITfJIITEXAS ..INSTRUMENTSPOST OFFiCe BOX 225012 • DALLAS, TEXAS 752652-49

SN54AS280, SN74AS2809·81T PARITY GENERATORS/CHECKERSlogic diagram~EVENlEILODDabsolute maximum ratings over operating free-air temrerature range (unless otherwise noted)Supply voltage, Vee ......................................................... 7 VInput voltage .............................................................. 7 VOperating free-air temperature range: SN54AS280 ....................... - 55 DC to 125 DCSN74AS280 ................. .- ......... oDe to 70 DeStorage temperature range ......................................... - 65 DC to 150 DCrecommended operating conditionsSN54AS280SN74AS280UNITMIN NOM MAX MIN NOM MAXVee Supply voltage 4.5 5 5.5 4.5 5 5.5 VVIH High-level input voltage 2 2 VVIL Low-level input voltage 0.8 0.8 VIOH High-level output current -2 -2 mAIOL Low·level output current 20 20 mATA Operating free-air temperature -55 125 0 70 °e2-50TEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54AS280, SN74AS2809·81T PARITY GENERATORS/CHECKERSelectrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)PARAMETERTEST CONDITIONSSN54AS280SN74AS280MIN Typt MAX MIN Typt MAXVIK Vee = 4.5 V, II = -18 mA -1.2 -1.2 VVOH Vee = 4.5 V to 5.5 V, 10H = -2 mA Vcc- 2 Vcc- 2 VVal Vee = 4.5 V, 10L" = 20 mA 0.35 0.5 0.35 0.5 VII Vee = 5.5 V, VI = 7 V 0.1 0.1 mAIIH Vee = 5.5 V, VI = 2.7 V 20 20 p.AIII Vee = 5.5 V, VI = 0.4 V -0.5 -0.5 mA10· Vee = 5.5 V, Va = 2.25 V -30 -112 -30 -112 mAlee Vee = 5.5 V 25 40 25 35 mAt All typical values are at Vee = 5 V, T A = 25°e.+The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.switching characteristics (see Note 1)UNITPARAMETERVcc = 4.5 V to 5.5 V,Cl = 50 pF,FROM TO Rl = 500 n,(INPUT) (OUTPUT) TA = MIN to MAX·SN54AS280SN74AS280MIN MAX MIN MAXtpLH 3 13 3 12Any 1: Even nstpHL 3 12.5 3 11tpLH 3 13 3 12Any 1: Odd nstpHL 3 12.5 3 11.5NOTE 1: load circuit and voltage waveforms are shown in Section 1.UNITElltJ)Q)(,)">cQ)en..JTEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-51

SN54ALS280, SN54AS280, SN74ALS280, SN74AS2809·HIT PARITY GENERATORS/CHECKERST,{PICAL APPLICATION DATA25-LlNE PARITY/GENERATOR CHECKER81-LlNE PARITY/GENERATOR CHECKERABCDEFGHIl:EVEN'ALS280/'AS280l:ODDABCDEFGHI!:ODD'ALS280/'AS280IrCJ)CCD

SN54AS286, SN74AS2869·BIT PARITY GENERATORS/CHECKERWITH BUS DRIVER PARITY 110 PORT02809, DECEMBER 1983-REVISED AUGUST 1985• Generates Either Odd or Even Parity forNine Data Lines• Cascadable for n-Bits Parity.. Direct Bus Connection for Parity Generationor for Checking by Using the Parity 1/0 PortoGlitch-Free Bus During Power Up/Down• Package,Options Include both Plastic andCeramic Carriers in Addition to Plastic andCeramic DIPs• Dependable Texas Instruments Quality andReliabilitydescriptionThe SN54AS286, and SN74AS286 universalnine-bit parity generators/checkers feature alocal output for parity checking and a48-milliampere bus-driving parity I/O port forparity generation/checking. The word-lengthcapability is easily expanded by cascading.The XMIT control input is implementedspecifically to accommodate cascading. WhenXMIT is low the parity tree is disabled and PE willremain at a high logic level regardless of the inputlevels. When XMIT is high the parity tree isenabled. The Parity Error output will indicate aparity error when either an even number ofinputs (A through I) are high and Parity 1/0 isforced to a low logic level. or when an oddnumber of inputs are high and Parity 1/0 isforced to a high logic level.SN54AS286 ... J PACKAGESN74AS286 ... D OR N PACKAGEGHXMITPARITY ERRORPARITY I/OGNOXMIT 4NC 5I 6NC 7PARITY ERROR 8NC - No internal connection(TOP VIEW)VCCFE0CBASN54AS286 ... FK PACKAGESN74AS286 ... FN PACKAGE(TOP VIEW)Uu uI(!JZ>u.3 2 1 20 199 1011 12 13oox «CO::::ZZ>-(!Jl-a:«a..18 E17 NC16 015 NC14 CThe I/O control circuitry was designed so that the I/O port will remain in the high-impedance state duringpower-up or power-down to prevent bus glitches.The SN54AS286 is characterized for operation over the full military range of - 55 DC to 125 DC. TheSN74AS286 is characterized for operation from 0 DC to 70 DC.IItJ)Q)0"$Q)een-IPRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments~~~~~:~~i~a{~~I~~e ~!~~~~tigr fl\o::~:~Mros~s notTEXAS ..INSTRUMENlSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1983. Texas Instruments Incorporated2-53

SN54AS286, SN74AS2869·BIT PARITY GENERATORS/CHECKERWITH BUS DRIVER PARITY I/O PORTFUNCTION TABLENUMBER OF INPUTS(A THRU I) THATARE HIGH0, 2, 4, 6, 81,3,5,7,90, 2, 4, 6, 81,3,5,7,9XMITIIhhhhPARITY1/0HLhIhIPARITYERRORHHHLLHh -H -high input levelhigh output levelI - low input levelL - low output levellogic symbol tlogic diagram (positive logic)II(8)A(9)Bc (10)(11)0(12)(13)(1)G(2)H(4)2KN2(6) PARITY1/0ERRORXMIT(3)EN1absolute maximum ratings over operating free-air temperature rangeSupply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VInput voltage .............................................................. 7 VVoltage applied to a disabled 3-state output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VOperating free-air temperature range: SN54AS286 ....................... - 55°C to 125°CSN74AS286 ........................... ooe to 70°CStorage temperature .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65 DC to 140 DCrecommended operating conditionsSN54AS286SN74AS286MIN NOM MAX MIN NOM MAXUNITVee Supply voltage 4.5 5 5.5 4.5 5 5.5 VVIH High-lev!!1 input voltage 2 2 VVIL Low-level input voltage 0.8 0.8 V10H High-level output currentParity error -2 -2Parity 110 -12 -15rnA10L Low-level output currentParity error 20 20Parity 1/0 32 48rnATA Operating free-air temperature -55 12570 °C2-54 TEXAS l!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265°

SN54AS286, SN74AS2869·BIT PARITY GENERATORS/CHECKERWITH BUS DRIVER PARITY I/O PORTelectrical characteristics over recommended free-air temperature range(unless otherwise noted)PARAMETERTEST CONDITIONSSN54AS286SN74AS286MIN Typt MAX MIN Typt MAXVIK Vee = 4.5 V. II = -18 mA -1.2 -1.2 VAll outputs Vee = 4.5 V to 5.5 V. 10H = -2 mA Vcc- 2 Vcc- 2VOHVee = 4.5 V. 10H = -3 mA 2.4 2.9 2.4 3Parity 1/0 Vee = 4.5 V. 10H = -12 mA 2.4Vee = 4.5 V. 10H = -15 mA 2.5Parity error Vee = 4.5 V. 10L = 20 mA 0.35 0.5 0.35 0.5VOL Vee = 4.5 V. 10L = 32 mA 0.5 VParity 1/0Vee = 4.5 V. 10L = 48 mA 0.5IIIIHParity 1/0 Vee = 5.5 V. VI = 5.5 V 0.1 0.1All other inputs Vee = 5.5 V. VI = 7 V 0.1 0.1Parity 1/0:1: 50 50Vee = 5.5 V.VI = 2.7 VAll other inputs20 20Parity 1/0:1: 0.5 -0.5IlL Vee = 5.5 V. VI = 0.4 V mAAll other inputs 0.5 -0.510§ Vee = 5.5 V. Vo = 2.25 V -30 -112 -30 -112 mAleeTransmit 30 43 30 43Vee = 5.5 VReceive35 50 35 50t All typical values are at Vee = 5 V. T A = 25 ce.:t:For 1/0 ports. the parameters IIH and IlL include the off-state current.§The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current. lOS.switching characteristics (see Note ,1)PARAMETERVCC = 4.5 V to 5.5 V.CL = 50 pF.FROM TO R1 = 500 n.(INPUT) (OUTPUT) R2 = 500 n.TA = MIN to MAXSN54AS286SN74AS286MIN MAX MIN MAXtpLH 3 17 3 15Any A thru I Parity 1/0tpHL3 15 3 14tpLH 3 20 3 16.5Any A thru IParity errortpHL3 18 3 16.5tpLH 3 10 3 9Parity 1/0Parity errortpHL 3 10 39tpZH 3 14 3 13tpZL3 17 3 16XMiTParity 1/0tpHZ 3 13 3 11.5tpLZ 3 11 3 10NOTE 1: Load circuit and voltage waveforms ar shown in Section 1.UNITVmAflAmAUNITnsnsnsnsEllenQ)CJ'S;Q)cen..JTEXAS -I!IINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-55

SN54AS286, SN74AS2869·BIT PARITY GENERATORS/CHECKERWITH BUS DRIVER PARITY I/O PORTTYPICAL APPl.lCATION DATA'AS286ABCD PAR ERR ~-----------.----------- BYTE 1EFGH PAR I/OXMITIrUlCCD

TYPICAL APPLICATION DATASN54AS286, SN74AS2869·BIT PARITY GENERATORS/CHECKERWITH BUS DRIVER PARITY 1/0 PORT'AS286HABC0 PAR ERRG'AS286H'AS286ABC0 PAR ERREFGH PAR I/OIXMITHHH'AS286ABC0 PAR ERREFGH PAR I/OIXMIT'AS286H'AS286ABC0 PAR ERREGHIXMITABc0FGHIXMITABCPAR I/O'AS286'AS286PAR ERR'AS286ABC0FGHIXMITPARITYERRORPARITYI/O•tJ)Q)(.)'S;Q)Cen..oJABC0 PAR ERRFGHPAR I/OHHIXMITHXMITXMIT ..... --------------------------------------------~FIGURE 2. 90-BIT PARITY GENERATOR/CHECKER WITH PARITY ERROR DETECTIONIn Figure 2, a gO-bit parity generator/checker with the XMIT on the last stage is available for use with parity detection.TEXAS ~INSTRUMENlSPOST OFFICE BOX 225012 • DALLAS. TeXAS 752652-57

I2-58

SN54LS610 THRU SN54LS613, SN74LS610 THRU SN74LS613MEMORY MAPPERSD2549, JANUARY 1981 -REVISED DECEMBER 1985• Expands 4 Address Lines to 1 2 AddressLinesoDesigned for Paged Memory Mappingo Output Latches Provided on 'LS610 and'LS611oChoice of 3-State or Open-Collector MapOutputso Compatible with TMS9900 and OtherMicroprocessorsDEVICEOUTPUTSLATCHEDMAPOUTPUT TYPE'LS610 Yes 3-State'LS611 Yes Open-Collector'LS612 No 3-State'LS613 No Open-CollectordescriptionEach 'LS610 through 'LS613 memory-mapperintegrated circuit contains a 4-line to 16-linedecoder, a 16-word by 12-bit RAM, 16 channelsof 2-line to 1-line multiplexers, and othermiscellaneous circuitry on a monolithic chip.Each 'LS610 and 'LS611 also contains 12latches with an enable control.The memory mappers are designed to expand amicroprocessor's memory address capability byeight bits. Four bits of the memory address bus(see System Block Diagram) can be used toselect one of 16 map registers that contain 12bits each. These 12 bits are presented to thesystem memory address bus through the mapoutput buffers along with the unused memoryaddress bits from the CPU. However,addressable memory space without reloading themap registers is the same as would be availablewith the memory mapper left out. Theaddressable memory space is increased only byperiodically reloading the map registers from thedata bus. This configuration lends itself tomemory utilization of 16 pages of 2(n -4)registers each without reloading (n = number ofaddress bits available from CPU).SN54lS' ... JD PACKAGESN74LS' ... JD OR N PACKAGE(TOP VIEW)VecRS2MA3MA2RS3RSlCSMAlSTROBERSOR/WMAODO 01101 010DATA {02 09BUS I/O 03 }DATA08 BUS I/O04 0705 06MMC (NC)t{MOOMO'}MOlMOlOMAP M02M09 MAPOUTPUTS M03 MOB OUTPUTSM04M07M05M06GNOMESN54LS' ... FK PACKAGESN74LS' ... FN PACKAGE(TOP VIEW)6 543 2 4443424140R/W 7 39 NCDO 8 38 MAO01 9 37 01102 10 36 01003 11 35 0904 12 34 0805 13 33 07MM 14 32 06MOO 15 31 C(NC)tMOl 16 30 MOllNC 17 29 MOlO18 19 2021 2223 2425262728tThis pin has no internal connection on 'LS612 and 'LS613NC - No internal connection(J)Q)(J'SQ)cen-IPRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments~~~~~~~~i~ai::1~1~ ~!~:i~~ti~r :llo~:~:~:t:ros~S notTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright :D 1981, Texas Instruments Incorporated2-59

SN54LS610 THRU SN54LS613, SN74LS610 THRU SN74LS613MEMORY MAPPERSn-4 MEMORY ADDRESS BUSMEMORY MAPPERCPUMAO-MA3MOO-M011CONTROL 00-011SYSTEMMEMORYSYSTEM BLOCK DIAGRAMIrC/)CCD

SN54LS610 THRU SN54LS613, SN7 4LS61 0 THRU SN74LS613MEMORY MAPPERSNO.PINNAME7-12 00 thru 01129-3436, 3B, 1,3 RSO thru RS36 R/W5 STROBE4 CS35,37,39,2 MAO thru MA314,19, MOO thru MO 1122-2713 MM21 ME2BC40, 20 VCC,GNODESCRIPTION1/0 connections to data and control bus used for reading from and writing to the map registerselected by RSO-RS3 when CS is low. Mode controlled by R/W.Register select inputs for 1/0 operations.Read or write control used in 1/0 operations to select the condition of the data bus. Whenhigh, the data bus outputs are active for reading the map register. When low, the data bus isused to write into the register.Strobe input used to enter data into the selected map register during 1/0 operations.Chip select input. A low input level selects the memory mapper (assuming more than oneused) for an 1/0 operation.Map address inputs to select one of 16 map registers when in map mode (MM low and CShigh).Map outputs. Present the map register contents to the system memory address bus in the mapmode. In the pass mode, these outputs provide the map address data on MOB-MOll and lowlevels on MOO-M07.Map mode input. When low, 12 bits of data are transferred from the selected map register tothe map outputs. When high (pass mode), the 4 bits present on the map address inputsMAO-MA3 are passed to the map outputs MOB-MO 11, respectively, while MOO-M07 are setlow.Map enable for the map outputs. A low level allows the outputs to be active while a high inputlevel puts the outputs at high impedance.Latch enable input for the 'LS610 and 'LS611 (no internal connection for 'LS612 and 'LS613).A high level will transparently pass data to the map outputs. A low level will latch the outputs.5 V power supply and network ground (substrate) pins.U)Q)CJ"SQ)cen-JTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-61

SN54LS610 THRU SN54LS613, SN74LS610 THRU SN74LS613MEMORY MAPPERSschematics of inputs and outputsINPUT/OUTPUT PORTS, 00-011I/OPORTeQUIVALENT OF OTHER INPUTSVee---+---20kn NOMINPUTMM Req = 7 kn NOMRS, STROBE: Req = 9 kn NOMes, RIW, MA: Req = 6 kn NOMTYPICAL OF 'LS610, 'LS612 MAP OUTPUTS---veeTYPICAL OF 'LS611, 'LS613 MAP OUTPUTSIIrC/)OUTPUT__ ~OUTPmCCD!S.oCDC/labsolute maximum ratings over operating free-air temperature (unless otherwise noted)Supply voltage, Vee (see Note 1) __ . ________ ... _ . _______ . __________ .. _____ .. _ _ _ _ 7 VInput voltage: Data Bus I/O _____ . __________ .. ________ .... _______________ . _ _ _ _ 5.5 VAll other inputs ___ .. _____ ... ___________ .. _ . __________ . _ _ _ _ _ _ _ _ _ _ _ 7 VOperating free-air temperature range: SN54LS61 a through SN54LS613 _ _ _ _ _ _ _ _ - 55°C to 125°CSN74LS61a through SN74LS613 _________ . _ aoe to 70°CStorage temperature range __ .. ______ . _ . ________ ... _______ .. _ . _ _ _ _ _ _ - 65°C to 150 °eNOTE 1: Voltage values are with respect to network ground terminal.2-62 TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54LS610, SN54LS612, SN74LS610, SN74LS612MEMORY MAPPERS WITH 3·STATE MAP OUTPUTSrecommended operating conditionsVCCVIHVILIOHIOLSN54LS610SN54LS612MIN NOM MAXSupply voltage 4.5 5 5.5High-level input voltage 2Low-level input voltage0.7MO-12High-level output currentD-1MO12Low-level output currentD4SN74LS610SN74LS612 UNITMIN NOM MAX4.75 5 5.25 V2 V0.8 V-15mA-2.624mA8tAVCLAddress setup timeI 'LS610 only See Figure 2 30(AV before Claw)30 nstSLSHDuration of strobe input pulse 7575 nstCSLSLCS setup time (CS low to strobe low) 2020 nstWLSLR/W setup time (R/W low to strobe low) 2020 nstRVSLRS setup time (RS valid to strobe low) 2020 nstDVSHtSHCSHtSHWHtSHRXtSHDXTAData setup time (DO-D11 valid to strobe high) See Figure 1 75CS hold time (Strobe high to CS high) 20R/W hold time (Strobe high to R/W high) 20RS hold time (Strobe high to RS invalid) 20Data hold time (Strobe high to DO-D11 invalid) 20Operating free-air temperature -5512575 ns20 ns20 ns20 ns20 ns0 70 °c(/)Q)(.)"S;Q)cen..JTEXAS l.!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-63

SN54LS610, SN54LS612, SN74LS610, SN74LS612MEMORY MAPPERS WITH 3-STATE MAP OUTPUTSelectrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)Ir0-C/)CCD

SN54LS611, SN54LS613, SN74LS611, SN74LS613MEMORY MAPPERS WITH OPEN·COLLECTOR MAP OUTPUTSrecommended operating conditionsSN54LS611SN74LS611SN54LS613SN74LS613UNITMIN NOM MAXMIN NOM MAXVCCVIHVILVOHIOHIOLSupply voltage 4.5High-level input voltage 2Low-level input voltageHigh-level output voltageMOHigh-level output currentDLow-level output currentMOD5 5.50.75.5-11244.75 5 5.2520.85.5-2.6248VVVVmAmAtAVCLAddress setup time(AV before C low)I 'LS611 onlySee Figure 2 3030nstSLSHDuration of strobe input pulse 7575nstCSLSLCS setup time (CS low to strobe low) 2020nstWLSLR/W setup time (R/W low to strobe low) 2020nstRVSLRS setup time (RS valid to strobe low) 2020nstDVSHData setup time (DO-D11 valid to strobe high) See Figure 1 7575nstSHCSHtSHWHtSHRXtSHDXTACS hold time (Strobe high to CS high) 20R/W hold time (Strobe high to R/W high) 20RS hold time (Strobe high to RS invalid) 20Data hold time (Strobe high to DO-D11 invalid) 20Operating free-air temperature -55125202020200 70nsnsnsns°CtnQ)Co)oSQ)cen..JTEXAS .~INSTRUMENTSPOST OFFICE BOX 2250~2 • OALLAS. TEXAS 752652-65

SN54LS611, SN54LS613, SN74LS611, SN74LS613MEMORY MAPPERS WITH OPEN·COLLECTOR MAP OUTPUTSelectrical characteristics over recommended operating free·air temperature range (unless otherwisenoted)SN54LS611SN74LS611PARAMETERTEST CONDITIONStSN54LS613SN74LS613MIN TYP* MAX MIN TYP* MAXVIKVee = MIN, II = -18mA-1.5 -1.5Vee = MIN, VIH = 2 V,VOH D2.4 2.4VIL = MAX, IOH = MAXIOHMO Vee = MIN, VIH = 2 V, VOH = 5.5 V0.1 0.1IOL = 12 mA0.25 0.4 0.25 0.4MOVee = MIN, VIH = 2 V, IOL = 24 mA0.35 0.5VOLVIL = MAXIOL = 4 mA0.25 0.4 0.25 0.4DIOL = 8 mA0.35 0.5IOZH D20 20Vee - MAX, VIH - 2 V,IOZL D-0.4 -0.4Vo = 0.4 VDVI = 5.5 V0.1 0.1IIVee = MAXAll othersVI = 7 V0.1 0.1IIHVee = MAX, VI = 2.7 V20 20IlLVee = MAX, VI = 0.4 V-0.4 -0.4IOS§ D Vee = MAX-30 -130 -30 -130Outputs high100 170 100 170leeVee = MAX I Outputs low100 170 100 170CI Outputs disabled110 200 110 200CD< tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.n" tAli typical values are at Vee = 5 V, T A = 25°e.CD §Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.Vee = MAX, VIH = 2 V,VIL = MAX, Vo = 2.7 VIIrC/)enswitching characteristics, V CC = 5 V, T A = 25 DC, CL = 45 pF to GNDPARAMETERFROM TO 'LS611 'lS613TEST CONDITIONS(INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAXtesLDV Access (enable) time est DO-ll 31 50 28 50tWHDV Access (enable)· time R/Wi DO-ll RL = 2 kfl, 23 35 21 35tRVDV Access time RS DO-ll See Figure 1, 51 75 47 75tWLDZ Disable time R/Wt DO-ll See Notes 2 and 3 32 50 31 50tesHDZ Disable time eSi DO-ll 41 65 40 65tELQV Access (enable) time MEt MOO-ll 21 30 19 30teSHQV Access time eSi MOO-ll 57 90 53 90tMLQV Access time MMt MOO-ll 25 40 25 40RL = 667 fl,teHQV Access time ei MOO-ll30 45See Figure 2,tAVQVl Access time (MM lowl MA MOO-ll47 70 44 70See Notes 2 and 3tMHQV Access time MMi MOO-ll 31 50 31 50Propagation timetAVQV2(MM high)MA M08-11 21 30 20 30tEHQZ Disable time MEi MOO-ll 15 25 15 25UNITVVmAVp.AmAmAp.AmAmAmAUNITnsnsnsnsnsnsnsnsnsnsnsnsnsNOTES: 2. Access times are tested as tpLH and tpHL or tpZH or tpZL. Disable times are tested as tpHZ and tPLZ.3. Load circuits and voltage waveforms are shown in Section 1 .2-66. TEXAS "!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

______________SN54LS610 THRU SN54LS613. SN74LS610 THRU SN74LS613MEMORY MAPPERSexplanation of letter symbolsThis data sheet uses a new type of letter symbol based on JEDEC Standard 100 to describe time intervals.The format is:tAB-CDwhere: subscripts A and C indicate the names of the signals for which changes of state or level orestablishment of state or level constitute signal events assumed to occur first and last, respectively,that is, at the beginning and end of the time interval.Subscripts Band D indicate the direction of the transitions and/or the final states or levels of thesignals represented by A and C, respectively. One or two of the following is used:HLVXZhigh or transition to highlow or transition to lowa valid steady-state levelunknown, changing, or "don't care" levelhigh-impedance (off) state.The hyphen between the Band C subscripts is omitted when no confusion is likely to occur. For theseletter symbols on this data sheet, the signal names are further abbreviated as follows:SIGNAL NAME A AND C SUBSCRIPT SIGNAL NAME A AND C SUBSCRIPTC C ME ECS CS MM MDO-11 D R/W WMAO-MA3 A RSO-RS3 RMOO-M011 Q STROBE STIMING DIAGRAMSCS\""cS" } ....----------------------'I \'--------RiW"W"!+-----tCSLSL ----+1!+-----tSHCSH---+I I III\___ ~I------~:~----flI I I!+-tWLsL -+!+--tSLSH-----+J+-tSHWH-.j: I I ISTROBE--~--------II~----~~jf~--------~I------------------------------------"5" 1 I' 'I !!+tRvSL.1 j+tSHRX+j 1I I I I~~~~~~I I Ir-~I------~------~----~ r---------RS"S" ....... ~~~ ....... ~JI00-11"0"I~tCSLD:!14 ~ItWLDZ IHi-Z I IADDRESS VALID I I ADDRESS VALID NEWV~~~~ESSI ~~I~14 ~14 ~I ~tDVSH tSHDX I twHDV IINPUT VALIDFIGURE 1. WRITE AND READ MODESIf~-JI~~~}-----

SN54LS610 THRU SN54LS613, SN74LS610 THRU SN74LS613MEMORY MAPPERSIrencCD

SN54ALS616, SN54ALS617, SN74ALS616, SN74ALS61716·BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS• Detects and Corrects Single-Bit Errors• Detects and Flags Dual-Bit Errors• Built-In Diagnostic Capability• Fast Write and Read Cycle ProcessingTimes• Byte-Write Capability• Dependable Texas Instruments Quality andReliabilitydescriptionThe 'ALS616 and 'ALS617 are 16-bit parallelerror detection and correction circuits in 40-pin,600-mil packages. The EDACs use a modifiedHamming code to generate a 6-bit check wordfrom a 16-bit data word. This check word isstored along with the data word during thememory write cycle. During memory read cycles,the 22-bit words from memory are processed bythe EDACs to determine if errors have occurredin memory.Single-bit errors in the 16-bit data word areflagged and corrected. Single-bit errors in the6-bit check word are flagged, but the data wordwill remain unaltered. The 6-bit error syndromecode will pinpoint the error-generating location.Dual-bit errors are flagged but not corrected.These errors may occur in any two bits of the22-bit word from memory. The gross-errorcondition of all lows or all highs from memorywill be detected. Otherwise, errors in three ormore bits of the 22-bit word are beyond thecapabilities of these devices to detect.Read-modify-write (byte-control) operations canbe performed with the' ALS616 and 'ALS617EDACs by using output latch enable, LEDBO, andindividual OEBO and OEB1 byte control pins.• Diagnostics are performed on the EDACs bycontrols and internal paths that allow the userto read the contents of the DB and CB inputlatches. These will determine if the failureoccurred in memory or in the EDAC.02840, APRIL 1984-REVISED SEPTEMBER 1985SN54ALS616. SN54ALS617 •.• JD PACKAGESN74ALS616. SN74ALS617 ... JD OR N PACKAGELEDBDMERRERRNCNCNCGNDNCDBODB1OEBODB2DB3DB4DB5DB6DB7CB5CB4OECB(TOP VIEW)VCCS1SONCNCNCGNDDB15DB14OEB1DB13DB12DB11DB10DB9DB8CBOCB1CB2CB3SN74ALS616. SN74ALS617 ... FN PACKAGE1314(TOP VIEW)0: 10 co Uu u u I~ !;g ~ u ..... 0 U UZZZw..:::...J>c.nc.nzz/6 5 432 1 44434241407398389371036113512343332NCGNDDB15DB14DEB1DB13DB12DB1115 31 DB1016 30 DB9NC 17 29 NC1819202122232425262728U ,..... LO -.:t ICO M ('oj ..... 0 CX) UZCDCDCDUCDCDCDCDCDZouuwuuuuoaNC-No internal connectionThe SN54ALS616 and SN54ALS617 are characterized for operation over the full military temperature rangeof - 55°C to 125°C. The SN74ALS616 and SN74ALS617 are characterized for operation from OOC to70°C.This document contains information on products inmore than one phase of development. The status ofeach device is indicated on the pagels) specifying itselectrical characteristics.TE~.INSTRUMENlSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1984, Texas Instruments IncorporatedEll(IJQ)(.)"$Q)cen-'2-69

SN54ALS616, SN54ALS617, SN74ALS616, SN74ALS61716·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSTABLE 1. WRITE CONTROL FUNCTIONCBMEMORY EDAC CONTROL DB CONTROL DB OUTPUT LATCH ERROR FLAGSDATA I/OCHECK I/O CONTROLCYCLE FUNCTION S1 SOOEBO & OEB1 LEDBOERR MERROECBGenerateOutputWrite L L Input H XL H Hcheck wordcheck bits ttSee Table 2 for details on check bit generation.memory write cycle detailsDuring a memory write cycle, the check bits (CBO thru CB5) are generated internally in the EDAC by six8·input parity generators using the 16-bit data word as defined in Table 2. These six check bits are storedin memory along with the original 16-bit data word. This 22-bit word will later be used in the memoryread cycle for error detection and correction.CHECK WORDTABLE 2. PARITY ALGORITHM16-BIT DATA WORDBIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0CBO X X X X X X X XCB1 X X X X X X X XCB2 X X X X X X X XCB3 X X X X X X X XCB4 X X X X X X X XCB5 X X X X X X X XThe six check bits are parity bits derived from the matrix of data bits as indicated by "X" for each bit.error detection and correction detailsDuring a memory read cycle, the 6-bit check word is retrieved along with the actual data. In order to beable to determine whether the data from memory is acceptable to use as presented to the bus, the errorflags must be tested to determine if they are 'at the high level.The first case in Table 3 represents the normal, no-error conditions. The EDAC presents highs on bothflags. The next two cases of single-bit errors give a high on MERR and a low on ERR, which is the signalfor a correctable error, and the EDAC should be sent through the correction cycle. The last three casesof double-bit errors will cause the EDAC to signal lows on both ERR and MERR, which is the interruptindication for the CPU.TOTAL NUMBER OF ERRORSTABLE 3. ERROR FUNCTIONERROR FLAGS16-BIT DATA WORD 6-BIT CHECK WORD ERR MERRDA T A CORRECTION0 0 H H Not applicable1 0 L H Correction0 1 L H Correction1 1 L L Interrupt2 0 L L Interrupt0 2 L L Interrupt2-70 TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54ALS616, SN54ALS617, SN74ALS616, SN74ALS61716·BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSCBMEMORY EDAC CONTROLDB CONTROL DB OUTPUT LATCHERROR FLAGSDATA 1/0CHECK 1/0 CONTROLCYCLE FUNCTION S1 SOOEBO & OEB1 LEDBOERR MERROECBRead Read & flag H L Input H X Input H Enabled tLatch inputRead data & check HReadbitsOutputcorrected dataandsyndrome bitstSee Table 3 for error description.:tSee Table 5 for error location.HHHTABLE 4. READ. FLAG. AND CORRECT FUNCTIONLatchedLatchedinput H L input H Enabled tdatacheck wordOutputOutputcorrected L X syndrome L Enabled tdata wordbits:tError detection is accomplished as the 6-bit check word and the 16-bit data word from memory are appliedto the internal parity generators/checkers. If the parity of all six groupings of data and check bits are correct,it is assumed that no error has occurred and both error flags will be high.If the parity of one or more of the check groups is incorrect. an error has occurred and the proper errorflag or flags will be set low. The two-bit error is not correctable since the parity tree can only identifysingle-bit errors. Both error flags are set low when any two-bit error is detected.Three or more simultaneous bit errors can cause the EDAC to believe that no error, a correctable error,or an uncorrectable error has occurred and will produce erroneous results in all three cases. It should benoted that the gross-error conditions of all highs will be detected.As the corrected word is made available on the data I/O port (DBa thru DB15), the check word I/O port(CBO thru CB5) presents a 6-bit syndrome error code. This syndrome code can be used to locate the badmemory chip. See Table 5 for syndrome decoding.(J)Q)ooSQ)cen...JTEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-71

SN54ALS616, SN54ALS617, SN74ALS616, SN74ALS61716·BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSTABLE 5. SYNDROME DECODINGSYNDROME BITS SYNDROME BITS SYNDROME BITS SYNDORME BITSERRORERRORERROR5 4 3 2 1 05 4 3 2 1 05 4 3 2 1 05 4 3 2 1 0ERRORL L L L L L 2-bit L H L L L L unc H L L L L L unc H H L L L L 2-bitL L L L L H unc L H L L L H 2-bit H L L L L H 2-bit H H L L L H DBaL L L L H L unc L H L L H L 2-bit H L L L H L 2-bit H H L L H L uncL L L L H H 2-bit L H L L H H OB5 H L L L H H D915 H H L L H H 2-bitL L L H L L unc L H L H L L 2-bit H L L H L L 2-bit H H L H L L DB9L L L H L H 2-bit L H L H L H DB4 H L L H L H DB14 H H L H L H 2-bitL L L H H L 2-bit L H L H H L DB3 H L L H H L DB13 H H L H H L 2-bitL L L H H H unc L H L H H H 2-bit H L L H H H 2-bit H H L H H H CB3L L H L L L unc L H H L L L 2-bit H L H L L L 2-bit H H H L L L uncL L H L L H 2-bit L H H L L H OB2 H L H L L H OB12 H H H L L H 2-bitL L H L H L 2-bit L H H L H L DB1 H L H L H L DB11 H H H L H L 2-bitL L H L H H DB7 L H H L H H 2-bit H L H L H H 2-bit H H H L H H CB2L L H H L L 2-bit L H H H L L DBO H L H H L L DB10 H H H H L L 2-bitL L H H L H unc L H H H L H 2-bit H L H H L H 2-bit H H H H L H CB1L L H H H L DB6 L H H H H L 2-bit H L H H H L 2-bit H H H H H L CBOL L H H H H 2-bit L H H H H H CB5 H L H H H H CB4 H H H H H H nonermcCDc::::c:;"CDenCB X = error in check bit XDB Y = error in data bit Y2-bit = double-bit errorunc = uncorrectable multibit errorread-modify-write (byte control) operationsThe' ALS616 and' ALS617 devices are capable of byte-write operations. The 22-bit word from memorymust first be latched into the DB and CB input latches. This is easily accomplished by switching from theread and flag mode (S1 = H, SO = L) to the latch input rt:Jode (S1 = H, SO = HI. The EDAC will thenmake any corrections, if necessary, to the data word and place it at the input of the output data latch.This data word must then be latched into the output data latch by taking LEDBO from a low to a high.Byte control can now be employed on the data word through the OEBO or OEB1 controls. OEBO controlsDBO-DB7 (byte 0), OEB1 controls DB8-DB15 (byte 1).Placing a high on the byte control will disable the output and the user can modify the byte. If a low isplaced on the byte control, then the original byte is allowed to pass onto the data bus unchanged. If theoriginal data word is altered through byte control, a new check word must be generated before it is writtenback into memory. This is easily accomplished by taking control S 1 and SO low. Table 6 lists the readmodify-writefunctions.2-72 TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54ALS616, SN54ALS617, SN74ALS616, SN74ALS61716·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSTABLE 6. READ-MODIFY-WRITE FUNCTIONMEMORYCYCLEReadReadReadModify/writeEDAC FUNCTIONRead & FlagLatch input data& check bitsLatch correcteddata word intooutput latchModify appropriatebyte or bytes &generate newcheck wordDB OUTPUTCONTROLBYTEn t OEBnt LATCHS1 SOLEDBOH Input H XLatchedH H Input HdataLatchedH HoutputdatawordInputmodifiedHHHBYTEOHOutputunchangedBYTEOCHECK I/OCBERROR FLAGCONTROL ERR MERRInput H EnabledLatchedinput H Enabledcheck wordHi-Z----. OutputSyndromebitsOutputcheck wordHEnabledH HtOEBO controls OBO-OB7 (BYTEO). OEB1 controls OB8-0B15 (BYTE1)diagnostic operationsThe' ALS616 and' ALS61 7 are capable of diagnostics that allow the user to determine whether the EDACor the memory is failing. The diagnostic function tables will help the user to see the pqssibilities for diagnosticcontrol.In the diagnostic mode (S1 = L, SO = H)' the checkword is latched into the input latch while the datainput latch remains transparent. This lets the user apply various data words against a fixed knowncheckword. If the user applies a diagnostic data word with an error in any bit location, the ERR flag shouldbe low. If a diagnostic data word with two errors in any bit location is applied, the MERR flag should below. After the checkword is latched into the input latch, it can be verified by taking OECB low. This outputsthe latched checkword. The diagnostic data word can be latched into the output data latch and verifiedvia the LEDBO control pin. By changing from the diagnostic mode (S 1 = L, SO = H), the user can verifythat the EDAC will correct the diagnostic data word. Also. the syndrome bits can be produced to verifythat the EDAC pinpoints the error location. Table 7 lists the diagnostic functions.tJ)Q)(,)'S;Q)cen..JTEXAS -Ij}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-73

SN54ALS616, SN54ALS617, SN74ALS616, SN74ALS61716-81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSTABLE 7. DIAGNOSTIC FUNCTIONDB BYTE DB OUTPUT CBCONTROLEDAC FUNCTION DATA 1/0 CONTROL LATCH CHECK 1/0 CONTROLS1 SOOEBn LEDBO OECBRead & flag H LLatch input checkword while datainput latch remainstransparentEIOutput diagnosticInput correctdata wordInputHXInput correctcheck bitsLatchedERROR FLAGSERRMERRH H HL H diagnostic H L input H Enableddata word tcheck bitsLatch diagnostic Input Output latchedLdata word into L H diagnostic H H check bits Enableddata word t -------H--output latchHi·ZLatchedOutputLatch diagnosticinput syndrome Ldata word into H H H H Enableddiagnosticbitsinput latchdata wordOutput-~---- --H"--Hi-ZOutputsyndromeLdata word & H H diagnostic L H Enabledbitssyndrome bits data word r-~---------Hi-Z , HOutput corrected Output Outputdiagnostic data corrected syndrome LH H L L Enabledword & output diagnostic bitssyndrome bitsdata word---,----Hi-Z--H--tDiagnostic data is a data word with an error in one bit location except when testing the MERR error flag. In this case, the diagnosticdata word will contain errors in two bit locations.2-74 TEXAS -I!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54ALS616, SN54ALS617, SN74ALS616, SN74ALS61716·BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSlogic diagram (positive logic)DECODERSYNDROMEX/Y O~---------------------------------------------------~ GENERATORO~------------------------------~SO - 1 3 t---------------------------,1r-------------~L, r--:;-6", 1;;'1 I 6 ~, r-----=:L==::::::.r--CBO-CB5 ......,LATCHESr---....... C16" 10,BUFFERSS1 - 2 3 I: ... ~--------__,2r--:a-~ GO-G1-,- ~ * ~~,~.~~ 6" O~~~-o 6"ERRORDETECTOROECB ---------d" ENLATCHES--C1DBO-DB7 8",10DB8-D B158, 10MUX[6 X-OR)1~ /--. ,~..-EN ERROR p-- ERR6/,, MUL TI-ERROR 0--- MERR(f)Q)(,)'S;Q)cen...J~8j ,8" , BUFFERS

SN54ALS616, SN54ALS617, SN74ALS616, SN74ALS61716·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VInput voltage: eB and DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VAll others. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VOperating case temperature range SN54ALS616, SN54ALS617, . . . . . . . . . .. - 55°C to 125°COperating free-air temperature range, SN74ALS616, SN74ALS617 ............... ooe to 70°CStorage temperature range ......................................... - 65°C to 150 °erecommended operating conditionsSN54ALS616SN54ALS617MIN NOM MAXVCC Supply voltage 4.5 5 5.5VIH High-level input voltage 2VIL Low-level input voltage 0.8VOH High-level output voltage D8 or CB l'ALS617 5.5IOH High-level output currentERR or MERR -0.4DB or CB l'ALS616 - 1IOL Low-level output currentERR or MERR4DB or CB12tw Pulse duration LEDBO low 45(1) Data and check word before SOT(51 =H)15(2) SO high before LEDBOT (51 = H) t 45(3) LEDBO high before the earlier ofsot or SU t0tsu Setup time(4) LEDBO high before 51 T (SO = H) 0(5) Diagnostic data word before 51 T(SO=H)28(6) Diagnostic check word before thelater of 51 ~ or SOT15(7) Diagnostic data word beforeLEDBOT (51 =L and SO=H)t35(8) Read-mode, SO low and 51 high 35(9) Data and check word after SOT(51 =H)20(10) Data word after S 1 T (SO = H) 20th Hold time(11) Check word after the later of20SU or SOT(12) Diagnostic data word after0LEDBOT (51 =L, SO=H)ttcorr Correction time (see Figure 1) 70TC Operating case temperature - 55 125TA Operating free-air temperatureSN74ALS616SN74ALS617 UNITMIN NOM MAX4.5 5 5.5 V2 V0.8 V5.5 V-0.4mA-2.68mA2425 ns124500121220301515150nsns65 ns°c0 70 °ctThese times ensure that corrected data is saved in the output data latch.tThese times ensure that the diagnostic data word is saved in the output data latch.2-76 TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54ALS616, SN74ALS61616·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS'ALS616 electrical characteristics over recommended operating temperature range (unless otherwisenoted)PARAMETERTEST CONDITIONSSN54ALS616 SN74ALS616MIN Typt MAX MIN Typt MAXVIK VCC = 4.5 V, II = -18 mA -1.5 -1.5 VAll outputs VCC = 4.5 V to 5.5 V, 10H = -0.4 mA Vcc- 2 Vcc- 2VOH VCC = 4.5 V, 10H = -1 mA 2.4 3.3 VDB or CBVCC = 4.5 V, 10H = -2.6 mA 2.4 3.2VOLIIIIHIlLERR or MERRDB or CBVCC = 4.5 V, 10H = 4 mA 0.25 0.4 0.25 0.4VCC = 4.5 V, 10L = 8 mA 0.35 0.5VCC = 4.5 V, 10L = 12 mA 0.25 0.4 0.25 0.4VCC = 4.5 V, 10L = 24 mA 0.35 0.550 or 51 VCC = 5.5 V, VI = 7 V 0.1 0.1DB or CB VCC = 5.5 V, VI = 5.5 V 0.1 0.150 or 51 20 20VCC = 5.5 V, VI = 2.7 V /lADB or CBt20 2050 or 51 -0.4 -0.4VCC = 5.5 V, VI = 0.4 V mADB or CBt-0.1 -0.110§ VCC = 5.5 V, Vo = 2.25 V -30 -112 -30 -112 mAICC VCC = 5.5 V 5ee Note 1 110 190 110 170 mAUNITVmAt All typical values are at VCC = 5V, T A = 25°C.tFor 1/0 ports, the parameters IIH and IlL include the off-state output current.§The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, 105.NOTE 1: ICC is measured with 50 and 51 at 4.5 V and all CB and DB pins grounded.• ALS616 switching characteristics, Vee = 4.5 V to 5.5 V, eLSN54ALS616. TA = ooe to 70 0 e for SN74ALS616PARAMETERtpdtpdFROM(INPUT)TO(OUTPUT)TEST CONDITIONSDB and CB ERR 51 = H, 50 = L, RL = 500 nDB ERR 51 = L, 50 = H, RL = 500 nDB and CB MERR 51 = H, 50 = L, RL = 500 nDB MERR 51 = L, 50 = H, RL = 500 ntpd 50! and 5U CB R 1 = R2 = 500 n·tpd DB CB 51 =L, 50=L, R1 =R2=500 ntpd LEDBO! DB 51 =X, 50=H, Rl =R2=500 fltpd 51i CB 50=H, Rl =R2=500 nten OECB! CB 50=H, 51 =X, Rl =R2=500 ntdis OECBi CB 50=H, 51 =X, Rl =R2=500 nten OEBO and OEB1! DB 50=H, 51 =X, Rl =R2=500 ntdis OEBO and OEBl i DB 50=H,51=X,Rl=R2= 500n50 pF, TeSN54ALS616SN74ALS616MIN MAX MIN MAX10 43 10 4010 43 10 4015 65 15 5515 65 15 55UNIT10 60 10 49 ns10 60 10 49 ns7 35 7 30 ns10 50 10 50 ns2 30 2 27 ns2 30 2 27 ns2 30 2 27 ns2 30 2 27 nsnsnsC/)Q)(.)'S;Q)cen-IPRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments~~~~~:~~i~at~:I~lJ~ ~!~:i~~ti~r :I~o~:~:~:t:ros~s notTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-77

SN54ALS617, SN74ALS61716·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSPRODUCTPREVIEWEIrencCD~.C')CDen'ALS617 electrical characteristics over recommended operating temperature range (unless otherwisenoted)PARAMETERTEST CONDITIONSSN54ALS617 SN74ALS617MIN Typt MAX MIN Typt MAXVIK VCC = 4.5 V. II = -18 mA -1.5 -1.5 VVOH ERR or MERR VCC = 4.5 V to 5.5 V. IOH = -0.4 mA VCC- 2 VCC-2 VIOH DB or CB VCC = 4.5 V. VOH = 5.5 V 0.1 0.1 mAVOLIIIIHIlLERR or MERRDB or CBVCC = 4.5 V. IOH = 4 mA 0.25 0.4 0.25 0.4VCC = 4.5 V. IOL = 8 mA 0.35 0.5VCC = 4.5 V. IOL = 12 mA 0.25 0.4 0.25 0.4VCC = 4.5 V. IOL = 24 mA 0.35 0.5SO or Sl VCC = 5.5 V. VI = 7 V 0.1 0.1DB or CB VCC = 5.5 V. VI = 5.5 V 0.1 0.1SO or Sl 20 20VCC = 5.5 V.VI = 2.7 VDB'or CBt20 20SO or Sl -0.4 -0.4VCC = 5.5 V. VI = 0.4 V mADB or CBt-0.1 -0.1IO§ ERR or MERR VCC = 5.5 V. Vo = 2.25 V -30 -112 -30 -112 mAICC VCC = 5.5 V See Note 1 110 110 mAtAli typical values are at VCC = 5 V. TA = 25°C.tFor 1/0 ports. the parameters IIH and IlL include the off-state output current.§The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current. lOS.NOTE 1: ICC is measured with SO and Sl at 4.5 V and all CB and DB pins grounded., ALS61 7 switching characteristics, V CC = 4.5 V to 5.5 V, CLfor SN54ALS617, TA = ooC to 70°C for SN74ALS617PARAMETERtpdtpd50 pF, TCFROMTOSN54ALS617TEST CONDITIONS(INPUT) (OUTPUT) MIN Typt MAXDB and CB ERR Sl =H. SO=l. RL=500 {l 26DB ERR Sl =L. SO=H. RL=500 {l 26DB and CBMERRSl =H. SO=L. RL=500 {l 40Sl =L. SO=H. RL=500 {l 40tpd SO~ and Sl ~ CB RL =680 {l 40tpd DB CB S 1 = L. SO = L. RL - 680 {l 40tpd LEDBm DB Sl =X. SO=H. RL=680 {l 26tpd Slt CB SO=H. RL-680 {l 40tpLH OECBl CB Sl =X. SO=H. RL=680 {l 24tpHL OECB~ CB Sl =X. SO=H. RL=680 {l 24tplH OEBO and OEBlt DB Sl =X. SO=H. RL=680 {l 24tpHL OEBO and OEB 1 ~ DB Sl =X. SO=H. RL =680 {l 24t All typical values are at VCC = 5 V. T A = 25°C.Additional information on these products can be obtained from the factory as it becomes available.SN74ALS617MIN Typt MAXUNITVmAp.AUNIT26ns2640ns4040 ns40 ns26 ns40 ns24 ns24 ns24 ns24 nsPRODUCT PREVIEW documents contain informationon products in the formative or design ~hase ofdevelopment. Characteristic data and other2-78 specifications are design goals. Texas Instrumentsreserves the right to change or discontinue theseproducts without notice.TEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54ALS616, SN54ALS617, SN74ALS616, SN74ALS61716·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS~READ---+_t4!4----------CDRRECT-------------+t_1~thIS)------+! :I I Iso~~I------------------------------------------~I~ __________SI----~~;=========~tco:rr:oct:;oo;,==========~---------------------------I:-t5UI1I--+r-th(9)--+:j4-td;5~DBOTHRU DBI5----1:::::::='~N~PU~T~D~A$TA~W~D~R~D~=~tZ~~~,C==j(~O~U~TP~U~T~C~DR~R~E~CT~E~D~D~A~TA~W~O~R~D~~~~~--I+---ten---+lOEBOANDOEB1---~----~----~1I I ~I _________________ ~I4--t5ull)~thI9)---+I If- -..I I I I tdis - ~CBOTHRUCB5----i==~I~NP~U~T~C~HE~C~K~W~O~RD~==~ES~~~====:J-IDBS THRU DB15 INPUT DATA WORD OUTPUT CORRECTED DATA WORDI....... ~OEBOOEBII4---t5uI2)~/4'""t5u I3)-+ILEDBO ~~,.....~ ..... ~~,.....~ ...... ...... .... ~~,.....~ ..... ~ #/#$$/$///$////4 :k--tw----+lOECB-----------~~I _____________ ~ ________ ~~ICBO THRU CB5 INPUT CHECK WORD OUTPUT SYNDROME CODE OUTPUT CHECK WORD\~______VA_L_'D_E_R_R_F_LA_G ______J7\~____vA_L_'D_M_E_R_R_F_LA_G ___--J1FIGURE 2. READ, CORRECT, MODIFY MODE SWITCHING WAVEFORMSTEXAS -Ij}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-79

SN54ALS616, SN54ALS617, SN74ALS616, SN74ALS61716·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSIrOOCCD

SN54AlS632A, SN54AlS633 THRU SN54AlS635SN74AlS632A, SN74AlS633 TJiRIJ SN74AlS63532-81T PARAllEL ERROR DETECTION AND CORRECTION CIRCUITS02661, DECEMBER 1982-REVISED DECEMBER 1985• Detects and Corrects Single-Bit Errors• Detects and Flags Dual-Bit Errorso Built-In Diagnostic CapabilityGFast Write and Read Cycle ProcessingTimes• Byte-Write Capability ... 'ALS632A and'ALS633o Dependable Texas Instruments Quality andReliabilityDEVICE PACKAGE BYTE-WRITE OUTPUT'ALS632A 52-pin yes 3-State'ALS633 52-pin yes Open-Collector'ALS634 48-pin no 3-State, ALS635 48-pin no Open-CollectordescriptionThe' ALS632A and' ALS633 through' ALS635devices are 32-bit parallel error detection andcorrection circuits (EDACs) in 52-pin ('ALS632Aand' ALS633) or 48-pin (' ALS634 and' ALS635)600-mil packages. The EDACs use a modifiedHamming code to generate a 7-bit check wordfrom a 32-bit data word. This check word isstored along with the data word during thememory write cycle. During the memory readcycle, the 39-bit words from memory areprocessed by the EDACs to determine if errorshave occurred in memory.Single-bit errors in the 32-bit data word areflagged and corrected.Single-bit errors in the 7-bit check word areflagged, and the CPU sends the EDAC throughthe correction cycle even though the 32-bit dataword is not in error. The correction cycle willsimply pass along the original 32-bit data wordin this case and produce error syndrome bits topinpoint the error-generating location.Dual-bit errors are flagged but not corrected_These errors may occur in any two bits of the39-bit data word from memory (two errors in the32-bit data word, two errors in the 7-bit checkword, or one error in each word). The gross-errorcondition of all lows or all highs from memorywill be detected. Otherwise, errors in three ormore bits of the 39-bit word are beyond thecapabilities of these devices to detect.• ALS632A •• ALS633 _ , , JD PACKAGE(TOP VIEW)LEDBOVCCMERR 51ERR 50DBa 4 OB31OBlOB30OB2OB29OB3OB28OB4OB27OB5OB26OEBOOEB3OB6OB25OB7OB24GNOGNOOB8OB23OB9OB22OEBlOEB2OB10OB21OBllOB20OB12OB19OB13OB18OB14OB17OB15OB16CB6CBOCB5CBlCB4CB2OECBCB3• ALS632A •• ALS633 , , , FN PACKAGE(TOP VIEW)N~OCCCCccl~ UU (")(")N ~I0 ClZZOOOLU~~»~~ooozzU U Cll Cll Cll Icc LU 53 U U ~ 0 Cll Cll Cll U U9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61NC D 10 60 NCOB3 ~11 59 NCOB4 g12 58 OB28OB5 P 13 57 OB27OEBD 14 56 OB26OB6 15 55[ OEB3OB7 16 54 [ OB25GNO 17 53 [ OB24GNO 18 52[ GNOOB8 19 51 [ GNOOB9 20 50 [ OB23OEBl 21 49[ OB22OB10 22 48[ OEB2OBll 23 47( OB21OB12J2446[OB20OB13 J2545( OB19OB14 ]2644[ OB182728293031323234353637383940414243,..., ,,...,NC - No internal connectionIItJ)Q)CJoscQ)en..JThis document contains information on products inmore than one phase of development. The status ofeach device is indicated on the pagels) specifying itselectrical characteristics. TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265Copyright © 1985, Texas Instruments Incorporated2-81

SN54ALS632A, SN54ALS633 THRU SN54ALS635SN74ALS632A, SN74ALS633 THRU SN74ALS63532·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSRead-modify-write (byte-control) operations can be performed with the I ALS632A and I ALS633 EDACsby using output latch enable, LEDBO, and the individual OEBO thru OEB3 byte control pins.Diagnostics are performed on the EDACs by controls and internal paths that allow the user to read thecontents of the DB and CB input latches. These will determine if the failure occurred in memory or in theEDAC.'ALS634, 'ALS635 ... JO PACKAGE(TOP VIEW)'ALS634, 'ALS635 ... FN PACKAGE(TOP VIEW)Ir-CJ)CCD

SN54ALS632A, SN54ALS633 THRU SN54ALS635SN74ALS632A, SN74ALS633 THRU SN74ALS63532-81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSCHECK WORDBIT 31CBO XCB1CB2CB3CB4CBSCB6XXXXTABLE 2. PARITY ALGORITHM32-BIT DATA WORD30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0X X X X X X X X X X X X X X XX X X X X X X X X X X X X X X XX X X X X X X X X X X X X X XX X X X X X X X X X X X X X X XX X X X X X X X X X X X X X XX X X X X X XX X X X X X X XX X X X X X XX X X X X X X XThe seven check bits are parity bits derived from the matrix of data bits as indicated by "X" for each bit.error detection and correction detailsDuring a memory read cycle, the 7-bit check word is retrieved along with the actual data. In order to beable to determine whether the data from memory is acceptable to use as presented to the bus, the errorflags must be tested to determine if they are at the high level.The first case in Table 3 represents the normal, no-error conditions. The EDAC presents highs on bothflags. The next two cases of single-bit errors give a high on MERR and a low on ERR, which is the signalfor a correctable error, and the EDAC should be sent through the correction cycle. The last three casesof double-bit errors will cause the EDAC to signal lows on both ERR and MERR, which is the interruptindication for the CPU.TABLE 3. ERROR FUNCTIONTOTAL NUMBER OF ERRORS32-BIT DATA WORD7-BIT CHECK WORDERROR FLAGSERRMERRDATA CORRECTION0 0 H H Not applicable1 0 L H Correction0 1 L H Correction1 1 L L Interrupt2 0 L L Interrupt0 2 L L InterruptError detection is accomplished as the 7-bi~ check word and the 32-bit data word from memory are appliedto internal parity generators/checkers. If the parity of all seven groupings of data and check bits are correct,it is assumed that no error has occurred and both error flags will be high.If the parity of one or more of the check groups is incorrect, an error has occurred and the proper errorflag or flags will be set low. Any single error in the 32-bit data word will change the state of either threeor five bits of the 7-bit check word. Any single error in the 7-bit check word changes the state of onlythat one bit. In either case, the single error flag (ERR) will be set low while the dual error flag (MERR) willremain high.Any two-bit error will change the state of an even number of check bits. The two-bit error is not correctablesince the parity tree can only identify single-bit errors. Both error flags are set low when any two-bit erroris detected.Three or more simultaneous bit errors can cause the EDAC to believe that no error, a correctable error,or an uncorrectable error has occurred and will produce erroneous results in all three cases. It should benoted that the gross-error conditions of all lows and all highs will be detected.•U)Q)(.)'SQ)c(J)...JTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-83

SN54ALS632A, SN54ALS633 THRU SN54ALS635SN74ALS632A, SN74ALS633 THRU SN74ALS63532·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSTABLE 4. READ. FLAG. AND CORRECT FUNCTIONDB CONTROL DB OUTPUT LATCHMEMORY EDAC CONTROLDATA 1/0 OEBn OR (' ALS632A •• ALS633) CHECK 1/0CYCLE FUNCTION S1 SOOEDBLEDBORead Read & flag H LLatch inputRead data & check H HbitsOutputRead corrected data H H& syndrome bitsInput H X InputLatchedLatchedinput H L inputdataOutputcheck wordOutputcorrected L X syndromedata wordbitsfCBERROR FLAGSCONTROLOECBERR MERRH EnabledtH EnabledtL EnabledttSee Table 3 for error description.tSee Table 5 for error location.IrCJ)oen~.oentJ)As the corrected word is made available on the data I/O port (DBa thru OB311. the check word I/O port(CBO thru CB6) presents a 7-bit syndrome error code. This syndrome error code can be used to locatethe bad memory chip. See Table 5 for syndrome decoding.2-84TEXAS "!}INSTRUMENTSPOST OFFICE BOX 225012 • OALLAS. TEXAS 75265.

SN54ALS632A, SN54ALS633 THRU SN54ALS635SN74ALS632A, SN74ALS633 THRU SN74ALS63532·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSTABLE 5. SYNDROME DECODINGSYNDROME BITSSYNDROME BITSSYNDROME BITSSYNDROME BITSERRORERRORERROR6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0ERRORL L L L L L L unc L H L L L L L 2-bit H L L L L L L 2-bit H H L L L L L uncL L L L L L H 2-bit L H L L L L H unc H L L L L L H unc H H L L L L H 2-bitL L L L L H L 2-bit L H L L L H L DB7 H L L L L H L unc H H L L L H L 2-bitL L L L L H H unc L H L L L H H 2-bit H L L L L H H 2-bit H H L L L H H OB23L L L L H L L 2-bit L H L L H L L OB6 H L L L H L L unc H H L L H L L 2-bitL L L L H L H unc L H L L H L H 2-bit H L L L H L H 2-bit H H L L H L H DB22L L L L H H L unc L H L L H H L 2-bit H L L L H H L 2-bit H H L L H H L DB21L L L L H H H 2-bit L H L L H H H OB5 H L L L H H H unc H H L L H H H 2-bitL L L H L L L 2-bit L H L H L L L OB4 H L L H L L L unc H H L H L L L 2-bitL L L H L .L H unc L H L H L L H 2-bit H L L H L L H 2-bit H H L H L L H OB20L L L H L H L OB31 L H L H L H L 2-bit H L L H L H L 2-bit H H L H L H L OB19L L L H L H H 2-bit L H L H L H H OB3 H L L H L H H OB15 H H L H L H H 2-bitL L L H H L L unc L H L H H L L 2-bit H L L H H L L 2-bit H H L H H L L OB18L L L H H L H 2-bit L H L H H L H OB2 H L L H H L H unc H H L H H L H 2-bitL L L H H H L 2-bit L H L H H H L unc H L L H H H L OB14 H H t.. H H H L 2-bitL L L H H H H OB30 L H L H H H H 2-bit H L L H H H H 2-bit H H L H H H H CB4L L H L L L L 2-bit L H H L L L L OBO H L H L L L L unc H H H L L L L 2-bitL L H L L L H unc L H H L L L H 2-bit H L H L L L H 2-bit H H H L L L H OB16L L H L L H L OB29 L H H L L H L 2-bit H L H L L H L 2-bit H H H L L H L uncL L H L L H H 2-bit L H H L L H H unc H L H L L H H OB13 H H H L L H H 2-bitL L H L H L L OB28 L H H L H L L 2-bit H L H L H L L 2-bit H H H L H L L OB17L L H L H L H 2-bit L H H L H L H OB1 H L H L H L H OB12 H H H L H L H 2-bitL L H L H H L 2-bit L H H L H H L unc H L H L H H L OB11 H H H L H H L 2-bitL L H L H H H OB27 L H H L H H H 2-bit H L' H L H H H 2-bit H H H L H H H CB3L L H H L L L OB26 L H H H L L L 2-bit H L H H L L L 2-bit H H H H L L L uncL L H H L L H 2-bit L H H H L L H unc H L H H L L H OB10 H H H H L L H 2-bitL L H H L H L 2-bit L H H H L H L unc H L H H L H L OB9 H H H H L H L 2-bitL L H H L H H OB25 L H H H L H H 2-bit H L H H L H H 2-bit H H H H L H H CB2L L H H H L L 2-bit L H H H H L L unc H L H H H L L OB8 H H H H H L L 2-bitL L H H H L H 0824 L H H H H L H 2-bit H L H H H L H 2-bit H H H H H L H CB1L L H H H H L unc L H H H H H L 2-bit H L H H H H L 2-bit H H H H H H L CBOL L H H H H H 2-bit L H H H H H H CB6 H L H H H H H CB5 H H H H H H H noneCB X= error in check bit X08 Y= error in data bit Y2-bit = double-bit errorunc = uncorrectable multibit errorEllCJ)Q)(.)oSQ)Cen..oJread·modify-write (byte control) operationsThe' ALS632A and' ALS633 devices are capable of byte-write operations. The 39-bit word from memorymust first be latched into the DB and CB input latches. This is easily accomplished by switching from theread and flag mode (S1 = H, SO = L) to the latch input mode (S1 = H, SO = H). The EOAC will thenmake any corrections, if necessary, to the data word and place it at the input of the output data latch,This data word must then be latched into the output data latch by taking LEOBO from a low to a high.Byte control can now be employed on the data word through the OEBO through OEB3 controls. OEBOcontrols OBO-OB7 (byte 0)' OEBl controls OB8-0B15 (byte 1), OEB2 controls OB16-0B23 (byte 2), andOEB3 controls OB24-0B31 (byte 3). Placing a high on the byte control will disable the output and the usercan modify the byte. If a low is placed on the byte control, then the original byte is allowed to pass ontothe data bus unchanged. If the original data word is altered through byte control, a new check word mustbe generated before it is written back into memory. This is easily accomplished by taking control S 1 andSO low. Table 6 lists the read-modify-write functions.TEXAS '1!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-85

SN54ALS632A, SN54ALS633 THRU SN54ALS635SN74ALS632A, SN74ALS633 THRU SN74ALS63532·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSMEMORYCONTROLEOAC FUNCTIONCYCLE S1 SOIIr- diagnostic operationsencctI

SN54AlS632A, SN54AlS633 THRU SN54AlS635SN74AlS632A, SN74AlS633 THRU SN74AlS63532·811 PARAllEL ERROR DETECTION AND CORRECTION CIRCUITSTABLE 7. 'ALS632A, 'ALS633 DIAGNOSTIC FUNCTIONEDAC FUNCTIONRead & flagLatch input checkword while datainput latch remainstransparentLatch diagnosticdata word intooutput latchLatch diagnosticdata word intoinput latchOutput diagnosticdata word &syndrome bitsOutput correcteddiagnostic dataword & outputsyndrome bitsCONTROLS1HSOLDB BYTE DB OUTPUT CBDATA.I/O CONTROL LATCH CHECK I/O CONTROLInput correctdata wordInputOEBn LEDBO OECBHXInput correctcheck bitsLatchedERROR FLAGSERRMERRH H HL H diagnostic H L input H Enableddata word tcheck bitsInputOutput latchedLL H diagnostic H H check bits Enableddata word t-------- -----Hi-ZHLatchedOutputinput syndrome LH H H H Enableddiagnosticbits---------data word Hi-Z HOutputOutputsyndromeLH H diagnostic L H Enabledbitsdata word -------- ----Hi-ZHOutputOutputcorrected syndrome LH H L L Enableddiagnosticbitsr-----------data word Hi-Z HtOiagnostic data is a data word with an error in one bit location except when testing the MERR error flag. In this case, the diagnostic dataword will contain errors in two bit locations.TABLE 8. 'ALS634, 'ALS635 DIAGNOSTIC FUNCTIONIIU)Q)(.)'>Q)CCJ)..JEDAC FUNCTIONRead & flag H LLatch input checkbits while datainput latch remainstransparentOutput inputcheck bitsCONTROL DB CONTROL DB CONTROL ERROR FLAGSDATA I/OCHECK I/OS1 SOOEDBOECB ERR MERRInput correctdata wordHInput correctcheck bitsH H HInputLatched inputL H diagnostic H H Enableddata word tcheck bitsInputLOutput inputH diagnostic Hdata word tcheck bitsL EnabledLatch diagnostic Latched input OutputLdata into H H diagnostic H syndrome bits Enabledinput latchdata wordr--------- ---H----Output corrected Output corrected OutputLdiagnostic H H diagnostic L syndrome bits Enableddata word1-------- ---H----data word Hi-ZtOiagnostic data is a data word with an error in one bit location except when testing the MERR error flag. In this case, the diagnostic dataword will contain errors in two bit locations.Hi-ZTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-87

SN54ALS632A, SN54ALS633, SN74ALS632A, SN74ALS63332-81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS'ALS632A, 'ALS633 logic diagram (positive logic)DECODERX/Y0OhI'"'so - 1 31S1 - 2 3"2-~71,r--I.l:tIICHECK·BITGENERATORJ SYNDROMEGENERATOR- =1;;;>1~ ~~--+- ~~IIrencCD

SN54ALS634, SN54ALS635, SN74ALS634, SN74ALS63532·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS'ALS634, 'ALS635 logic diagram (positive logic)SO -- 1S1 -- 2DECODERX/Y 0o 1.0..I""313 ::2 -LATCHES~~-7,,JSYNDROMEIGENERATOR~ r--:;-I ;;;'1 L ~ hCHECK-BITGENERATOR ~(See Table 2)hh'"'CBOCB67,,~MUXBUFFERS~ GO 1r!r-'--~G1---C ENLATCHES~* ~1 .... 71 o ' ...'-- C1DBO_DB31-. .....__3--:2~ __ ~~3...,. ,2'--_-11 D~32'- EN7, ..,ERRORDETECTOR(See Table 3)[7X·OR]7, -ERROR 0--- ERRMUL TI- 0----ERROR MERRIIU)Q)(,)oS;cQ)en..oJ32'---4----1*OEDB---------------~~'ENBUFFERS

SN5'4ALS632A, SN54ALS633 THRU SN54ALS635SN74ALS632A, SN74ALS633 THRU SN74ALS63532·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VInput voltage: eB and DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VAll others .....................' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VOperating free-air temperature range:SN74ALS632A, SN74ALS633 thru SN74ALS635 ................ oDe to 70 D eOperating case temperature range:SN54ALS632A, SN54ALS633 thru SN54ALS635 . . . . . . . . . . . .. - 55 DC to 125°CStorage temperature range ......................................... - 65 DC to 150 °erecommended operating conditionsI~CCD

SN54ALS632A, SN54ALS634, SN74ALS632A, SN74ALS63432·BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSWITH 3·STATE OUTPUTS'ALS632A, 'ALS634 electrical characteristics over recommended operating temperature range (unlessotherwise noted)SN54ALS632ASN74ALS632APARAMETER TEST CONDITIONS SN54ALS634 SN74ALS634 UNITMIN Typt MAX MIN Typt MAXVIK Vcc = 4.5 V. II = -18 mA -1.5 -1.5 VAll outputs Vcc = 4.5 V to 5.5 V. IOH = -0.4 mA Vcc- 2 Vcc- 2VOH Vcc = 4.5 V •. 10H = -1 mA 2.4 3.3 VDB or CBVCC = 4.5 V.10H = -2.6 mA 2.4 3.2VOLERR or MERRVCC = 4.5 V. 10L = 4 mA 0.25 0.4 0.25 0.4VCC = 4.5 V. 10L = 8 mA 0.35 0.5DB or CBVCC = 4.5 V. 10L = 12 mA 0.25 0.4 0.25 0.4VCC = 4.5 V.10L = 24 mA 0.35 0.5VII50 or 51 VCC = 5.5 V. VI = 7 V 0.1 0.1All others VCC = 5.5 V. VI = 5.5 V 0.1 0.1mAIIHIlL50 or 51 20 20All others t VCC = 5.5 V. VI = 2.7 V20 2050 or 51 -0.4 -0.4All others t VCC = 5.5 V. VI = 0.4 V mA-0.1 -0.110§ VCC = 5.5 V. Vo = 2.25 V -30 -112 -30 -112 mAICC VCC = 5.5 V. 5ee Note 1 150 250 150 250 mAt All t~pical values are at VCC = 5 V. T A = 25°C.~ For I/O ports. the parameters IIH and IlL include the off-state output current.§ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current. 105.NOTE 1: ICC is measured with 50 and 51 at 4.5 V and all CB and DB pins grounded.'ALS632A switching characteristics, Vee = 4.5 V to 5.5 V, eLfor SN54ALS632A, TA = 0 °e to 70 °e for SN74ALS632A50 pF, Tep.AIIenQ)(,)oSQ)CPARAMETERtpdtpdFROM TO SN54ALS632A SN74ALS632ATEST CONDITIONS(INPUT I (OUTPUll MIN MAX MIN MAXDB and CB ERR 51 =H. 50=L. RL=500 fl 10 43 10 40DB ERR 51 =L. 50=H. RL=500 fl 10 43 10 40DB and CB MERR 51 = H. 50 = L. RL = 500 fl 15 67 15 55DB MERR 51=L. 50=H. RL=500fl 15 67 15 55tpd 50~ and 51 ~ CB R1 =R2=500 fl 10 60 10 48tpLH SO~ and SU ERR RL = 500 fl 5 30 5 25tpd DB CB S 1 = L. SO = L. R 1 = R2 = 500 fl 10 60 10 48tpd LEDBO~ DB S1 =X. SO=H. R1 =R2=500 fl 7 35 7 30tpd S1i CB SO=H. R1 =R2=500 n 10 60 10 50ten OECB~ CB SO=H. 51 =X. R1 =R2=500 n 2 30 2 25tdis OECBf CB SO=H. S1 =X. R1 =R2=500 n 2 30 2 25ten OEBO thru OEB3~ DB SO=H. S1 =X, R1 =R2=500 n 2 30 2 25tdis OEBO thru OEB3f DB SO=H.S1=X.R1=R2= 500n 2 30 2 25UNITnsnsnsnsnsnsnsnsnsnsnsPRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments~~~:~~~~i~a{~:1~1e ~!~~~~ti~r fl\o::~:~it:r~~s notTEXAS -Ii}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-91

SN54ALS634. SN74ALS63432·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSWITH 3·STATE OUTPUTS'ALS634 switching characteristics, Vee = 4.5 V to 5.5 V, eLfor SN54ALS634, T A = 0 De to 70 De for SN74ALS63450 pF, TeIrC/)CCD

PRODUCTPREVIEWSN54ALS633, SN74ALS63332·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSWITH OPEN·COLLECTOR OUTPUTS'ALS633 electrical characteristics over recommended operating temperature range (unless otherwisenoted)PARAMETERTEST CONDITIONSSN54ALS633 SN74ALS633MIN Typt MAX MIN Typt MAXVIK Vcc = 4.5 V, II = -18 mA -1.5 -1.5 VVOH ERR or MERR Vce = 4.5 V to 5.5 V, IOH = -0.4 mA VCc- 2 VCC-2 V10H DB or CB VCC = 4.5 V, VOH = 5.5 V 0.1 0.1 mAVOLIIERR or MERRDB or CBVec = 4.5 V, 10L = 4 mA 0.25 0.4 0.25 0.4VCC = 4.5 V, 10L = 8 mA 0.35 0.5VCC = 4.5 V, 10L = 12 mA 0.250.4 0.25 0.4VCC = 4.5 V, 10L = 24 mA 0.35 0.550 or 51 VCC = 5.5 V, VI = 7 V 0.1 0.1All others VCC = 5.5 V, VI = 5.5 V 0.1 0.150 or 51 20 20IIH VCC = 5.5 V, VI = 2.7 V p.AAll others t 20 20IlL50 or 51 -0.4 -0.4VCC = 5.5 V, VI = 0.4 V mAAll otherst-0.1 -0.110§ ERR or MERR VCC = 5.5 V, Va = 2.25 V -30 -112 -30 -112 mAICC VCC = 5.5 V, 5ee Note 1 150 250 150 250 mAt All typical values are at VCC = 5 V, T A = 25°C.t For 1/0 ports, the parameters IIH and IlL include the off-state output current.§ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, 105.NOTE1: ICC is measured with 50 and 51 at 4.5 V and all CB ijnd DB pins grounded.'ALS633 switching characteristics, V CC = 4.5 V to 5. 5 V, CL = 50 pF, TC = - 55 °C to 125°Cfor SN54ALS633, TA = ooC to 70°C for SN74ALS633PARAMETERtpdtpdFROM TO SN54ALS633 SN74ALS633TEST CONDITIONS(INPUT) (OUTPUT) MIN MAX MIN MAXDB and CB ERR 51 =H, 50=L, RL=500 n 10 43 10 40DB ERR 51 =L, 50=H, RL=500n 10 43 10 40DB and CBMERR51 =H, 50=L, RL=500 n 15 67 15 5551 =L, 50=H, RL=500 n 15 67 15 55tpd 50L and 5U CB RL =680 n 10 75 10 60 nstpLH 50L and 5U ERR RL =500 n 5 30 5 25 nstpd DB CB 51 = L, 50 = L, RL = 680 n 10 70 10 60 nstpd LEDBOL DB 51 =X, 50=H, RL=680 n 15 70 15 50 nstpd 51i CB 50 = H, RL = 680 n 10 60 10 45 nstpLH OECBi CB 51 =X, 50=H, RL=680 n 2 35 2 30 nstpHL OECBL CB 51 =X, 50=H, RL=680 n 2 35 2 30 nstpLH OEBO thru OEB3i DB 51 =X, 50=H, RL=680 n 2 35 2 30 nstpHL OEBO thru OEB3L DB 51 = X, 50 = H, RL = 680 n 2 35 2 30 nsUNITVmAUNITnsnsfJI(/)Q)Co)'SQ)cen..JPRODUCT PREVIEW documents contain informationon products in the formative or design phase ofdevelopment. Characteristic data and otherspecifications are design goals. Texas InstrumentsTEXAS ..reserves the right to change or discontinue these INSTRUMENTSproducts without notice.POST OFFICE BOX 225012 • DALLAS. TEXAS 752652-93

SN54ALS635, SN74ALS63532·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSWITH OPEN·COLLECTOR OUTPUTSPRODUCTPREVIEWIIrOOCCD

SN54ALS632A, SN54ALS633 THRU SN54ALS635SN74ALS632A, SN74ALS633 THRU SN74ALS63532·81T PARALLEL ERROR 'DETECTION AND CORRECTION CIRCUITSI+--READ--4j_,4-4 ---------coRREcT----------~-II I I!4---'h(SI---+!Iso-lri--------------------------------------------~i ___________:~ tcorrection-------.t·104--'su(1I~'h(91----'" : ~'dis4DBO THRU DB31 -------~:==~~~~I~~~====I~~~~====:J(I:!~~~~~~~~~~~~~-----INPUT DATA WORD OUTPUT CORRECTED DATA WORDI14--'.n~mo THRU 0EB3II : ~I _________________________________ ~l4---'su(1I-----'-'h(91-tj14--' _I I I I dis .:CBOTHRUCB6-------{==:!IN~P~UT~C~H~E~CK~W~O~R~D====~ZE~~c:====)(==~O~U~TP~U~T!SY~N~D~R~OM~E~C~O~D~E==~~~ZZ~---l4--'en---.iiII!4---'pd~ERR 0' M d'NVALID000f Mr--------------V-A-L-,D-=E=R=R -FL-A-G-----------------...)00jMl(d)jfdi4 'pd _IFIGURE 1. READ. FLAG. AND CORRECT MODE SWITCHING WAVEFORMSDBO THRU DB7 ---

SN54ALS632A, SN54ALS633 THRU SN54ALS635SN74ALS632A, SN74ALS633 THRU SN74ALS63532·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSsoSlLj4--tsuISI--+j

PRODUCTPREVIEWSN54AS632, SN54AS634SN74AS632, SN74AS63432-811 PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS02661. JANUARY 1986-• Detects and Corrects Single-Bit Errorso Detects and Flags Dual-Bit Errors• Built-In Diagnostic Capability• Fast Write and Read Cycle ProcessingTimes• Byte-Write Capability ... 'AS632• Dependable Texas Instruments Quality andReliability -descriptionThe 'AS632 and 'AS634 devices are 32-bitparallel error detection and correction circuits(EDACs) in 52-pin (' AS632) or 48-pin (' AS634)600-mil packages. The EDACs use a modifiedHamming code to generate a 7-bit check wordfrom a 32-bit data word. This check word isstored along with the data word during thememory write cycle. During the memory readcycle, the 39-bit words from memory areprocessed by the EDACs to determine if errorshave occurred in memory.Single-bit errors in the 32-bit data word areflagged and corrected.Single-bit errors in the 7-bit check word areflagged, and the CPU sends the EDAC throughthe correction cycle even though the 32-bit dataword is not in error. The correction cycle willsimply pass along the original 32-bit data wordin this case and produce error syndrome bits topinpoint the error-generating location.Dual-bit errors are flagged but not corrected.These errors may occur in any two bits of the39-bit data word from memory (two errors in the32-bit data word, two errors in the 7-bit checkword, or one error in each word). The gross-errorcondition of all lows or all highs from memorywill be detected. Otherwise, errors in three ormore bits of the 39-bit word are beyond thecapabilities of these devices to detect.• AS632 ... JD PACKAGE(TOP VIEW)LEDBOVCCMERR 51ERRSODBaOB31OBlOB30OB2OB29OB3OB28OB4OB27OB5OB26OEBOOEB3OB6OB25OB7OB24GNOGNDOB8OB23OB9OB22OEBlOEB2OB10OB21OB11OB20OB12OB19OB13OB18OB14OB17OB15OB16CB6CBOCB5CB4OECB·AS632 ... FN PACKAGE(TOP VIEW)12i5N~Ocr:cr:cr: C"lC"lN~ 0 en uuU U CIl CIl CIl Icr: w ~ U U ~ 0 CIl CIl CIl U Uzzooow~~»~~ooozzI9 8 7 6 5 4 3 2 1 68 67 6665 64 63 62 61NC 10 60OB3 11 59OB4 12 58OB5 13 57OEOO ~ WOB6 15 55OB7 16 54GND 17 53GND 18 52OBB 19 51OB9 20 50OEBl 21 49OB10 22 48OBll 23 47OB12 24 46OB13 25 45OB14 26 442728293031323234353637383940414243tJ)Q)U'S;Q)cen...JNC - No internal connectionPRODUCT PREVIEW documents contain informationCopyright © 1986. Texas Instruments Incorporatedon products in the formative or design ~hase ofdevelopment. Characteristic data an~ otherspecifications are design goals. Texas Instruments/ TEXAS'"2-97reserves the right to change or discontinue these INSTRUMENlSproducts without notice.POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54AS632, SN54AS634SN74AS632, SN74AS63432·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSRead-modify-write (byte-control) operations can be performed with the' AS632 EDAC by using outputlatch enable, LEDBO, and the individual OEBO thru OEB3 byte control pins.Diagnostics are performed on the EDACs by controls and internal paths that allow the user to read thecontents of the DB and CB input latches. These will determine if the failure occurred in memory or in theEDAC.'AS634 ••• JD PACKAGE(TOP VIEW)'AS634 •.• FN PACKAGE(TOP VIEW)Ir-enCCD

SN54AS632, SN54AS634SN74AS632, SN74AS63432·811 PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSTABLE 2. PARITY ALGORITHMCHECK WORDBIT 31CBO XCBlCB2 XCB3CB4 XCB5 XCB6 X32-BIT DATA WORD30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0X X X X X X X X X X X X X X XX X X X X X X X X X X X X X X XX X X X X X X X X X X X X X XX X X X X X X X 'x X X X X X X XX X X X X X X X X X X X X X XX X X X X X X X X X X X X X XX X X X X X X X X X X X X X XThe seven check bits are parity bits derived from the matrix of data bits as indicated by "X" for each bit.error detection and correction detailsDuring a memory read cycle, the 7-bit check word is retrieved along with the actual data. In order to beable to determine whether the data from memory is acceptable to use as presented to the bus, the errorflags must be tested to determine if they are at the high level.EllThe first case in Table 3 represents the normal, no-error conditions. The EDAC presents highs on bothflags. The next two cases of single-bit errors give a high on MERR and a low on ERR, which is the signalfor a correctable error, and the EDAC should be sent through the~rection cycle. The last three casesof double-bit errors will cause the EDAC to signal lows on both ERR and MERR, which is the interruptindication for the CPU.f/)Q)TABLE 3. ERROR FUNCTION "5TOTAL NUMBER OF ERRORSERROR FLAGSQ)DATA CORRECTION32-BIT DATA WORD 7-BIT CHECK WORD ERR MERRo0 0 H H Not applicable1 0 L HenCorrection..oJ0 1 L H Correction1 1 L L Interrupt2 0 L L Interrupt0 2 L L InterruptError detection is accomplished as the 7-bit check word and the 32-bit data word from memory are appliedto internal parity generators/checkers. If the parity of all seven groupings of data and check bits are correct,it is assumed that no error has occurred and both error flags will be high.If the parity of one or more of the check groups is incorrect, an error has occurred and the proper errorflag or flags will be set low. Any single error in the 32-bit data word will change the state of either threeor five bits of the-7-bit check word. Any single error in the 7-bit check word changes the state of onlythat one bit. In either case, the single error flag (ERR) will be set low while the dual error flag (MERR) willremain high.Any two-bit error will change the state of an even number of check bits. The two-bit error is not correctablesince the parity tree can only identify single-bit errors. Both error flags are set low when any two-bit erroris detected.Three or more simultaneous bit errors can cause the EDAC to believe that no error, a correctable error,-or an uncorrectable error has occurred and will produce erroneous results in all three cases. It should benoted that the gross-error conditions of all lows and all highs will be detected.TEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-99

SN54AS632, SN54AS634SN74AS632, SN74AS63432·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSTABLE 4. READ. FLAG. AND CORRECT FUNCTIONDB CONTROLMEMORY EDAC CONTROLDB OUTPUT LATCHCBERROR FLAGSDATA 1/0 OEBn OR ('AS632) CHECK 1/0 CONTROLCYCLE FUNCTION S1 SOERR MERROEDBLEDBOOECBRead Read & flag H LLatch inputRead data & check H HbitsOutputRead corrected data H H& syndrome bitstSee Table 3 for error description.:j:See Table 5 for error location.InputLatchedinputdata, Outputcorrecteddata wordH X InputLatchedH L inputcheck wordOutputL X syndromebits:j:HHLEnabledtEnabledtEnabledtIrC/)CCD

SN54AS632, SN54AS634SN74AS632, SN74AS63432·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSTABLE 5. SYNDROME DECODINGSYNDROME BITSSYNDROME BITSSYNDROME BITSSYNDROME BITSERRORERRORERROR6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 543 2 1 0 6 5 4 3 2 1 0ERRORL L L L L L L unc L H L L L L L 2-bit H L L L L L L 2-bit H H L L L L L uncL L L L L L H 2-bit L H L L L L H unc H L L L L L H unc H H L L L L H 2-bitL L L L L H L 2-bit L H L L 'L H L DB7 H L L L L H L unc H H L L L H L 2-bitL L L L L H H unc L H L L L H H 2-bit H L L L L H H 2-bit H H L L L H H OB23L L L L H L L 2-bit L H L L H L L OB6 H L L L H L L unc H H L L H L L 2-bitL L L L H L H unc L H L L H L H 2-bit H L L L H L H 2-bit H H L L H L H OB22L L L L H H L unc L H L L H H L 2-bit H L L L H H L 2-bit H H L L H H L OB21L L L L H H H 2-bit L H L L H H H OB5 H L L L H H H unc H H L L H H H 2-bitL L L H L L L 2-bit L H L H L L L OB4 H L L H L L L unc H H L H L L L 2-bitL L L H L L H unc L H L H L L H 2-bit H L L H L L H 2-bit H H L H L L H OB20L L L H L H L DB31 L H L H L H L 2-bit H L L H L H L 2-bit H H L H L H L OB19L L L H L H H 2-bit L H L H L H H OB3 H L L H L H H OB15 H H L H L H H 2-bitL L L H H L L unc L H L H H L L 2-bit H L L H H L L 2-bit H H L H H L L OB18L L L H H L H 2-bit L H L H H L H OB2 H L L H H L H unc H H L H H L H 2-bitL L L H H H L 2-bit L H L H H H L unc H L L H H H L OB14 H H L H H H L 2-bitL L L H H H H OB30 L H L H H H H 2-bit H L L H H H H 2-bit H H L H H H H CB4L L H L L L L 2-bit L H H L L L L OBO H L H L L L L unc H H H L L L L 2-bitL L H L L L H unc L H H L L L H 2-bit H L H L L L H 2-bit H H H L L L H DB16L L H L L H L OB29 L H H L L H L 2-bit H L H L L H L 2-bit H H H L L H L uncL L H L L H H 2-bit L H H L L H H unc H L H L L H H OB13 H H H L L H H 2-bitL L H L H L L OB28 L H H L H L L 2-bit H L H L H L L 2-bit H H H L H L L OB17L L H L H L H 2-bit L H H L H L H OBl H L H L H L H OB12 H H H L H L H 2-bitL L H L H H L 2-bit L H H L H H L unc H L H L H H L OBll H H H L H H L 2-bitL L H L H H H OB27 L H H L H H H 2-bit H L H L H H H 2-bit H H H L H H H CB3L L H H L L L OB26 L H H H L L L 2-bit H L H H L L L 2-bit H H H H L L L uncL L H H L L H 2-bit L H H H L L H unc H L H H L L H OB10 H H H H L L H 2-bitL L H H L H L 2-bit L H H H L H L unc H L H H L H L OB9 H H H H L H L 2-bitL L H H L H H OB25 L H H H L H H 2-bit H L H H L H H 2-bit H H H H L H H CB2L L H H H L L 2-bit L H H H H L L unc H L H H H L L OB8 H H H H H L L 2-bitL L H H H L H OB24 L H H H H L H 2-bit H L H H H L H 2-bit H H H H H L H CB1L L H H H H L unc L H H H H H L 2-bit H L H H H H L 2-bit H H H H H H L CBOL L H H H H H 2-bit L H H H H H H CB6 H L H H H H H CB5 H H H H H H H noneCB X= error in check bit XDB Y= error in data bit Y2-bit = double-bit errorunc = uncorrectable multibit error•(J)Q)(J'SQ)cen..Jread-modify-write (byte control) operationsThe 'AS632 is capable of byte-write operations. The 39-bit word from memory must first be latched intothe OB and CB input latches. This is easily accomplished by switching from the read and flag mode (S 1 = H,SO = L) to the latch input mode (S1 = H, SO = H). The EOAC will then make any corrections, if necessary,to the data word and place it at the input of the output data latch. This data word must then be latchedinto the output data latch by taking LEOBO from a low to a high.Byte control can now be employed on the data word through the OEBO through OEB3 controls. OEBOcontrols OBO-OB7 (byte 0), OEB1 controls OB8-0B15 (byte 1), OEB2 controls OB16-0B23 (byte 2)' andOEB3 controls OB24-0B31 (byte 3). Placing a high on the byte control will disable the output and the usercan modify the byte. If a low is placed on the byte control, then the original byte is allowed to pass ontothe data bus unchanged. If the original data word is altered through byte control, a new check word mustbe generated before it is written back into memory. This is easily accomplished by taking control S 1 andSO low. Table 6 lists the read-modify-write functions.TEXAS -I!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-101

SN54AS632, SN54AS634SN74AS632, SN74AS63432·BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSlEIrC/)om

SN54AS632, SN54AS634SN74AS632, SN74AS63432-811 PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSTABLE 7. 'AS632 DIAGNOSTIC FUNCTIONCONTROLEDAC FUNCTIONS1 SORead & flag H LLatch input checkword while datainput latch remainstransparentLatch diagnosticdata word intoLLHHoutput latchLatch diagnosticdata word into H Hinput latchOutput diagnosticdata word & H Hsyndrome bitsOutput correcteddiagnostic dataword & outputH Hsyndrome bitsCONTROLEDAC FUNCTIONS1 SORead & flag H LLatch input checkbits while datainput latch remainsL HtransparentOutput inputcheck bitsLatch diagnosticdata intoLHHHinput latchOutput correcteddiagnostic H Hdata wordDB BYTE DB OUTPUT CBDATA 1/0 CONTROL LATCH CHECK 1/0 CONTROLInput correctdata wordInputOEBn LEDBO OECBHXInput correctcheck bitsLatchedERROR FLAGSERRMERRH H Hdiagnostic H L input H Enableddata word tcheck bitsInputOutput latchedLdiagnostic H H check bits Enabled-------- -----data word t Hi-ZHLatchedOutputinput syndrome LH H Enableddiagnosticbits--------- -----data word Hi-Z HOutputOutputsyndromeLdiagnostic L H Enabledbitsdata word -------- ----Hi-ZHOutputOutputcorrected syndrome LL L Enableddiagnosticbits------- ----data word Hi-Z HTABLE 8. 'AS634 DIAGNOSTIC FUNCTIONDATA 1/0Input correctdata wordInputdiagnosticdata word tDB CONTROL DB CONTROL ERROR FLAGSCHECK 1/0OEDBOECB ERR MERRHHInput correctcheck bitsLatched inputcheck bitsH H HHEnabledInputOutput inputdiagnostic H L Enableddata word tcheck bitsLatched inputOutputLdiagnostic H syndrome bits Enabled--------- -------data word Hi-Z HOutput correctedOutputLdiagnostic L syndrome bits Enabled-------- ---H----data wordHi-Z(J)Q)(,)"S;Q)cen...JtDiagnostic data is a data word with an error in one bit location except when testing the MERR error flag. In this case, the diagnostic dataword will contain errors in two bit locations.TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-103

ERROR~ ,SN54AS632, SN74AS63232·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSI AS632 logic diagram (positive logic)Irenc~

SN54AS634, SN74AS63432·81T PARALLEL ERROR DETECTIN AND CORRECTION CIRCUITSI AS634 logic diagram (positive logic)DECODERX/YI J SYNDROME0 ~--------------------------------~IGENERATOR0'"""'l ...._~.. ~I""SO - 1 31Sl - 2 3 ..... ,....2f-7 1;:;;'1 LL."---"':"'~-""I ~--=~4~ CHECK·BIT..--- GENERATOR ~(See Table 2)- C1CBO· .~ 7,CBG -_....--..-r--I10LATCHES~, 7"j~~OECB ---------01 ~ ENr

SN54AS632, SN54AS634SN74AS632, SN74AS63432-81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VInput voltage: eB and DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VAll others. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VOperating free-air temperature range:SN74AS632, SN74AS634 .................................. OOeto 70 0 eOperating case temperature range:SN54AS632, SN54AS634 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 °e to 125 °eStorage temperature range ......................................... - 65 De to 150 °erecommended operating conditions•r(J)CCDc::ri"CDt/)SN54AS632SN74AS632SN54AS634 SN74AS634 UNITMIN NOM MAX MIN NOM MAXVCC Supply voltage 4.5 5 5.5 4.5 5 5.5 VVIH High-level input voltage 2 2 VVIL Low-level input voltage 0.8 0.8 VIOHIOLHigh-level output currentLow-level output currentERR or MERR -0.4 -0.4DB or CB-1 -2.6ERR or MERR 4 8DB or CB12 24tw Pulse duration LEDBO low 25 25 ns(1) Data and check word before SOl(S1 =H)15 10tsuthSetup timeHold time(2) SO high before LED BOt (51 = H) t 45 45(3) LEDBO high before the earlier ofSO! or S1!t(4) LEDBO high before S11 (SO=H) 0 0(5) Diagnostic data word before S 1 1(SO=H)(6) Diagnostic check word before thelater of S1! or SOl(7) Diagnostic data word beforeLEDBOl (S1 =L and SO=H):I:015 1015 1025 20(8) Read-mode, SO low and S1 high 35 30(9) Data and check word after SOl(S1 =H)20 15(10) Data word after S11 (SO=H) 20 15(11) Check word after the later ofSHorSOl(12) Diagnostic data word afterLEDBOl (51 =L, SO=H):I:20 150 0tcorr Correction time (see Figure 1) 65 58 nsTC Operating case temperature -55 125 DCTA Operating free-air temperature 0 70 DC0mAmAnsnst These times ensure that corrected data is saved in the output data latch.:I: These times ensure that the diagnostic data word is saved in the output data latch.2-106TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54AS632, SN54AS634, SN74AS632, SN74AS63432·81T PARAllEL ERROR DETECTION AND CORRECTION CIRCUITSWITH 3·STATE OUTPUTS'AS632, 'AS634 electrical characteristics over recommended operating temperature range (unlessotherwise noted)SN54AS632SN74AS632PARAMETER TEST CONDITIONS SN54AS634 SN74AS634 UNITMIN Typt MAX MIN Typt MAXVIK VCC = 4.5 V, II = -18 mA -1.5 -1.5 VAll outputs Vce = 4.5 V to 5.5 V, IOH = -0.4 mA VCc- 2 VCC- 2VOHVOLIIIIHIlLDB or eBERR or MERRDB or CBVce = 4.5 V, IOH = -1 mA 2.4 3.3 VVCC = 4.5 V, 10H = -2.6 mA 2.4 3.2VCC = 4.5 V, 10H = 4 mA 0.25 0.4 0.25 0.4VCC = 4.5 V, 10L = 8 mA 0.35 0.5VCC = 4.5 V, 10L = 12 mA 0.25 0.4 0.25 0.4VCC = 4.5 V, 10L = 24 mA 0.35 0.5SO or 51 VCC = 5.5 V, VI = 7 V 0.1 0.1All others Vce = 5.5 V, VI = 5.5 V 0.1 0.1DB or CBt 20 20All others t VCC = 5.5 V, VI = 2.7 V /lA20 20SO or 51Vce = 5.5 V, VI = 0.4 V-0.4 -0.4mAAll others t -0.1 -0.110§ Vce = 5.5 V, Vo = 2.25 V -30 -112 -30 -112 mAICC VCC = 5.5 V, See Note 1 150 150 mANOTE 1: ICC is measured with SO and 51 at 4.5 V and all CB and DB pins grounded.'AS632 switching characteristics, Vee = 4.5 V to 5.5 V, eLfor SN54AS632, TA = ooe to 70 °e for SN74AS632PARAMETERtpdtpd50 pF, TeFROM TO SN54AS632 SN74AS632TEST CONDITIONS(INPUT) (OUTPUT) MIN Typt MAX MIN Typt MAXDB and eB ERR 51 = H, SO = L, RL = 500 n 17 17DB ERR 51 =L, 50=H, RL=500 n 17 17DB and CB MERR 51 =H, 50=L, RL =500 n 26 26DB MERR 51 =L, 50=H, RL=500 n 26 26tpd SOt and 51 t CB Rl =R2 =500 n 26 26 nstpLH sot and 51 t ERR RL = 500 n 9 9 nstpd DB CB 51 = L, SO = L, R 1 = R2 = 500 n 26 26 nstpd LEDBOt DB 51 =X, 50=H, Rl =R2=500 n 17 17 nstpd 5li CB 50-H, Rl -R2-500 n 26 26 nsten OECBt CB 50=H, Sl =X, Rl =R2=500 n 12 12 nstdis OECBf CB 50=H, 51 =X, Rl =R2=500 n 12 12 nsten OEBO thru OEB3t DB 50=H, 51 =X, Rl =R2=500 n 12 12 nstdis OEBO thru OEB3f DB SO=H, 51 =X, Rl =R2= 500 n 12 12 nsVmAUNITnsnsenQ)(.)oSQ)cen..Jt All typical values are at Vec = 5 V, T A = 25 DC.t For I/O ports, the parameters IIH and IlL include the off-state output current.§ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS·TEXAS -I.!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-107

SN54AS634, SN74AS63432·BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSWITH 3·STATE OUTPUTS'AS634 switching characteristics, Vee = 4.5 V to 5.5 V, eLfor SN54AS634, T A = ooe to 70 0 e for SN74AS63450 pF, TePARAMETERFROM TO SN54AS634TEST CONDITIONS(INPUT) (OUTPUT) MIN Typt MAXtpdDB and CBERR5.1 = H, 50 = L, RL = 500 fl 1751 =L, 50=H, RL=500 fl 17tpdDB and CB MERR51 =H, 50=L, RL=500 fl 2651 =L, 50=H, RL=500 fl 26tpd 50! and 51! CB R1 =R2=500 fl 23tpLH 50! and 51! ERR RL = 500 fl 9tpd DB CB 51 =L, 50=L, R1 =R2=500 fl 23tpd 51i CB 50=H, R1 =R2=500 fl 23ten OECS! CB 51 =X, 50=H, R1 =R2=500 fl 12tdis OECBt CB 51 =X, 50=H, R1 =R2=500 fl 12ten OEDB! DS 51 =X, 50=H, R1 =R2=500 fl 12tdis OEDBt DB 51 =X, 50=H, R1 =R2=500 fl 12It All typical values are at VCC = 5 V, T A = 25 ac.SN74AS634UNITMIN Typt MAX17ns1726ns2623 ns9 ns23 ns23 ns12 ns12 . ns12 ns12 ns2-108 TEXAS -1!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54AS632, SN54AS634SN74AS632, SN74AS63432·BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITSI4----READ-----+tt'4-4 ---------CORRECT-----------+ttlI, I14----'hIBI----+!so-lri--------------------------------------------~ __________~ tcorrection----------+4tl_·'uI1l~·hI9I_tor : ,_'d;,~DBa THRU DB31 -------~:==~~~~1~~~====1~~~~====~~1~~~~~~~~~~~1~~1~INPUT DATA WORD OUTPUT CORRECTED DATA WORD 1----Il4---'en--+lI, : ~I----------------------------------~OEBO THRU DEBJ~t'ulll~.hI91~r-'d;'~CBO THRU CB6 ~ INPUT CHECK WORD ~ OUTPUT SYNDROME CODE »»»»': l4--'en~: il4----'pd-+j '-----------------~ERR WW dINVALID~ Mr--------------V-A-L-ID.",E"'RR=-FL-A-G--------------.......... ~r.0r-;0..,07IN"7'} V'r.} k"'C,"'6)('707:~~i4--------.PdtlMeAR 0W".$J?,~&l(,b%00' 1#4r------------V-A-Ll-D=M=ER=R,...F-L-AG------------~)00(JJMD?0lFIGURE 1. READ. FLAG. AND CORRECT MODE SWITCHING WAVEFORMS14--- 'hIBI~so I ri------------------------------------~ISI~14-----READ tl4 CORRECT tl4 WRITEDBO THRU DB7 ~ INPUT DAT~ WORD~=OU~T~PU~T~C~O~R~RE~C~TE~D~D~A~TAj{~l~»~)~--~C~IN~P~U~T M~O~D~IF~IE~D~B~Y~TE~O~2>W>--~~DBB THRU DB15 INPUT DATA WORD OUTPUT CORRECTED DATA WORDDB16 THRU DB2J INPUT DATA WORD OUTPUT CORRECTED DATA WORDIIIenCl)o'S;Cl)cen..JDB24 THRU DBJI INPUT DATA WORD OUTPUT CORRECTED DATA WORD~ ____________________ ~ ____________ ~r____0EB2~ ______________________ ~----------~r----14--',uI21---+1~ ______________________ ~I ____________ ~r____f4-"',uIJI~LEDBO ~~~~~~,..,.~"""~"

IrC/)C(1)

• Independent Registers for A and B Buses• Multiplexed Real-Time and Stored DataooooChoice of True or Inverting Data PathsChoice of 3-State or Open-Collector OutputsIncluded Among the Package Options AreCompact 24-pin 300-mil Wide DIPs andBoth 28-pin Plastic and Ceramic ChipCarriersDependable Texas Instruments Quality andReliabilityDEVICE OUTPUT LOGIC'ALS646, 'AS646 3-State True'ALS647 Open-Collector True'ALS648, 'AS648 3-State Inverting'ALS649 Open-Collector InvertingdescriptionThese devices consist of bus transceiver circuits,with 3-state or open-collector outputs,. D-typeflip-flops, and control circuitry arranged formUltiplexed transmission of data directly fromthe data bus or from the internal storageregisters. Data on the A or B bus will be clockedinto the registers on the low-to-high transitionof the appropriate clock pin (CAB or CBA). Thefollowing examples demonstrate the fourfundamental bus-management functions thatcan be performed with the octal bus transceiversand registers.Enable (G) and direction (DIR) pins are providedto control the transceiver functions. In theSN54ALS646 THRU SN54ALS649. SN54AS646. SN54AS648SN74ALS646 THRU SN74ALS649. SN74AS646. SN74AS648OCTAL BUS TRANSCEIVERS AND REGISTERS02661, DECEMBER 19B3-NOVEMBER 1985SN54AlS', SN54AS' ... JT PACKAGESN74AlS', SN74AS' ... OW OR NT PACKAGECABSABDIRA1A2A3A4A5A6A7A8GND(TOP VIEW)VCCCBASBAGB1B2B3B4B5B6B7B8SN54ALS', SN54AS' ... FK PACKAGESN74AlS', SN74AS' ... FN PACKAGE(TOP VIEW)O:~~U ~;ii;iiO(J)UZ>U(J)4 3 2 1 28 27 26A1 25 GA2 6 24 81A3 23 82NC 8 22 NCA4 9 21 83A5 10 20 84A6 11 19 8512 13 14 15 1617 18NC - No internal connectiontransceiver mode, data present at the high-impedance port may be stored in either register or in both. Theselect controls (SAB and SBA) can mUltiplex stored and real-time (transparent mode) data. The circuitryused for select control will eliminate the typical decoding glitch which occurs in a multiplexer during thetransition between stored and real-time data. The direction control determines which bus will receive datawhen enable G is active (low). In the isolation mode (control G high), A data may be stored in one registerand/or B data may be stored in the other register.When an output function is disabled, the input function is still enabled and may be used to store and transmitdata. Only one of the two buses, A or B, may be driven at a time.The -1 versions of the SN74ALS' parts are identical to the standard versions except that the recommendedmaximum IOL is increased to 48 milliamperes. There are no -1 versions of the SN54ALS' parts.The SN54' family is characterized for operation over the full military temperature range of - 55°C to 125°C.The SN74' family is characterized for operation from O°C to 70°C.IIrnQ)(.)"S;Q)cen..oJPRODUCTION DATA documents contain informationcurrent as of puhlication date. Products conform tospecifications per the terms of Texas Instruments~~~~~:~~i~a{~~I~~~ ~!~:i~~ti~f :llo~:~:~:t:ros~s notTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1982, Texas Instruments Incorporated2-111

SN54ALS646 THRU SN54ALS649, SN54AS646, SN54AS648SN74ALS646 THRU SN74ALS649, SN74AS646, SN74AS648OCTAL BUS TRANSCEIVERS AND REGISTERS2-112 . TEXAS"INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54ALS646 THRU SN54ALS649, SN54AS646, SN54AS648SN74ALS646 THRU SN74ALS649, SN74AS646, SN74AS648OCTAL BUS TRANSCEIVERS AND REGISTERSFUNCTION TABL~INPUTSG DIR CAB CBA SAB SBAX X t X X XX X X t X XH X t t X XH X H or L HorL X XL L X X X LL L X H or L X HL H X X L XL H H or L X H XDATA 1/0OPERATION OR FUNCTION• ALS646 •• ALS647 • ALS648 •• ALS649A1 THRU A8 B1 THRU B8 'AS646 'AS648Input Unspecified t Store A. B unspecified t Store A. B unspecified tUnspecified t Input Store B. A unspecified t Stor~ B. A unspecified tInputInputStore A and B Data Store A and B DataIsolation. hold storage Isolation. hold storageOutputInputReal-Time B Data to A Bus Real-Time B Data to A BusStored B Data to A Bus Stored B Data to A BusInput OutputReal-Time A Data to B Bus Real-Time A Data to B BusStored A Data to B Bus Store A Data to B BustThe data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are alwaysenabled. i.e .• data at the bus pins will be stored on every low-to· high transition on the clock inputs.functional block diagrams (positive logic)• ALS646 •• AS646 •• ALS64 7• ALS648 •• AS648 •• ALS649fItJ)Q)to)'SQ)cen...J(201B1------------~v~------------TO 7 OTIiER CIiANNELSTO 7 OTHE: CHANNELSPin numbers shown are for DW. JT. and NT packages.TEXAS ~.INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-113

SN54ALS646 THRU SN54ALS649, SN54AS646, SN54AS648SN74ALS646 THRU SN74ALS649, SN74AS646, SN74AS648OCTAL BUS TRANSCEIVERS AND REGISTERSlogic symbols t'ALS646, 'AS646G (211G (211G3DIR (31 3 ENl IBA] DIR (313 EN2 lAB]CBA (231C4 CBA (231SBA (221 G5 SBA (221CAB (11 CAB (11SAB (21 SAB (71(41Al(201Bl(41AlG33 ENl IBAI3 EN2 IABIC4G5C6'ALS647(201BlIIr-VICCD

SN54ALS646, SN74ALS646OCTAL BUS TRANSCEIVERS AND REGISTERSWITH 3-STATE OUTPUTSabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VInput voltage: Control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VI/O ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VOperating free-air temperature range: SN54ALS646. . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°CSN74ALS646 .......................... O°C to 70°CStorage temperature range ..... .recommended operating conditionsSN54ALS646MIN NOM MAX MINSN74ALS646VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 VVIH High-level input voltage 2 2 VVIL Low-level input voltage 0.8 0.8 VIOH High-level output current -12 -15 mAIOLLow-level output currentNOMMAX12 2448 tfclock Clock frequency 0 35 0 40 MHztw Pulse duration, clocks high or low 14.5 12.5 nstsU" Setup time, A before CABt or B before CBAt 15 10 nsth Hold time, A after CABt or B after CBA t 0 0 nsTA Operating free-air temperature -55 125 0 70 °c (J)Q)tThe extended condition applies if VCC is maintained between 4.75 V and 5.25 V.CJThe 48-mA limit applies for the SN74ALS646-1 only. ":;Q)electrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)PARAMETERTEST CONDITIONSVIK VCC = 4.5 V, II = -18 mAVOHVCC = 4.5 V to 5.5 V, 10H = -0.4 mAVCC = 4.5 V,VCC = 4.5 V,VCC = 4.5 V,VCC = 4.5 V,10H = -3 mA10H = -12 mA10H = -15 mA10L = 12 mAVOL VCC = 4.5 V, 10L = 24 mA(IOL = 48 mA for - 1 version)IIIIHIlLControl inputs VCC = 5.5 V, VI = 7 VA or B ports VCC = 5.5 V, VI = 5.5 VControl inputsA or B portsSControl inputsA or B ports§VCC = 5.5 V,VCC = 5.5 V,VI = 2.7 VVI = 0.4 VIO~ VCC = 5.5 V, Vo = 2.25 Vl Outputs highICC VCC = 5.5 V I Outputs lowI Outputs disabledSN54ALS646MIN TYPl::tAli typical values are at VCC = 5 V, TA = 25°C§For 1/0 ports, the parameters IIH and IlL include the off-state output current.~The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.VCC- 22.4 3.22MAX-1.20.25 0.40.10.12020-0.2-0.2-30 -11247 7655 8855 88SN74ALS646MIN TYPl: MAX-1.2VCC-22.4 3.220.25 0.40.35 0.50.10.12020-0.2-0.2-30 -11247 7655 8855 88UNITmAUNITVVVmAJlAmAmAmACen..JTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-115

SN54ALS646, SN74ALS646OCTAL BUS TRANSCEIVERS AND REGISTERSWITH 3·STATE OUTPUTS'ALS646 switching characteristics (see Note 1)IIrOOo(I)!S.o(I)oPARAMETERFROM(INPUT)TO(OUTPUT)Vcc - 5 V. Vcc = 4.5 V to 5.5 V.CL - 50 pF. CL - 50 pF.R1 - 500 n. R1 - 500 n.R2 - 500 n. R2 - 500 n.TA - 25°C TA - MIN to MAX'ALS646 SN54ALS646 SN74ALS646MIN TYP MAX MIN MAX MIN MAXf max 50 35 40tpLH 20 25 10 35 10CBA or CAB A or BtpHL 11 15 5 20 5tpLH 11 17 5 22 5A or BB or AtpHL 7.5 10 3 15 3tpLH SBA or SABt 24 32 15 40 15A or BtpHL (with A or B high) 13 17 5 23 5tPLH SBA or SABt 17 22 8 30 8A or BtpHL (with A or Blow) 13 17 5 24 5tpZH10 15 3 20 3ITA or BtpZL 10 15 5 22 5tpHZ6 8 1 12 1GA or BtpLZ 10 13 2 20 2tpZH 22 28 10 38 10DIRA or BtpZL 14.5 20 5 30 5tpHZ 6 8 1 12 1DIRA or BtpLZ 10 13 2 21 2t These parameters are measured with the internal output state of the storage register opposite to that of the bus input ..NOTE 1: Load circuit and voltage waveforms are shown in Section 1.30172012352025201720101630251016UNITMHznsnsnsnsnsnsnsns2-116 TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54ALS647, SN74ALS647OCTAL BUS TRANSCEIVERS AND REGISTERSWITH OPEN·COLLECTOR OUTPUTSabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage. Vee ......................................................... 7 VInput voltage .............................................................. 7 VOperating free-air temperature range: SN54ALS647...... . . . . . . . . . . . . . . . .. - 55°C to 125°CSN7 4ALS64 7 ........................ " ooe to 70°CStorage temperature range ......................................... - 65°C to 150°Crecommended operating conditionsSN54ALS647SN74ALS647MIN NOM MAX MIN NOM MAXVCC Supply voltage 4.5 5 5.5 4.5 5 5.5 VVIH High-level input voltage 2 2 VVIL Low-level input voltage 0.8 0.8 VVOH High-level output voltage 5.5 5.5 VIOLLow-level output currentUNIT12 2448 t mAfclock Clock frequency 0 25 0 30 MHztw Pulse duration, clocks high or low 20 16.5 nstsu Setup time, A before CABT or B before CBA T 15 10 nsth Hold time, A after CABT or B after CBA T 0 0 nsTA Operating free-air temperature - 55 125 0 70 °ctThe extended condition applies if Vec is maintained between 4.75 V and 5.25 V.The 48-mA limit applies for the SN74ALS647-1 only.electrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)PARAMETERTEST CONDITIONSSN54ALS647 SN74ALS647MIN TVP~ MAX MIN Typt MAXVIK VCC = 4.5 V, II = -18 mA -1.2 -1.2 V.10H VCC = 4.5 V, VOH = 5.5 V 0.1 0.1 mAVCC = 4.5 V, 10L = 12 mA 0.25 0.4VOL VCC = 4.5 V, 10L = 24 mA V0.35 0.5(lOL = 48 mA for - 1 versions)IIIIHIlLICCA or B ports Vce = 5.5 V, VI = 7 V 0.1 0.1Control inputs Vee = 5.5 V, VI = 7 V 0.1 0.1A or ports~ 20 20Vee = 5.5 V, VI = 2.7 VControl inputs20 20Control inputsA or B ports§Vee = 5.5 V,Vee = 5.5 V10 All typical values are at Vee = 5 V, T A = 25 ac§For 1/0 ports, the parameters IIH and IlL include the off-state output current.VI = 0.4 V-0.2 -0.2-0.2 -0.2I Outputs high 35 60 35 60I Outputs low40 65 40 65UNITmAp.AmAmAEJIenQ)o"S:Q)cCJ)...JTEXAS -1!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-117

SN54ALS647, SN74ALS647OCTAL BUS TRANSCEIVERS AND REGISTERSWITH OPEN·COLLECTOR OUTPUTS, ALS64 7 switching characteristics (see Note 1)PARAMETERFROM(INPUT)TO(OUTPUT)Vcc - 5 V. Vec - 4.5 V to 5.5 V.CL - 50 pF. CL - 50 pF.RL - 680 n. RL - 680 n.TA - 25 c C TA ~ MIN to MAX'ALS647 SN54ALS647 SN74ALS647MIN TYP MAX MIN MAX MINf max 40 25 30tpLH 38 50 19 72 19CBA or CABA or BtpHL 12 20 6 24 6tpLH 35 39 17 70 17A or BBorAtpHL 10 13 4 19 4tPLH SBA or SABt 40 51 20 72 20A or BtpHL (with A or B high) 12 17 6 26 6tpLH SBA or SABt 40 51 20 72 20A or BtpHL (with A or Blow) 12 17 6 26 6tpLH20 27 10 37 10GA or BtpHL 10 15 2 20 2tpLH 20 25 9 34 9DIRA or BtPHL 13 17 2 22 2MAX582254166022602231172919UNITMHznsnsnsnsnsnsrenc(1)

SN54ALS648, SN74ALS648OCTAL BUS TRANSCEIVERS AND REGISTERSWITH 3·STATE OUTPUTSabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VInput voltage: Control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VI/O ports ..................................... , . . . . . . . . . . . . . .. 5.5 VOperating free-air temperature range: SN54ALS648. . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°CSN74ALS648 ........................ " O°C to 70°CStorage temperature range ..................... .recommended operating conditionsSN54ALS648SN74ALS648MIN NOM MAX MIN NOM MAXVee Supply voltage 4.5 5 5.5 4.5 5 5.5 VVIH High-level input voltage 2 2 VVIL Low-level input voltage 0.8 0.8 V10H High-level output current -12 -15 mA10LLow-level output currentUNIT12 2448 t mAfclock elock frequency 0 35 0 40 MHztw Pulse duration, clocks high or low 14.5 12.5 nstsu Setup time, A before eABt or B before eBAt 15 10 nsth Hold time, A after eABt or B after eBAt 0 0 nsTA Operating free-air temperature -55 125 0 70 °etThe extended conditon applies if Vec is maintained between 4.75 V and 5.25 V.The 48-mA limit applies for the SN74ALS648-1 only.electrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)PARAMETERTEST CONDITIONSSN54ALS648MIN Typt MAXSN74ALS648MIN Typt MAXVIK Vec = 4.5 V, II = -18 mA - 1.2 -1.2 VVec = 4.5 V to 5.5 V, 10H = -0.4 mA vCC- 2 VCC-2VOHVee = 4.5 V, 10H = -3 mA 2.4 3.2 2.4 3.2Vee = 4.5 V, 10H = -12 mA 2Vce = 4.5 V, 10H = -15 mA 2Vee = 4.5 V, 10L = 12 mA 0.25 0.4 0.25 0.4VOL Vee = 4.5 V, 10L = 24 mA V'0.35 0.5(IOL = 48 mA for - 1 version)IIIIHIlLControl inputs Vee = 5.5 V, VI = 7 V 0.1 0.1A or B ports Vee = 5.5 V, VI = 5.5 V 0.1 0.1Control inputs 20 20Vec = 5.5 V, VI = 2.7 V /lAA or B ports§20 20Control inputs -0.2 -0.2Vee = 5.5 V, VI = 0.4 V mAA or B ports§-0.2 -0.210' Vee = 5.5 V, Vo = 2.25 V - 30 -112 -30 -112 mAI Outputs high 47 76 47 76lec Vec = 5.5 V I Outputs low 57 88 57 88 mAI Outputs disabled 57 88 57 88UNITVmAenCDCJ'SCDCCJ)..Jt All typical values are at Vee = 5 V, T A = 25°e§For 1/0 ports, the parameters IIH and IlL include the off-state output current.'The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-119

SN54ALS648, SN74ALS648OCTAL BUS TRANSCEIVERS AND REGISTERSWITH 3·STATE OUTP.UTS, ALS648 switching characteristics (see N~te 1)IrenPARAMETERf maxtpLHtpHLtpLHtpHLtPLHtpHLFROM(INPUT!CBA or CABAorBSBA or SABt(with A or B high)TO(OUTPUT!A or BB or AA or BVcc - 5 V. VCC - 4.5 V to 5.5 V.CL - 50 pF. CL - 50 pF.R1 - 500 n. R1 - 500 n.R2 - 500 n. R2 - 500 n.TA - 25°C TA - MIN to MAX'ALS648 SN54ALS648 SN74ALS648MIN TVP MAX MIN MAX MIN MAXtpLHSBA or SABt16 22 6 30 625A or BtpHL(with A or Blow)14 19 6 25 6 .21tpLH12 18 4 25 422ITA or BtpHL12 18 4 25 422tpLH5 8 1 12 110ITA or BtpHL7 12 2 21 215tpZH14 22 4 35 427DIRA or BtpZL10 17 3 25 319tPHZ7 12 1 17 114DIRA or BctpLZ7 13 2 22 215~< t These parameters are measured with the internal output state of the storage register opposite to that of the bus input.n" NOTE 1: Load circuit and voltage waveforms are shown in Section 1.~en502113106241535 4029 8 39 818 5 23 515 3 20 38 2 12 232 5 44- 521 4 26 4332017103922UNITMHznsnsnsnsnsnsnsns2-120 TEXAS "'-!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54ALS649, SN74ALS649OCTAL BUS TRANSCEIVERS AND REGISTERSWITH OPEN·COLLECTOR OUTPUTSabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, Vee .............................................. " . . . . . . . .. 7 VInput voltage .............................................................. 7 VOperating free-air temperature range: SN54ALS649. . . . . . . . . . . . . . . . . . . . . .. - 55 °e to 125°eSN74ALS649 .......................... ooe to 70 0 eStorage temperature range ......................................... - 65 °e to 150 °erecommended operating conditionsSN54ALS649SN74ALS649MIN NOM MAX MIN NOM MAXVCC Supply voltage 4.5 5 5.5 4.5 5 5.5 VVIH High-level input voltage 2 2 VVIL Low-level input voltage 0.8 0.8 VVOH High-level output voltage 5.5 5.5 VIOLLow-level output currentUNIT12 2448 t mAfclock Clock frequency 0 25 0 30 MHztw Pulse duration, clocks high or low 20 16.5 nstsu Setup time, A before CABT or B before CBA T 15 10 nsth Hold time, A after CABT or B after CBA T 0 0 nsTA Operating free-air temperature -55 125 0 70 DCtThe extended condition applies if VCC is maintained between 4.75 V and 5.25 V.The 48-mA limit applies for the SN74ALS649-1 only.electrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)PARAMETERTEST CONDITIONSSN54ALS649SN74ALS649MIN TYP:t MAX MIN TYP:t MAXVIK VCC = 4.5 V, II = -18 mA -1.2 -1.2 V10H Vec = 4.5 V, VOH = 5.5 V 0.1 0.1 mAVCC = 4.5 V, 10L = 12 mA 0.25 0.4VOL VCC = 4.5 V, IOL = 24 mA V0.35 0.5(IOL = 48 mA for - 1 versions)IIIIHIlLICCA or B ports VCC = 5.5 V, VI = 7 V 0.1 0.1Control inputs Vec = 5.5 V, VI = 7 V 0.1 0.1A or ports§ 20 20VCC = 5.5 V, VI = 2.7 VControl inputs20 20Control inputsA or B ports§VCC = 5.5 V,VCC = 5.5 VtAil typical values are at Vce = 5 V, TA = 25 D C§For I/O ports, the parameters IIH and IlL include the off-state output current.-0.2 -0.2VI = 0.4 V-0.2 -0.2I Outputs hi\)h 40 60 40 60I Outputs low 45 70 45 70UNITmAf.lAmAmAIItnQ)(,)"S;Q)cen..oJTEXAS -1.!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-121

SN54ALS649, SN74ALS649OCTAL BUS TRANSCEIVERS AND REGISTERSWITH OPEN·COLLECTOR OUTPUTS, ALS649 switching characteristics (see Note 1)IIrmcCD

SN54AS646, SN54AS648, SN74AS646, SN74AS648OCTAL BUS TRANSCEIVERS AND REGISTERSWITH 3·STATE OUTPUTSabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, Vcc ........................................................ , 7 VInput voltage: Control inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VI/O ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . .. 5.5 VOperating free-air temperature range: SN54AS646, SN54AS648 ............ , - 55°C to 125°CSN74AS646, SN74AS648 ................ O°C to 70°CStorage temperature range ......................................... - 65°C to 150°Crecommended operating conditionsSN54AS646SN54AS648SN74AS646SN74AS648MIN NOM MAX MIN NOM MAXVCC Supply voltage 4.5 5 5.5 4.5 5 5.5 VVIH High-level input voltage 2 2 VVIL Low-level input voltage 0.8 0.8 V10H High-level output current -12 -15 rnA10L Low-level output current 32 48 rnAfclock Clock frequency 0 75 0 90 MHzI Clock high 6 5tw Pulse duration nsI Clock high 7 6tsu Setup time, A before CABl or B before CBAl 7 6 nsth Hold time, A after CABl or B after CBM 0 0 nsenTA Operating free-air temperature -55 125 0 70 °c Q)CJelectrical characteristics over recommended operating free-air temperature range (unless otherwisenoted) . Q)PARAMETERTEST CONDITIONSVIK VCC = 4.5 V, II = -18 mAVOHVOLIIIIHIlLVCC = 4.5 V to 5.5 V, 10H = -2 rnAVCC = 4.5 V,10H = -3 mAVCC = 4.5 V,VCC = 4.5 V,VCC = 4.5 V,10H = -12 rnA10H = -15 mA10L = 32 mAVCC = 4.5 V,10L = 48 rnAControl inputs VCC = 5.5 V, VI = 7 VA or B ports VCC = 5.5 V, VI = 5.5 VControl inputsA or B ports i VCC = 5.5 V, VI = 2.7 VControl inputsA or B portsSVCC = 5.5 V,VI = 0.4 V10§ VCC = 5.5 V, Va = 2.25 VICC'AS646'AS648VCC = 5.5 VOutputs highOutputs lowOutputs disabledOutputs highOutputs lowOutputs disabledSN54AS646SN54AS648MIN Typt MAX-1.2vcc- 22.4 3.220.25 0.500.10.12070-0.5-0.75-30 -112120 195130 211130 211110 185120 195120 195SN74AS646SN74AS64BMIN Typt MAX-1.2VCC- 22.4 3.2tAli typical values are at Vcc = 5 V, TA = 25°CiFor I/O ports, the parameters IIH and IlL include the off-state output current.§The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.20.35 0.500.10.12070-0.5-0.75-30 -112120 195130 211130 211110 185120 195120 195UNITUNITVVVmAJlArnAmAmAoSCen...ITEXAS -I.!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-123

SN54AS646, SN54AS648, SN74AS646, SN74AS648OCTAL BUS TRANSCEIVERS AND REGISTERSWITH 3·STATE OUTPUTS, AS646 switching characteristics (see Note 1)IrenPARAMETERfmaxtPLHtpHLtpLHtpHLtPLHtpHLtPZHtpZLtpHZtpLZtpZHtpZLtpHZtPLZFROM(lNPUnCBA or CABA or BSBA or SABtGGDIRDIRTO(OUTPUT)A or BB or AA or BA or BA or BA or BA or Bc ' AS648 switching characteristics (see Note 1)C»

SN54ALS651 THRU SN54ALS654, SN54AS651, SN54AS652SN74ALS651 THRU SN74ALS654, SN74AS651, SN74AS652OCTAL BUS TRANSCEIVERS AND REGISTERSD2661, DECEMBER 1 9B3 - REVISED NOVEMBER 19B5• Bus Transceivers/Registers• Independent Registers and Enables for A andB Buses• Multiplexed Real-Time and Stored Data• Choice of True and Inverting Data Paths• Choice of 3-State or Open-Collector Outputsto A Bus• Included Among the Package Options AreCompact 24-Pin 300-mil-Wide DIPs andBoth 28-Pin Plastic and Ceramic ChipCarriers• Dependable Texas Instruments Quality andReliabilitySN54ALS'. SN54AS' , .. JT PACKAGESN74ALS·. SN74AS' ... OW OR NT PACKAGECABSABGABA1A2A3A4A5A6A7A8GNDITOP VIEW)VCCCBASBAGBAB1B2B3B4B5B6B7B8DEVICE A OUTPUT B OUTPUT LOGIC'ALS651, 'AS651 3-State 3-State Inverting'ALS652, 'AS652 3-Statc 3-State True'ALS653 Open-COllector 3-State Inverting'ALS654 Open-Collector 3·State TruedescriptionThese devices consist of bus transceiver circuits,D-type flip-flops, and control circuitry arrangedfor multiplexed transmission of data directly fromthe data bus or from the internal storageregisters. Enable GAB and GBA are provided tocontrol the transceiver functions. SAB and SBAcontrol pins are provided to select whether realtimeor stored data is transferred. The circuitryused for select control will eliminate the typicaldecoding glitch which occurs in a multiplexerduring the transition between stored and realtimedata. A low input level selects real-timedata, and a high selects stored data. Thefollowing examples demonstrate the fourfundamental bus-management functions thatcan be performed with the octal bus transceiversand registers.SN54ALS·. SN54AS' ... FK PACKAGESN74ALS·. SN74AS' ... FN PACKAGE(TOP VIEW)co coco U

SN54ALS651 THRU SN54ALS654, SN54AS651, SN54AS652SN74ALS651 THRU SN74ALS654, SN74AS651, SN74AS652OCTAL BUS TRANSCEIVERS AND REGISTERSGAB GBA CAB CBA SAB SBA GABL L X X X L H'-...-'GBA CAB CBA SABH X X LSBAX•r-encCD~.0CD(J)GABXLLREAL-TIME TRANSFERBUS B TO BUS A'--.r--'GBA CAB CBA SAB SBA GABH t X X XHX X X XH t t X XSTORAGE FROMA AND/OR BREAL- TIME TRANSFERBUS A TO BUS B~GBA CAB CBA SABL HorL HorL HTRANSFERSTORED DATATO A AND/OR BSBAH2-126TEXAS ..Jj}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54ALS651 THRU SN54ALS654, SN54AS651, SN54AS652SN74ALS651 THRU SN74ALS654, SN74AS651, SN74AS652OCTAL BUS TRANSCEIVERS AND REGISTERSFUNCTION TABLEINPUTS-GAB GBA CAB CBA SAB SBAL H H or L H or L X XL H X XX H H or L X XH H xt XL X H or L X XL L X X+L L X X X LL L X H or L X HH H X X L XH H HorL X H XH L H or L H or L H HDATA I/OOPERATION OR FUNCTION'ALS651, 'ALS653 'ALS652, 'ALS654A1 THRU A8 B1 THRU B8 'AS651 'AS652IsolationIsolationInputInputStore A and B Data Store A and B DataInput Unspecified t Store A, Hold B Store A, Hold BInput Output Store A in both registers Store A in both registersUnspecified t Input Hold A, Store B Hold A, Store BOutput Input Store B in both registers Store B in both registersReal-Time B Data to A Bus Real-Time B Data to A BusOutputInputStored B Data to A Bus Stored B Data to A BusReal-Time A Data to B Bus Real-Time A Data to B BusInput OutputStored A Data to B Bus Stored A Data to B BusStored A Data to B Bus and Stored A Data to B Bus andOutput OutputStored B Data to A Bus Stored B Data to A BustThe data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data input functions are alwaysenabled, i.e., data at the bus pins will be stored on every low-to-high transition on the. clock inputs.tSelect control L: clocks can occur simultaneously.Select control = H: clocks must be staggered in order to load both registers.logic diagrams (positive logic)'A LS651, ' AS651, 'A LS653'ALS652, 'AS652, 'ALS654enQ)(.)oS;cQ)en...J(201+-+-+-7--

SN54ALS651 THRU SN54ALS654, SN54AS651, SN54AS652SN74ALS651 THRU SN74ALS654, SN74AS651, SN74AS652OCTAL BUS TRANSCEIVERS AND REGISTERSlogic symbols t'ALS651, 'AS651'ALS652, 'AS652GBA (211ENI IBAIGBA (211GAB (31 EN21ABI GAB (31CBA 1231 C4 CBA (231SBA 1221 G5 SBA (221CAB 111 C6 CAB (11SAB 121 SAB (21ENllBAIEN21ABIC4G5C6Al1411201BlAl141(201Bl151 1191 (51A2 B2 A2(191B2161 11S1 161A3 B3 A3(1S1B3171 1171 171A4 B4 A4(171B4IIr-VJ(SI 1161 lSIA5 B5 AS191 1151 (91A6 B6 A6(101 1141 (101A7 B7 A71111 1131 (IllAS BS AS(161B5(151B6(141B7(131BSCCD

SN54ALS651, SN54ALS652, SN74ALS651, SN74ALS652OCTAL BUS TRANSCEIVERS AND REGISTERSabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, VCC ... : ........................................................... 7 VInput voltage: Control inputs .......................................................... 7 VI/O ports .................... ',' ...................................... 5.5 VOperating free-air temperature range: SN54ALS651, SN54ALS652 ..................... - 55°C to 125°CSN74ALS651,SN74ALS652 ........................ OOCt070oCStorage temperature range ................................................. - 65°C to 1 50°Crecommended operating conditionsSN54ALS651SN74ALS651SN54ALS652 SN74ALS652 UNITMIN NOM MAX MIN NOM MAXVee Supply voltage 4.5 5 5.5 4.5 5 5.5 VVIH High-level input voltage 2 2 VVIL Low-level input voltage 0.8 0.8 V10H High·level output current -12 -15 mA10LLow·level output current12 24fclock elock frequency 0 35 0 40 MHzCBA or CAB high 14.5 12,5twPulse durationnsCBA or CAB low 14.512.5tsu Setup time before CABi or eBAi A or B 15 10 risth Hold time after CABi or eBAi A or B 5 0 nsTA Operating free·air temperature -55 125 0 70 aetThe extended condition applies if Vec is maintained between 4.75 V and 5.25 V. The 48-mA limit applies for the SN74ALS651 -1and SN74ALS652 -1 only.electrical characteristics ovor recommended operating free-air temperature range (unless otherwise noted)SN54ALS651SN74ALS651PARAMETER TEST CONDITIONS SN54ALS652 SN74ALS652 UNIT48tMIN Typi MAX MIN Typi MAXVIK Vce = 4.5 V, II = -18 mA -1.2 -1.2 VVCC = 4.5 V to 5.5 V, 10H = -0.4 mA VCC-2 VCC-2VOHVCC = 4.5 V, 10H = -3 mA 2.4 3.2 2.4 3.2VCC = 4.5 V,10H = -12 mAVCC = 4.5 V, 10H = -15 mA 2Vec = 4.5 V, 10L = 12 mA 0.25 0.4 0.25 0.4VOL Vee = 4.5 V, 10L = 24 mA 0.35 0.5 V(lOL = 48 mA for -1 versions)IIIIHIlLControl inputs Vec = 5.5 V, VI = 7 V 0.1 0.1A or B ports VCC = 5.5 V,VI = 5.5 V0.1 0.1Control inputs 20 20Vee = 5.5 V,VI = 2.7 VA or B ports§20 20Control inputs -0.2 -0.2A or B ports§-0.2 -0.2Vec = 5.5 V, VI = 0.4 V mA10' Vce = 5.5 V, Vo = ,2.25 V -30 -112 -30 -112 mAOutputs high 42 68 42 68'ALS651 Outputs low 52 82 52 82Outputs disabled 52 82 52 82lee Vee = 5.5 V mAOutputs high 47 76 47 76'ALS652 Outputs low 55 88 55 882Outputs disabled 55 88 55 88tAli typical values are at VCC = 5 V,T A = 25 ac.§For I/O ports, the parameters IIH and IlL include the off·state output current.~ The output conditio[1s have been chosen to produce a current that closely approximates one half of the true short·circuit output current, lOS·PRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments~~~~~:~~i~ai~:I~~i ~!=~:~ti:r :1~o::::~:t:~~S notTEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265mAVmA",A2-129t/)Q)(,)oS;cQ)en...J

SN54ALS651, SN54ALS652, SN74ALS651, SN74ALS652OCTAL BUS TRANSCEIVERS AND REGISTERS'ALS651 switching characteristics (see Note 1)r(J)Vcc - 5 V.CL - 50 pF.R1 - 500 n.FROMTOPARAMETER R2 - 500 n.(INPUT!(OUTPUT)TA - 25°Cf maxtpLHtpHLtpLHtPHLtpLHtpHLtpLHtPHLtpZHtpZLtpHZtPLZtpZHtpZLtpHZCBA or CABA or BSBA or SABt(with A or B high)SBA or SABt(with A or Blow)GBAGBAGABGABA or BB or AA or BA or BtpLZC~ 'ALS652 switching characteristics (see Note 1)C:;"CDenPARAMETERFROM(INPUT!AABBTO(OUTPUT)'ALS651Vcc - 4.5 V to 5.5 V.CL - 50 pF.R1 - 500 n.R2 - 500 n.rTA - MIN to MAXSN54ALS651SN74ALS651MIN TYP MAX MIN MAX MIN MAX5035 4020 27 10 38 10 3211 15 5 21 5 179 13 4 20 4 185 8 2 12 2 1024 31 13 45 13 3813 18 7 25 7 2115 20 8 30 8 2513 18 7 25 7 2112 16 5 22 5 2011 15 5 21 5 184 7 2 10 2 97 10 3 16 3 1214 19 7 25 7 2213 18 7 25 7 215 10 2 14 2 127 10 2 20 2 14VCC - 5 V.CL - 50 pF.R1 - 500 n.R2 - 500 n.VCC - 4.5 V to 5.5 V.CL - 50 pF.R1 - 500 n.R2 - 500 n.TA - 25°CTA - MIN to MAX'ALS652 SN54ALS652 SN74ALS652MIN TYP MAX MIN MAX MIN MAXf max 50 35 40tpLH20 25 10 35 1030CBA or CABA or BtpHL 11 15 5 20 517tpLH 11 15 5 20 518A or BB or AtpHL 8 10 3 15 312tpLH SBA or SABt 24 32 15 40 1535A or BtPHL (with A or B high) 13 17 6 23 620tpLH SBA or SABt 17 22 8 30 825A or BtpHL (with A or Blow) 13 17 5 24 520tpZH10 15 3 20 317GBAAtpZL 10 14 5 22 518tpHZ6 8 1 12 110GBAAtpLZ 10 13 2 20 216tpZHGAB-----B15 20 8 25 82_2tpZL 12 16 6 21 618tpHZ6 8 1 12 110GABBtpLZ 10 13 2 21 216t These parameters are measured with the Internal output state of the storage register opposite to that of the bus Input.NOTE 1: Load circuit and voltage waveforms are shown in Section 1.PRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments2-130 ~~~~~:~~i~ai~:I~~~ ~!:~~~ti:f ~Io::~:~:t:~~s notTEXAS l!}INSTRUMENTSPOST OFFICE BOX 225012 • OALLAS. TEXAS 75265UNITMHznsnsnsnsnsnsnsnsUNITMHznsnsnsnsnsnsnsns

PRODUCTPREVIEWSN54ALS653, SN54ALS654, SN74ALS653, SN74ALS654OCTAL BUS TRANSCEIVERS AND REGISTERSabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, Vee ............................................................... 7 VInput voltage: All inputs and A 110 ports ................................................... 7 VB 110 ports ........................................................... 5.5 VOperating free-air temperature range: SN54ALS653, SN54ALS654 ........... ; ......... - 55 °e to 125 °eSN74ALS653,SN74ALS654 ........................ OOeto70oeStorage temperature range ................................................. - 65 °e to 150 °erecommended operating conditionsSN54ALS653SN74ALS653SN54ALS654 SN74ALS654 UNITMIN NOM MAX MIN NOM MAXVCC Supply voltage 4.5 5 5.5 4.5 5 5.5 VVIH High-level input voltage 2 2 VVIL Low-level input voltage 0.8 0.8 VVOH High-level output voltage A ports 5.5 5.5 VIOH High-level output current B ports -12 -15 rnAIOLLow-level output current12 244Stfclock Clock frequency MHztwPulse durationCBA or CAB highCBA or CAB lowtsu Setup time before CABi or CBAi A or B nsth Hold time after CABi or CBAi A or B nsTA Operating free-air temperature -55 125 0 70 °c•tThe extended condition applies if VCC is maintained between 4.75 V and 5.25 V. The 48-mA limit applies for the SN74ALS653-1and SN74ALS654-1 only.rnAnsen(1)(.)'>(1)C(Jl...JPRODUCT PREVIEW documents contain informationon products in the formative or design !lhase ofdevelopment. Characteristic data and otherspecifications are design goals. Texas Instrumentsreserves the right to change or discontinue theseproducts without notice.TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-131

SN54ALS653, SN54ALS654, SN74ALS653, SN74ALS654OCTAL BUS TRANSCEIVERS AND REGISTERSPRODUCTPREVIEWIrmC(1)

PRODUCTPREVIEWSN54ALS653, SN74ALS653OCTAL BUS TRANSCEIVERS AND REGISTERS, ALS653 switching characteristics (see Note 1)PARAMETERFROM(INPUT)TO(OUTPUT)SN54ALS653Vcc = 4.5 V to 5.5 V.CL = 50 pF.RL = 680 Q. (A outputs)R1 = R2 = 500 Q. (B outputs)TA = MIN to MAXSN74ALS653MIN Typt MAX MIN Typt MAXf maxtpLH 24 24CBAAtpHL 15 15tpLH 11 11CABBtpHL 13 13tpLH10 10ABtpHL 12 12tpLH 24 24BAtpHL 10 10tpLH SBA+ 26 26AtpHL (with B high) 15 15tPLH SBA+ . 26 26AtpHL (with Blow) 15 15tpLH SAB+ 16 16BtPHL (with A high) 16 16tpLH SAB+ 15 15BtPHL (with A low) 15 15tpLH24 24GBAAtpHL 17 17tpZH 19 19GABBtpZL 22 22tpHZ 12 12GABBtpLZ 14 14t All typical values are at VCC = 5 V. T A = 25°C.+ These parameters are measured with the internal outp'ut state of the storage register opposite to that of the bus input.NOTE 1: Load circuit and voltage waveforms are shown in Section 1.UNITMHznsnsnsnsnsnsnsnsnsnsnsenQ)oos:Q)cen...JAdditional information on these products can be obtained from the factory as it becomes available.PRODUCT PREVIEW documents contain informationon products in the formative or design phase ofdevelopment. Characteristic data and otherspecifications are design goals. Texas Instrumentsreserves the right to change or discontinue these INSTRUMENTSproducts without notice.POST OFFICE BOX 225012 • DALLAS. TEXAS 75265TEXAS -1!12-133

SN54ALS654, SN74ALS654OCTAL BUS TRANSCEIVERS AND REGISTERSPRODUCTPREVIEW, ALS6 54 switching characteristics (see Note 1)IIPARAMETERf maxtPLHtpHLFROM(INPUT)CBATO(OUTPUT)ASN54ALS654Vcc = 4.5 V to 5.5 V,CL = 50 pF,RL = 680 Q, (A outputs)R1 = R2 = 500 Q, (B outputs)TA = MIN to MAXSN74ALS654MIN Typt MAX MIN Typt MAX24 2415 15tpLH11 11CABBtpHL13 13tpLH8 8ABtpHL 8 8tPLH 24 24BAtpHL10 10tpLH SBAt 26 26AtPHL(with B high) 15 15tpLH SBAt 26 26AtpHL(with Blow) 15 15tPLH SBAt 16 16BtPHL(with A high)16 16tPLH SABt 15 15BtPHL(with A low) 12 12tpLH24 24GBAAtpHL17 17tpZHtpZLtpHZtpLZGABGABBB19 1922 2212 1214 14t All typical values are at VCC = 5 V, T A = 25°C.t These parameters are measured with the internal output state of the storage register opposite to that of the bus input.NOTE 1: Load circuit and voltage waveforms are shown in Section 1.UNITMHznsnsnsnsnsnsnsnsnsnsnsAdditional information on these products can be obtained from the factory as it becomes available.PRODUCT PREVIEW documents contain informationon products in the formative or design ~hase ofdevelopment. Characteristic data and otherTEXAS ..2-134 specifications are design goals. Texas Instrumentsreserves the right to change or discontinue these INSTRUMENTSproducts without notice.POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54AS651, SN54AS652, SN74AS651, SN74AS652OCTAL BUS TRANSCEIVERS AND REGISTERSabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, VCC ............................................................... 7 VInput voltage: Control inputs .......................................................... 7 V110 ports ............................................................ 5.5 VOperating free-air temperature range: SN54AS651, SN54AS652 ...................... - 55°C to 125 DCSN74AS651, SN74AS652 .................. ' ........ 0 DC to 70 DCStorage temperature range ................................................. - 65°C to 1 50 DCrecommended operating conditionsSN54AS651SN74AS651SN54AS652 SN74AS652 UNITMIN NOM MAX MIN NOM MAXVee Supply voltage 4.5 5 5.5 4.5 5 5.5 VVIH High-level input voltage 2 2 VVIL Low-level input voltage 0.8 0.8 V101-1 High-level output current -12 -15 mA10L Low-level output current 32 48 mAfclock 0 75 0 90 MHzCBA or CAB high 6 5twPulse durationnseBA or CAB low 76tsu Setup time before CABi or CBAi A or B 7 6 nsth Hold time after CABi or CBAi A orB 0 0 nsTA Operating free-air temperature -55 125 0 70 °eelectrical characteristics over recommended operating free-air temperature range (unless otherwise noted)SN54AS651SN74AS651PARAMETER TEST CONDITIONS SN54AS652 SN74AS652 UNITMIN Typt MAX MIN Typt MAXVIK Vce = 4.5 V, II = -18 mA - 1.2 -1.2 VVCC = 4.5 V to 5.5 V, IOH = -2 mA VCC-2 VCC-2VOHVOLIIIIHIlLVCC = 4.5 V, IOH = -3 mA 2.4 3.2 2.4 3.2VCC = 4.5 V,IOH = -12 mAVCC = 4.5 V, IOH = -15 mA 2VCC = 4.5 V, IOL = 32 mA 0.25 0.50VCC = 4.5 V, IOL = 48 mA 0.35Control inputs VCC = 5.5 V, VI = 7 V 0.1 0.1A or B ports VCC = 5.5 V,VI = 5.5 V0.1 0.1Control inputs 20 20A or B ports;VCC = 5.5 V, VI = 2.7V20.5070 70Control inputs -0.5 -0.5VCC = 5.5 V,VI = 0.4 VA or B ports;-0.75 -0.75IO§ Vce = 5.5 V, Vo = 2.25 V -30 -112 -30 -112 mAIceOutputs high 110 185 110 185'AS651 Outputs low 120 195 120 195Vce = 5.5 VOutputs disabled 130 195 130 195Outputs high 120 195 120 . 195'AS652 Outputs low 130 211 130 211Outputs disabled 130 211 130 211t All typical values are at Vce = 5 V, T A = 25°C.;For I/O ports, the parameters IIH and IlL include the off-state output current.SThe output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOSVVmAjAAmAmAfIIenQ)(,)"SQ)cen...JPRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tothese specifications per the terms of TexasInstruments standard warranty. Productionprocessing does not necessarily include testing of allparameters.TEXAS -Ij}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-135

SN54AS651, SN54AS654, SN74AS651, SN74AS652OCTAL BUS TRANSCEIVERS AND REGISTERS'AS651 switching characteristics (see Note 1)PARAMETERf maxtplHtPHLtpLHtpHLtplHtpHLtpZHtpZLtpHZtplZtpZHtpZLtpHZFROM(lNPUTICBA or CABA or BSBA or SABtGBAGBAGABGABr tplZOOC 'AS652 switching characteristics (see Note 1)CD

SN54ALS666, SN54ALS667, SN74ALS666, SN74ALS6678·BIT O·TYPE TRANSPARENT REAO·Bf\CK LATCHESWITH 3·STATE OUTPUTS02855, JUNE 1984-REVISED DECEMBER 1985• 3-State I/O-Type Read-Back Inputs• Bus-Structured Pinout• Choice of True or Inverting Logic'ALS666 ... True Outputs'ALS667 ... Inverting Outputs• Preset and Clear Inputs• Package Options Include Both Plastic andCeramic Chip Carriers in Addition to Plasticand Ceramics DIPs• Dependable Texas Instruments Quality andReliabilitydescriptionThese 8-bit latches are designed specifically forstoring the contents of the input data bus plusproviding the capability of reading-back thestored data onto the input data bus. In addition,they provide a 3-state buffer type output and areeasily utilized in bus-structured applications.The eight latches of the' ALS666 and' ALS667are transparent Ootype. While the enable (C) ishigh, the Q outputs of the' ALS666 will followthe data (0) inputs. On the ' ALS667, the 0:outputs will provide the inverse of what isapplied to its data (0) inputs. On both devices,the Q or 0: output will be in the high-impedancestate if either output control, OE1 or OE2, is ata high logic level.Read-back is provided thru the read-back controlinput (OERS). When OERS is taken low, the datapresent at the output of the data latches will beallowed to pass back onto the input data bus.When it is taken high, the output of the datalatches will be isolated from the data (0) inputs.The read-back control does not affect theinternal operation of the latches; however,caution should be exercised not to create a busconflictsituation.The SN54ALS666 and SN54ALS667 arecharacterized for operation over the full militarytemperature range of - 55 DC to 125 DC. TheSN74ALS666 and SN75ALS667 arecharacterized for operation from 0 DC to 70 DC.SN54ALS666 ... JT PACKAGESN74ALS666 ... OW OR NT PACKAGE203DNC506070(TOP VIEW)OERBVCCOElOE210 1020 203D 3040 4050 5060 6070 7080 80CLRPREGNOCSN54ALS666 ... FK PACKAGESN74ALS666 ... FN PACKAGE(TOP VIEW)~I~UNo ILU LU U UILU d~ooz>o~4 3 2 1 2827265625242320304089101.122212019NC50607012 131415161718o 10: 0·co U U ILU d..J Z Z 0: coU~ n.NC - No internal connection.C/)CI)o0>Q)cen...JPRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments~~~~~~~~i~a{~~1~1~ ~~::i~~ti~r :I~o~:~:~:t:~s~s notTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1984, Texas Instruments Incorporated2-137

SN54ALS666, SN54ALS667, SN74ALS666, SN74ALS6678·BIT D·TVPE TRANSPARENT READ·BACK LATCHESWITH 3·STATE OUTPUTSiii logicSN54ALS667 ... JT PACKAGESN74ALS667 ... OW OR NT PACKAGENC - No internal connection.symbols t(TOP VIEW)VCCOE2102535405060 6070 7080 80CLRPREGNOC"""1... __ J-''ALS666SN54ALS667 ... FK PACKAGESN74ALS667 ... FN PACKAGE20 530 640NC50 960 1070 11(TOP VIEW)"'I~O\W W U UN U\WIO... OOZ>O ...4 3 2 1 28272612 1314 151617 18° IClJot§Za:: ° U UI~IOa..CIJ'A LS66725 2524 3023 4022 NC21 5020 6019 70(22)10t------t. (21) 20(20) 30(19) 40(18) 50(17) 60(16) 70(15) 80tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12Pin numbers shown are for DW, JT, and NT packages.2·138 . TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54ALS666, SN54ALS667, SN74ALS666, SN74ALS6678·BIT D·TVPE TRANSPARENT READ·BACK LATCHESWITH 3·STATE OUTPUTSlogic diagrams (positive logic)'AlS666'AlS66710 (3)10 (3)20 (4)20 (4)3D (5)40 (6)50 (7)3D (5)40 (6)50 (7)U)Q)CJ'SQ)Cen..J60 (8)60 (8)70 (9)70 (9)80 (10)80 (10)Pin numbers shown are for DW, JT, and NT packages.TEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • OALLAS. TEXAS 752652-139

SN54ALS666, SN54ALS667, SN74ALS666, SN74ALS6678·BIT D·TVPE TRANSPARENT READ·BACK LATCHESWITH 3·STATE OUTPUTStiming diagramDATA BUS INPUT DATA~ »))))) READ BACKtsu/4-.14 th~cOERBII I\ II/4--- tsu .. ------+t !4-tdis~J4.tpd*lIHIIIINPUT DATAIII,IJ4-tpd~Q I ~>CCLR = H, PRE = H, 0E1 = L, 0E2 = L"This setup time ensures the readback circuit will not create a conflict on the input data bus.absolute maximum ratings over operating free-air temperature range (unless otherwise noted)LrC/)CCD

SN54ALS666, SN54ALS667, SN74ALS666, SN74ALS6678-BIT D·TVPE TRANSPARENT READ·BACK LATCHESWITH 3-STATE OUTPUTSelectrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)SN54ALS666SN74ALS666PARAMETER TEST CONDITIONS SN54ALS667 SN74ALS667 UNITMIN TYPt MAX MIN TYPt MAXVIK Vee = 4.5 V, II = -18 mA -1.2 -1.2 VAll outputs Vee = 4.5 V to 5.5 V, IOH = -0.4 mA Vcc- 2 Vcc- 2VOHValQorODQorOVee = 4.5 V, IOH = -1 mA 2.4 3.3 VVee = 4.5 V, 10H = -2.6 mA 2.4 3.2Vee = 4.5 V, 10L = 4 mA 0.25 0.4 0.25 0.4Vee = 4.5 V, 10l = 8 mA 0.35 0.5Vee = 4.5 V, IOl = 12 mA 0.25 0.4 0.25 0.4Vee = 4.5 V, 10l = 24 mA 0.35 0.5Vee = 5.5 V, Va = 2.7 V 20 20~ QorO10Zl Vee = 5.5 V, Va = 0.4 V -20 -20D inputs Vee = 5.5 V, VI = 5.5 V 0.1 0.1IIAll others Vee = 5.5 V, V = 7 V 0.1 0.1IIHD inputsi: 20 20Vee = 5.5 V,V = 2,7 VAll others20 20D inputsi: -0.1 -0.1III Vee = 5.5 V, VI = 0.4 V mAAll others -0.1 -0.1lo§ Vee = 5.5 V, Va = 2.25 V -30 -112 -30 -112 mAleeQ outputs high 25 50 25 50'AlS666 Q outputs low 40 73 40 73Vee = 5.5 V, Q outputs disabled 30 55 30 55OERB highQ outputs high 25 50 25 50'AlS667 Q outputs low 45 79 45 79Q outputs disabled 30 60 30 60t All typical values are at Vee = 5 V, T A = 25 ce.i: For 1/0 ports, the parameters IIH and IlL include the off-state output current.§ The output conditions have been chosen to produce a current that closely approximates one half the true short-circuit output currents, lOS.VI'AmAI'AmA(/)Q)(.)'SQ)cen..JTEXAS -1.!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-141

SN54ALS666, SN54ALS667, SN74ALS666, SN74ALS6678·BIT D·TVPE TRANSPARENT READ·BACK LATCHESWITH 3·STATE OUTPUTS, ALS666 switching characteristics (see Figure 1)PARAMETERFROM(INPUT)TO(OUTPUT)Vee - 5 V.eL -50 pF.Vee ~ 4.5 V to 5.5 V.eL -50 pF.TA - 25°eTA = MIN to MAX'ALS666 SN54ALS666 SN74ALS666MIN TYP MAXtpLH 7 10DQtpHL 11 15tpLH 12 16CQtpHL 16 21tpHLQ 17 22CLRtpHL D 17 24tpLHQ 13 18PREtpHL D 17 22ten11 17OERBDtdis 6 11ten11 17OE1. OE2Qtdis 6 11ii . AlS667 switching characteristics (see Figure 11rencCDc:::(;'CDfJ)PARAMETERtpLHtpHLtpLHtpHLtpLHtpHLtpHLtpLHtentdistentdisFROM(INPUT)TO(OUTPUT)D 0:C 0:CLRPREOERBQDQDDOE1. OE2 0:Vee - 5 v.eL - 50 pF.MIN MAX MIN MAX3 18 3 144 22 4 186 25 6 218 32 8 279 32 9 2911 36 11 327 28 7 229 35 9 284 25 4 211 18 1 144 25 4 211 18 1 14Vee - 4.5 V to 5.5 V.CL -50 pF.TA - 25°eTA - MIN to MAX'ALS667 SN54ALS667 SN74ALS667MIN TYP MAX MINMAX MIN MAX13 17 624 6 209 13 418 4 1518 23 935 9 2814 19 727 7 2214 19 728 7 2417 23 830 8 2617 23 830 8 2518 25 935 9 2811 17 425 4 216 11 120 1 1411 17 425 4 216 11 120 1 14UNITnsnsnsnsnsnsUNITnsnsnsnsnsnsten = tpZH or tpZLtdis = tpHZ or tpLZ2-142TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54ALS666, SN54ALS667, SN74ALS666, SN74ALS6678·BIT D·TVPE TRANSPARENT READ·BACK LATCHESWITH 3·STATE OUTPUTSPARAMETER MEASUREMENT INFORMATION7V~S17V~S1500 nFROM OUTPUTTESTUNOER TEST -1--+--+- POINTCL500 n(See Note A)1 kf!FROM OUTPUTTESTUNDER TEST -.-......- ....- POINTCL1 kf!(See Note A)LOAD CIRCUIT FORQ OR a: OUTPUTSLOAD CIRCUIT FOR D OUTPUTSTIMINGINPUTDATAINPUT___J./ 3.5 V/,1.3 V....J : - - - - - - - - 0.3 V~ tsu -014- th ~. ~1-,;~/-3.5V1 3V . ~0.3 VVOLTAGE WAVEFORMSSETUP AND HOLD TIMESINPUT ~-1.;V- - - 3.5VJ: I.~V .~ 0.3VtpLH~I4---*-tpHL! : -t-- VOHIN'PHASE~IOUTPUT i 1.3 V : 1.3 VIVOLtpHL~ ~tPLHIIOUT -OF·PHASE ~. I v.::1 ., \I I VOHOUTPUT . ~..2.~v(See Note D) - - - VOLVOLTAGE WAVEFORMSPROPAGATION DELAY TIMES~~~~~LEVEL ~ 3.5Vl4---- tw ~0.3 VLOW·LEVELPULSEOUTPUT~~ tw.~~ 3.5V~ __ _VOLTAGE WAVEFORMSPULSE WIDTHSCONTROL 1.3 V 1.3 V0.3 V3.5 V(low·level I -i-------- 0.3Venabling) tpZL --*-* ..., If- tpLZI I I II : I : '" 3.5 VWAVEFORM1~1.3V i :~3VS1 CLOSED I ~.:------:.:=-~ VOL(See Note B) tPZH~ I TWAVEFORM 21 ~ ~~_110_ V .I -----f- OHS10PEN(See Note B)1.3 V0.3 V ",0 VVOLTAGE WAVEFORMSENABLE AND DISABLE TIMES, THREE·STATE OUTPUTSEllU)Cl)CJoSCl)cen..oJNOTES: A. CL includes probe and jig capacitance.B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.C. All input pulses have the following characteristics: PRR :s 1 MHz, tr = tf = 2 ns, duty cycle = 50%.D. When measuring propagation delay times of 3·state outputs, switch S 1 is open.FIGURE 1. TEXAS"INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-143

II2-144

SN54AS821, SN54AS822, SN74AS821, SN74AS82210·BIT BUS INTERFACE FLlp·FLOPS WITH 3·STATE OUTPUTSD2825. DECEMBER 1983-REVISED JANUARY 1986• Functionally Equivalent to AMD's AM29821and AM29822• Provides Extra Data Width Necessary forWider Address/Data Paths or Buses withParity• Outputs Have Undershoot ProtectionCircuitry• Power·Up High·lmpedance State• Package Options Include Both Plastic andCeramic Carriers in Addition to Plastic andCeramic DIPs• Buffered Control Inputs to Reduce DCLoading Effects• Dependable Texas Instruments Quality andReliabilitySN54AS821 ... JT PACKAGESN74AS821 ... OW OR NT PACKAGE(TOP VIEW)oc 24 VeclD 23 102D 22 203D 21 304D 20 405D 19 506D 18 607D 17 708D 9 16 809D 10 15 90lOp 11 14 100GND 12 13 ClKSN54AS821 ... FKPACKAGESN74AS821 ... FN PACKAGE(TOP VIEW)4 3 ·2 1 28 27 26descriptionThese 10-bit flip-flops feature three-stateoutputs designed specifically for driving highlycapacitiveor relatively low-impedance loads.They are particularly suitable for implementingwider buffer registers, I/O ports, bidirectional busdrivers with parity, and working registers.The ten flip-flops are edge-triggered O-type flipflops.On the positive transition of the clock theQ outputs on the' AS821 will be true, and on the'AS822 will be complementary to the data input.A buffered output-control input can be used toplace the ten outputs in either a normal logicstate (high or low levels) or a high-impedancestate. In the high-impedance state the outputsneither load nor drive the bus lines significantly.The high-impedance state and increased driveprovide the capability to drive the bus lines in abus-organized system without need for interfaceor pull-up components. The output control (OC)does not affect the internal operation of the flipflops.Old data can be retained or new data canbe entered while the outputs are in the highimpedancestate.The SN54AS' family is characterized foroperation over the full military temperature rangeof - 55 DC to 125 DC. The SN74AS' family ischaracterized for operation from 0 DC to 70 DC.121314151617 18SN54AS822 ... JT PACKAGESN74AS822 ... OW OR NT PACKAGEOC(TOP VIEW)3D 4456D9D 10100 11GND 12Vcc102021 3020 4019 5018 6017 7016 8015 9014 10013 ClKSN54AS822 ... FK PACKAGESN74AS822 , , . FN PACKAGE(TOP VIEW)1~1~lg ~ ~ ~ ~4 3 2 1 2827 26U)Q)to)'S;Q)cen..J12 13 14 15 16 17 18NC - ND internal connectionPRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments~~~~~:~~i~at~~I~~e ~!~:i~~ti~r fl~o::~:~:t:r~~s notTEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265Copyright © 1983. Texas Instruments Incorporated2-145

SN54AS821, SN74AS82110-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS'AS821 FUNCTION TABLE (EACH FLiP-FLOPIINPUTSOUTPUTOC CLK D QL t H HL t L LL L X QOH X X Z'AS821 logic diagram (positive logic)oc -'(.....;1I ____ -QI'AS821 logic symbol tEIrCJ)CCD

SN54AS822, SN74AS82210·BIT BUS INTERFACE FLlp·FLOPS WITH 3·STATE OUTPUTS'AS822 FUNCTION TABLE (EACH FLIP-FLOP)INPUTSOUTPUToe elK D 0l i H Hl i L Ll l X 00H X X Z• AS822 logic diagram (positive logic)oc ....;(...;1 ,-----01• AS822 logic symbol t20 -(3-'----t--OI10(23)1020(22)2030(21)3040(20)40(19)5050(18)6060(17)7070(16)8080(15)9'090(11)100(14)100tThis symbol is in accordance with ANSI/IEEE Std 91-1984 andlEe Publication 617-12.3D ..;.(4..:-'___-+--a40 (5,50 (6)60 (7)ii5 (8)•(J)Q)(.)'S;Q)cen...J_ (10)90 ------1~~100 _(1_1_) ______ -QPin numbers shown are for DW, JT, and NT packages.TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-147

SN54AS821, SN54AS822, SN74AS821, SN74AS82210-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTSabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VInput voltage .............................................................. 7 VVoltage applied to a disabled 3-state output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VOperating free-air temperature range: SN54AS821, SN54AS822 . . . . . . . . . . . .. - 55 °e to 125 °eSN74AS821, SN74AS822 ................ ooe to 70°CStorage temperature range ........................................ - 65°C to 150 °erecommended operating conditionsrrncCD$.nCDt/)SN54AS821SN74AS821SN54AS822 SN74AS822 UNITMIN NOM MAX MIN NOM MAXVee Supply voltage 4.5 5 5.5 4.5 5 5.5 VVIH High-level input voltage 2 2 VVIL Low-level input voltage 0.8 0.8 V10H High-level outp,ut current - 24 - 24 mA10L Low-level output currrent 32 48 mAtw Pulse duration, eLK high or low 9 8 nstsu Setup time, data before eLKi 7 6 nsth Hold time, data after eLKi 0 0 nsTA Operating free-air temperature - 55 125 - 0 70 °eelectrical characteristics over recommended operating free-air temperature range (unless .otherwisenoted)SN54AS821SN74AS821PARAMETER TEST CONDITIONS SN54AS822 SN74AS822 UNITMIN TYpt MAX MIN TYpt MAXVIK Vee = 4.5 V, II = -18 mA -1.2 -1.2 VVee = 4.5 V to 5.5 V, 10H = -2 mA vCC- 2 VCC-2VOH Vee = 4.5 V, 10H = -15 mA 2.4 3.2 2.4 3.2 VVOLVee = 4.5 V, 10H = -24 mA 2 2Vee = 4.5 V, 10L = 32 mA 0.25 0.5Vee = 4.5 V,10L = 48 mA 0.35 0.510ZH Vee = 5.5 V, Vo = 2.7 V 50 50 {lA10ZL Vee = 5.5 V, Vo = 0.4 V - 50 -50 {lAII Vee = 5.5 V, VI = 7 V 0.1 0.1 mAIIH Vee = 5.5 V, VI = 2.7 V 20 20 {lAIlL Vee = 5.5 V, VI = 0.4 V -0.5 -0.5 mA10+ Vee = 5.5 V, Vo = 2.25 V -30 -112 -30 -112 mAOutputs high 55 88 55 88lee'AS821 Outputs low 68 109 68 109Vee = 5.5 VOutputs disabled 70 113 70 113Outputs high 55 88 55 88'AS822 Outputs low 68 109 68 109Outputs disabled 70 113 70 113VmAtAli typical values are at Vee = 5 V, TA = 25°e.+The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.2-148TEXAS -I!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54AS821, SN54AS822, SN74AS821, SN74AS82210·BIT BUS INTERFACE FLlp·FLOPS WITH 3·STATE OUTPUTSswitching characteristics (see Note 1)Vcc = 4.5 V to 5.5 V.Cl = 50 pF.Rl = 500 fl.PARAMETERFROM TO R2 = 500 fl.(INPUT) (OUTPUT) TA = MIN to MAXSN54AS821SN74AS821SN54AS822SN74AS822MIN MAX MIN MAXtplHelKAny Q3.5 9 3.5 7.5tpHl 3.5 11.5 3.510.5tpZH4 12 4 11oeAny QtpZL 4 13 412tpHZ2 10 2 8oeAny QtpZL 2 10 2 8UNITnsnsnsNOTE 1: Load circuit and voltage waveforms are shown in Section 1.EllCJ)Q)(.)'SQ)oCJ)...JTEXAS -I.!}INSTRUMENTSPOST OFFICE BOX 225012 • OALLAS. TEXAS 752652-149

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SN54AS823, SN54AS824SN74AS823, SN74AS8249·BIT BUS INTERFACE FlIp·FLOPS WITH 3·STATE OUTPUTS02825, JUNE 1984-REVISED JANUARY 1986• Functionally Equivalent to AMD's AM29823and AM29824• Provides Extra Data Width Necessary forWider Address/Data Paths or Buses withParity• Outputs Have Undershoot ProtectionCircuitryoPower-Up High-Impedance State• Buffered Control Inputs to Reduce DCLoading Effects• Package Options Include both Plastic andCeramic Carriers in Addition to Plastic andCeramic DIPs• Dependable Texas Instruments Quality andReliabilitydescriptionThese 9-bit flip-flops feature three-state outputsdesigned specifically for driving highly capacitiveor relatively low-impedance loads. They areparticularly suitable for implementing widerbuffer registers, I/O ports, bidirectional busdrivers, parity bus interfacing and workingregisters.With the clock enable (CLKEN) low, the nine Dtype edge-triggered flip-flops enter data on thelow-to-high transitions of the clock. TakingCLKEN high will disable the clock buffer, thuslatching the outputs. The 'AS823 hasnoninverting D inputs and the 'AS824' hasinverting D inputs. Taking the CLR input lowcauses the nine Q outputs to go lowindependently of the clock.A buffered output-control input (OC)can be usedto place the nine outputs in either normal logicstate (high or low level) or a high-impedancestate. In the high-impedance state the outputsneither load nor drive the bus lines significantly.The high-impedance state and increased driveprovide the capability to drive the bus lines in abus-organized system without need for interfaceor pull-up components. The output control doesnot affect the internal operation of the flip-flops.Old data can be retained or new data can beentered while the outputs are in the highimpedancestate.SN54AS823 ... JT PACKAGESN74AS823 ... OW OR NT PACKAGE(TOP VIEW)6CVCC1D 102040 4050607D 7080 8090 10 15 90ClR 11 14 ClKENGND 12 13 ClKSN54AS823 ... FK PACKAGESN74AS823 ... FN PACKAGE(TOP VIEW)u~ ~Ig ~ ~~ ~4 3 2 1 2827 2612131415 161718SN54AS824 ... JT PACKAGESN74AS824 ... OW OR NT PACKAGE6C(TOP VIEW)vcc10203045 4055 5065 607085 8095 10 15 90ClR 11 14 ClKENGND 12 13 ClKSN54AS824 ... FK PACKAGESN74AS824 ... FN PACKAGE(TOP VIEW)u1~1~lg ~ ~~ ~4 3 2 1 28 27 2625 3024 4023 5022 NC21 6010 20 7019 80121314151617 18EllenQ)(.)'SQ)cen..JPRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instrumentsstandard warranty. Production processing does notnecessarily include testing of all para~eters.TEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DAllAS, TEXAS 75265Copyright © 1984, Texas Instruments Incorporated2-151

SN54AS823, SN54AS824, SN74AS823, SN74AS8249·BIT BUS INTERFACE FLlp·FLOPS WITH 3·STATE OUTPUTSThe SN54AS' family is characterized for operation over the full military temperature range of - 55 DC to125 D C. The SN74AS' family is characterized for operation from ODC to 70 D C.• AS823 FUNCTION TABLEI AS823 logic diagram (positive logic)OClClRlINPUTSClKEN ClK 0X X XOUTPUTQlOc -.:.(.:.!11 __________

SN54AS824, SN74AS8249·BIT BUS INTERFACE FLlp·FLOPS WITH 3·STATE OUTPUTS'AS824 FUNCTION TABLEINPUTSOC CLR CLKEN CLK DL L X X XL H L t HL H L t LL H H X XH X X X XOUTPUT0LLH00Z• AS824 logic diagram (positive logic)OC~---------------------qCLR ....:....:...'-'-----

SN54AS823, SN54AS824, SN74AS823, SN74AS8249·BI1 BUS INTERFACE FLlp·FLOPS WITH 3·STATE OUTPUTSIrCJlCCD

SN54AS823, SN54AS824, SN74AS823, SN74AS8249·BIT BUS INTERFACE FLlp·FLOPS WITH 3·STATE OUTPUTSswitching characteristics (see Note 1)Vcc - 4.5 V to 5.5 V.- Cl - 50 pF.PARAMETERR1 -500 fl.FROM TO R2 - 500 fl.(INPUT) (OUTPUT) TA - MIN to MAXSN54AS823SN54AS824SN74AS823SN74AS824MIN MAX MIN MAXtpLH3.5 9 3.5 7.5ClKAny QtpHl 3.5 12 3.5 11tpHl CLR Any Q 3.5 14 3.5 13 nstpZHtpZLOCAny Q4 12 4 114 13 4 12tpHZ2 10 2 8OCArry QtpLZ 2 10 2 8NOTE 1: load circuit and voltage waveforms are shown in Section 1.o flip-flop signal conventionsIt is normal TI practice to name the outputs and other inputs of a D-type flip-flop and to draw its logicsymbol based on the assumption of true data (Df inputs. Then outputs that produce data in phase withthe data inputs are called Q and those producing complementary data are called Q. An input that causesa Q output to go high or a Q output to go low is called Preset; an input that causes a Q output to go highor a Q output to go low is called Clear. Bars are used over these pin names (PRE and CLR) if they areactive-low.The devices on this data sheet are second-source designs and the pin-name convention used by the originalmanufacturer has been retained. That makes it necessary to designate the inputs and outputs of the invertingcircuit D and Q. In some applications it may be advantageous to redesignate the inputs and outputsas D and Q. In that case, outputs should be renamed as shown below. Also shown are correspondingchanges in the graphical symbol. Arbitrary pin numbers are shown in parentheses.Notice that Q and Q exchange names, which causes Preset and Clear to do likewise. Also notice that thepolarity indicators ( ~ ) on PRE and CLR remain since these inputs are still active-low, but that the presenceor absence of the polarity changes at D, Q, and Q. Of course pin 5 (Q) is still in phase with the data inputD, but now both are considered active high.UNITnsnsnsIIenQ)UoSQ)cen...JClR R PRE SQClK C1 ClK C10 1D(6) D 10aPRE S ClR R(5)aQTEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-155

Irenc(1)

• Functionally Equivalent to AMD's AM29825and AM29826• Improved 10H Specifications• Multiple Output Enables Allow MultiuserControl of the Interface• Outputs Have Undershoot ProtectionCircuitryoPower-Up High-Impedance State• Package Options Include Both Plastic andCeramic Chip Carriers in Addition to Plasticand Ceramic DIPs• Buffered Control Inputs to Reduce DCloading EffectoDependable Texas Instruments Quality andReliabilitydescriptionThese 8-bit flip-flops feature three-state outputsdesigned specifically for driving highly capacitiveor relatively low-impedance loads. They areparticularly suitable for implementing multiuserregisters. I/O ports. bidirectional bus drivers. andworking registers.'With the clock enable (CLKEN) low. the eight Dtype edge-triggered flip-flops enter data on thelow-to-high transitions of the clock. TakingCLKEN high will disable the clock buffer. thuslatching the outputs. The • AS825 has noninvertingD inputs and the' AS826 has invertingD inputs. Taking the CLR input low causesthe eight Q outputs to go low independently ofthe clock.Multiuser buffered output-control inputs (OC 1.OC2. and OC3) can be used to place the eightoutputs in either a normal logic state (high or lowlevel) or a high-impedance state. In the highimpedancestate the outputs neither load nordrive the bus lines significantly. The highimpedancestate and increased drive provide thecapability to drive the bus lines in a busorganizedsystem without need for interface orpull-up components. The output controls do notaffect the internal operation of the flip-flops. Olddata can be retained or new data can be enteredwhile the outputs are in the high-impedancestate.PRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments~~~~~~~~i~a{~:I~~~ ~!~~~~ti:f fl~o::~:~:t:rOs~s notSN54AS825, SN54AS826SN74AS825, SN74AS8268·BIT BUS INTERFACE FLlp·FLOPS WITH 3·STATE OUTPUTSTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DAllAS, TEXAS 75265D2825. JUNE 1984-REVISED JANUARY 1986SN54AS825 ... JT PACKAGESN74AS825 ... OW OR NT PACKAGE(TOP VIEW)Oc1VCCOc2OC310203D 304050607D 708D 10 15 80ClR 11 14 ClKENGND 12 13 ClKSN54AS825 ... FK PACKAGESN74AS825 ... FN PACKAGE(TOP VIEW)4 3 2 1 28 27262D 5 25( 203D 6 24( 304D 23[ 40NC22[ NC5D 9 21( 506D 10 20[ 607D 11 19( 7012 131415161718SN54AS826 ... JT PACKAGESN74AS826 ... OW OR NT PACKAGE(TOP VIEW)7585 10ClR 11GND 12151413VCCOC31020304050607080ClKENClKSN54AS826 ... FK PACKAGESN74AS826 ... FN PACKAGE203545NC5565 1075 11(TOP VIEW)4 3 2 1 28272612 131415161718CIa:cU",,!ZOQJ....JZZ....JUJcoUt::) U:5U25[ 2024( 3023 4022 NC21 5020 6019 70NC-No internal connectionCopyright © 1984. Texas Instruments Incorporated2-157IIenQ)(,)os;cQ)en...J

SN54AS825. SN54AS826. SN74AS825. SN74AS8268·BIT BUS INTERFACE FLlp·FLOPS WITH 3·STATE OUTPUTSThe SN54AS' family is characterized for operation over the full military temperature range of - 55 °e to125°e. The SN74AS' family is characterized for operation from ooe to 70 o e.'AS825 FUNCTION TABLEINPUTSOC* CLR CLKEN CLK Dl L X X XL H L t HL H L t LL H H X XH X X X XOUTPUT0LHL00Z, AS825 logic diagram (positive logic)(1)OCl(2)OC2(23)OC3ClRCLKENIr-~CCD

SN54AS826, SN74AS8268·BIT BUS INTERFACE FLlp·FLOPS WITH 3·STATE OUTPUTS'AS826 FUNCTION TABLEINPUTSOC· ClR ClKEN ClK Dl l X X Xl H l t Hl H l t ll H H X XH X X X XOUTPUT0llH00Z'AS826 logic diagram (positive logic)OC1~~---------------.OC2~~------------------~OC3~~--------------~ClR ....:..:...~----~ClKENOC· = H if any of aCl, aC2, or aC3 are high.ac' = l if all of aCl, aC2, and aC3 are low.'AS826 logic symbol t(22)10OClOC2OC3ClRClKENelK1520354555657580t This symbol is in accordance with ANSI/IEEE Std 91-1984 andIEC Publication 617-12.E.!L 20(20) 30•(19) 40(18) 50(17) 60(16)70U)Q)CJ'SQ)0en..J(15) 80Pin numbers shown are for OW, JT, and NT packages.TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-159

SN54AS825, SN54AS826, SN74AS825, SN74AS8268·BIT BUS INTERFACE FLlp·FLOPS WITH 3·STATE OUTPUTSrencCDabsolute maximum ratings over operating free·air temperature range (unless otherwise noted)Supply voltage, Vee ......................................................... 7 VInput voltage .............................................................. 7 VVoltage applied to a disabled 3-state output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VOperating free-air temperature range:SN54AS825, SN54AS826 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°CSN74AS825, SN74AS826 ..................................... OOeto 70°CStorage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65 to 150 °erecommended operating conditionsSN54AS825SN74AS825SN54AS826 SN74AS826 UNITMIN NOM MAX MIN NOM MAXVee Supply voltage 4.5 5 5.5 4.5 5 5.5 VVIH High-level input voltage 2 2 VVil low-level input voltage 0.8 0.8 V10H High-level output current -24 -24 mA10l low-level output current 32 48 mAtw Pulse durationClR low 5 4elK high or low 9 8nselR inactive 8 8tsu Setup time before elKi Data 7 6 nsClKEN high or low 7 6th Hold time, elKEN or data after elKi 0 0 nsTA Operating free-air temperature -55 125 0 70 °e~. electrical characteristics over recommended operating free-air temperature range (unless otherwiseCD noted)tJ)PARAMETERTEST CONDITIONSSN54AS825SN74AS825SN54A5826SN74AS826MIN Typt MAX MIN Typt MAXVIK Vee = 4.5 V, II = -18 mA -1.2 -1.2 VVee = 4.5 V to 5.5 V, 10H = -2 mA vCC- 2 VCC-2VOH Vee = 4.5 V, 10H = -15 mA 2.4 3.2 2.4 3.2 VVOLVee = 4.5 V, 10H = -24 mA 2 2Vee = 4.5 V, IOL = 32 mA 0.3 0.5VCC = 4.5 V, 10l = 48 mA 0.35 0.510ZH Vee = 5.5 V, Vo = 2.7 V 50 50 p.A10Zl Vee = 5.5 V, Vo = 0.4 V -50 -50 p.AII Vee = 5.5 V, VI = 7 V 0.1 0.1 mAIIH Vee = 5.5 V, VI = 2.7 V 20 20 p.AIII Vee = 5.5 V, VI' = 0.4 V -0.5 -0.5 mAlot Vce = 5.5 V, Vo = 2.25 V -30 -112 -30 -112 mAleeOutputs high 45 73 45 73'AS825 Vee = 5.5 V Outputs low 56 90 56 90 mAOutputs disabled 59 95 59 95Outputs high 45 73 45 73'AS826 Vee = 5.5 V Outputs low 56 90 56 90 mAOutputs disabled 59 95 59 95t All typical values are at Vee = 5 V, T A = 25°e.t The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.UNITV2-160 TEXAS ~INSTRUMENTSPOST OFFiCe BOX 225012 • DALLAS. TeXAS 75265

SN54AS825, SN54AS826, SN74AS825, SN74AS8268-BIT BUS I~JTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTSswitching characteristics (see Note 1)PARAMETERVcc = 4.5 V to 5.5 V.CL = 50 pF.R1 = 500 fl.FROM TO R2 = 500 fl.(INPUT) (OUTPUT) TA = MIN to MAXSN54AS825SN54AS826SN74AS825SN74AS826MIN MAX MIN MAXtpLH 3.5 9 3.5 7.5ClK Any Q nstpHl 3.5 11.5 3.5 11tpHl ClR Any Q 3.5 14 3.5 13 nstpZH4 12 4 11OCAny QtpZl 4 13 4 12nstpHZ2 10 2 8OCAny QtplZ 2 10 2 8nsNOTE 1: load circuit and voltage waveforms are shown in Section 1.UNITD flip-flop signal conventionsIt is normal TI practice to name the outputs and other inputs of a Ootype flip-flop and to draw its logicsymbol based on the assumption of true data (0) inputs. Then outputs that produce data in phase withthe data inputs are called Q and those producing complementary data are called 6. An input that causesa Q output to go high or a Q output to go low is called Preset; an input that causes a Q output to go highor a Q output to go low is called Clear. Bars are used over these pin names (PRE and CLR) if they areactive-low.The devices on this data sheet are second-source designs and the pin-name convention used by the originalmanufacturer has been retained. That makes it necessary to designate the inputs and outputs of the invertingcircuit IS and Q. In some applications it may be advantageous to redesignate the inputs and outputs aso and O. In that case, outputs should be renamed as shown below. Also shown are corresponding changesin the graphical symbol. Arbitrary pin numbers are shown in parentheses.Notice that Q and Q exchange names, which cal!ses Preset and Clear to do likewise. Also no~ice that thepolarity indicators ( t:::.. ) on PRE and CLR remain since these inputs are still active-low, but that the presenceor absence of the polarity indicator changes at D, Q. and Q. Of course pin 5 (Q) is still in phase with the datainput D, but now both are considered active high.(f)Q)(.)os:Q)CU)-ICLR PRE SaCLK C1 CLK C10 0 10QPRE CLR R(5)QQTEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-161

II2-162

SN54ALS841, SN54AS841, SN54ALS842, SN54AS842SN74ALS841, SN74AS841, SN74ALS842, SN74AS84210·BIT BUS INTERFACE O·TYPE LATCHES WITH 3·STATE OUTPUTS02910. DECEMBER 1983-REVISED OCTOBER 1985• 3·State Buffer· Type Outputs Drive Bus·LinesDirectly• Bus·Structured Pinout• Provide Extra Bus Driving LatchesNecessary for Wider Address/Data Paths orBuses with Parity• Buffered Control Inputs to Reduce DCLoading• Power·Up High·lmpedance State• Package Options Include Both Plastic andCeramic Chip Carriers in Addition to Plasticand Ceramic DIPs• Dependable Texas Instruments Quality andReliabilitydescriptionThese 1 O-bit latches feature three-state outputsdesigned specifically for driving highly capacitiveor relatively low-impedance loads. They areparticularly suitable for implementing bufferregisters, I/O ports, bidirectional bus drivers, andworking registers.The ten latches are transparent D-type. The, ALS841 and' AS841 have noninverting data (D)inputs. The' ALS842 and' AS842 have inverting5 inputs.A buffered output control (OC) input can be usedto place the ten outputs in either a normal logicstate (high or low levels) or a high-impedancestate. In the high-impedance state, the outputsneither load nor drive the bus lines significantly.The high-impedance state and increased driveprovide the capability to drive the bus lines in abus-organized system without need for interfaceor pull-up components.The output control does not affect the internaloperation of the latches. Old data can be retainedor new data can be entered while the outputsare off.The -1 versions of the SN74ALS841 andSN74ALS842 parts are identical to the standardversions except that the recommendedmaximum 10L is increased to 48 milliamperes.There are no -1 versions of the SN 54ALS841and SN54ALS842.SN54ALS841. SN54AS841 ... JT PACKAGESN74ALS841. SN74AS841 ••. OW OR NT PACKAGEoc(TOP VIEW)VCC1022 2021 3040 20 4050 19 5060 7 18 6070 17 7080 16 8090 10 15 90100 11 14 100GNO 12 13 CSN54ALS841. SN54AS841 ... FK PACKAGESN74ALS841. SN74AS841 ... FN PACKAGENC6070 10(TOP VIEW)u~ ~Ig ~ ~~ ~4 3 2 1 28 27 2612131415161718ooouuaaClOZZ 001-(,? -304050NC607080SN54ALS842. SN54AS842 ..• JT PACKAGESN74ALS842. SN74AS842 ... OW OR NT PACKAGE(TOP VIEW)VCC10203045 4055 50607D 7085 8095 10 15 9010D 11 14 100GNO 12 13 CSN54ALS842. SN54AS842 ... FK PACKAGESN74ALS842. SN74AS842 ... FN PACKAGE(TOP VIEW)u1~1~lg ~ ~~ ~4 3 2 1 2827 26304055 50NCNC6075 708012131415 1617 1810100 U u a aClOZZ 001-t:) -NC-No internal connectionIItJ)Q)(.)'SQ)cen..JPRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments~~~~~~~~i~a{~:1~1~ ~!~~~~ti~f :llo~:~:~it:~s~s notTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1983. Texas Instruments Incorporated2-163

SN54ALS841, SN54AS841, SN54ALS842, SN54AS842SN74ALS841, SN74AS841, SN74ALS842, SN74AS84210·BIT BUS INTERFACE O·TVPE LATCHES WITH 3·STATE OUTPUTSThe SN54ALS841, SN54AS841, SN54ALS842, and SN54AS842 are characterized for operation overthe full military temperature range of - 55 ae to 125 ae. The SN74ALS841, SN74AS841, SN74ALS842,and SN74AS842 are characterized for operation from 0 ae to 70 ae.FUNCTION TABLES• ALS841 •• AS841• ALS842 •• AS842INPUTS OUTPUT INPUTS OUTPUTOC C 0 0 OC C 0 0L H H H L H H LL H L L L H L HL L X 00 L L X 00H X X Z H X X ZIr-CJ)CCD

'AL5842, 'A5842 logic symboltocC10203D40506070SO90100SN54ALS841, SN54AS841, SN54ALS842, SN54AS842SN74ALS841, SN74AS841, SN74ALS842, SN74AS84210-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS(23) la(22)2a(21) 3a(20)4a(19)5a. (lS) 6a(17)7a(16)sa(15)9a(14)loat This symbol is in accordance with ANSI/lEEE Std 91-1984 andlEe Publication 617-12.Pin numbers shown are for DW, JT, and NT packages.absolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VInput voltage .............................................................. 7 VVoltage applied to a disabled 3-state output ................................ ; . . . .. 5.5 VOperating free-air temperature range:SN54ALS841, SN54AS841, SN54ALS842, SN54AS842 ........... -55°Cto 125°eSN74ALS841, SN74AS841, SN74ALS842, SN74AS842 .............. , ooe to 70 0 eStorage temperature range ......................................... - 65°C to 150 0 e. TEXAS-II}INSTRUMENlSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-165

SN54ALS841, SN74ALS84110·BIT BUS INTERFACE O·TVPE LATCHES WITH 3·STATE OUTPUTSrecommended operating conditionsSN54ALS841SN74ALS841MIN NOM MAX MIN NOM MAXVee Supply voltage 4.5 5 5.5 4.5 5 5.5 VVIH High-level input voltage 2 2 VVIL Low-level input voltage 0.8 0.8 VIOH High-level output current -1 -2.6 rnA10LLow-level output currentUNIT12 2448 t rnAtw Pulse duration, enable e high 25 20 nstsu Setup time, data before enable e~ 16 10 nsth Hold time, data after enable e~ 7· 5 nsTA Operating free-air temperature -55 125 0 70 °etThe extended limit applies only if Vee is maintained between 4.75 V and 5.25 V. The 48 rnA limit applies for SN74ALS841-1 only.IIr(J)C(1)

SN54ALS841, SN74ALS84110·BIT BUS INTERFACE O·TVPE LATCHES WITH 3·STATE OUTPUTSI ALS841 switching characteristics (see Note 1)Vcc - 5 V. Vcc - 4.5 V to 5.5 V.CL - 50 pF. CL - 50 pF.R1 - 500 fl. R1 - 500 fl.FROMTOPARAMETER R2 - 500 fl. R2 - 500 fl. UNIT(INPUT) (OUTPUT)TA - 25°C TA - MIN to MAXSN54/74ALS841 SN54ALS841 SN74ALS841MIN TYP MAX MIN TYP MAX MIN TYP MAXtpLH 8.5 11 2 15 2 130 QtpHL 8.5 11 2 15 2 13nstpLHI14 18 7 25 7 21C QtpHL 17 23 8 30 8 26nstpZH7.5 10 2 14 2 12OCQtpZL 7.5 10 2 14 2 12nstpHZ6 8 2 12 2 10OCQtPLZ 7 9 2 14 2 12nsNOTE 1: Load circuit and voltage waveforms are shown in Section 1.EllTEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-167

SN54ALS842, SN74ALS84210·BIT BUS INTERFACE O·TVPE LATCHES WITH 3·STATE OUTPUTSrecommended operating conditionsSN54ALS842SN74ALS842MIN NOM MAX MIN NOM MAXVee Supply voltage 4.5 5 5.5 4.5 5 5.5 VVIH High-level input voltage 2 2 VVIL Low-level input voltage 0.8 0.8 VIOH High-level output current -1 -2.6 mAIOLLow-level output currentUNIT12 2448 t mAtw Pulse duration, enable e high 25 20 nstsu Setup time, data before enable e! 16 10 nsth Hold time, data after enable e! 7 5 nsTA Operating free-air temperature -55 125 0 70 °etThe extended limit applies only if Vee is maintained between 4.75 V and 5.25 V. The 48 mA limit applies for SN74ALS841-1 only.electrical characteristics over recommended operating free-air temperature range(unless otherwise noted)rencCD

SN54ALS842, SN74ALS84210·BIT BUS INTERFACE D·TVPE LATCHES WITH 3·STATE OUTPUTS'ALS842 switching characteristics (see Note 1)Vcc - 5 V. Vcc - 4.5 V to 5.5 V.cL. - 50 pF. CL - 50 pF.R1 - 500 n. R1 - 500 n.PARAMETERFROMTO(INPUT) (OUTPUT)R2 a 500 n.R2 a 500 n. UNITTA - 25°C TA - MIN to MAX'ALS842 SN54ALS842 SN74ALS842MIN TYP MAX MIN MAX MIN MAXtpLH11 15 4 22 4 18DQtpHL 8 11 3 17 3 13tpLH 17 23 8 31 8 27C QtpHL 13 18 6 24 6 20nstpZH8 10 2 14 2 12OCQtpZL 8 11 2 14 2 12nstpHZ6 8 1 12 1 10OCQtpLZ 7 9 2 14 212nsNOTE 1: Load circuit and voltage waveforms are shown in Section 1.ns(/)Q)CJ'S;Q)cen..JTEXAS -Ij}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-169

SN54AS841, SN54AS842SN74AS841, SN74AS84210-BIT BUS INTERFACE OoTYPE LATCHES WITH 3-STATE OUTPUTS.recommended operating conditionsSN54AS841SN54AS842MIN NOM MAXVee Supply voltage 4.5 5 5.5VIH High-level input voltage 2Vil low-level input voltage 0.810H High-level output current -2410l low-level output current 32tw Pulse duration, enable e high 5tsu Setup time, data before enable e.(. 3.5th Hold time, data after enable e.(. 3.5TA Operating free-air temperature -55 125SN74AS841SN74AS842MIN NOM MAX4.5 5 5.5242.50.8-24482.50 70UNITVVVrnArnAnsnsnsDeIIelectrical characteristics over recommended operating free-air temperature. range(unless otherwise noted)SN54AS841SN74AS841PARAMETER TEST CONDITIONS SN54AS842 SN74AS842MIN Typt MAX MIN Typt MAXVIK Vee = 4.5 V, II = -18 rnA -1.2 -1.2Vee = 4.5 V to 5.5 V, IOH = -2 rnA vcc- 2 vcc- 2VOH Vee = 4.5 V, IOH = -15 rnA 2.4 3.2 2.4 3.2ValVee = 4.5 V, 10H = -24 rnA 2 2Vee = 4.5 V, IOl = 32 rnA 0.25 0.5Vee = 4.5 V, 10l = 48 rnA 0.35 0.510ZH Vee = 5.5 V, Vo = 2.7V 50 5010Zl Vee = 5.5 V, Vo = 0.4 V -50 -50II Vee = 5.5 V, VI = 7 V 0.1 0.1IIH Vee = 5.5 V, VI = 2.7 V 20 20III Vee = 5.5 V, VI = 0.4 V -0.5 -0.510+ Vee = 5.5 V, Va = 2.25 V -30 -112 -30 -112leeOutputs high 36 60 36 60'AS841 Outputs low 58 94 58 94Vee = 5.5 VOutputs disabled 56 92 56 92Outputs high 38 62 38 62'AS842 Outputs low 60 97 60 97Outputs disabled 58 95 58 95UNITVVVp.Ap.ArnAp.ArnArnArnAt All typical values are at Vee = 5 V, T A = 25°e.t The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.2-170TEXAS -I.!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54AS841, SN54AS842SN74AS841, SN74AS84210·BIT BUS INTERFACE O·TYPE LATCHES WITH 3·STATE OUTPUTS• AS841 switching characteristics (see Note 1)Vcc = 4.5 V to 5.5 V.CL = 50 pF.R1 = 500 n.PARAMETERFROMTOR2 = 500 n. UNIT(INPUT)(OUTPUT)TA = MIN to MAXSN54AS841SN74AS841MIN MAX MIN MAXtpLH 1 8.5 1 6.5D Q nstpHL f'I 1 10 1 9tPLH 2 13 2 12C QtpHL 2 13 2 12nstpZH2 13.5 2 10.5OCQtpZL 2 15 2 13.5nstpHZ1 10 1 8OCQtpLZ 1 10 1 8ns• AS842 switching characteristics (see Note 1)Vcc = 4.5 V to 5.5 V.CL = 50 pF.R1 = 500 n.PARAMETERTA = MIN to MAXFROM(INPUT)TO(OUTPUT)R2 = 500 n. UNITSN54AS842SN74AS842MIN MAX MIN MAXtpLH1 11 1 8.5DQtpHL 1 10 1 9tpLH 2 13 2 12C QtpHL 2 13 2 12nstpZH2 14.5 2 125CQtpZL 2 15 2 12.5nstpHZ1 10 1 8OCQtpLZ ' 1 10 1 8nsnsEllenQ)(,)'S:Q)cen...JNOTE 1: Load circuit and voltage waveforms are. shown in Section 1.TEXAS~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-171

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SN54ALS843, SN54ASB43, SN54ALS844, SN54AS844SN74ALS843, SN74ASB43, SN74ALS844, SN74AS8449-81T BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTSD2910. DECEMBER 1983-REVISED DECEMBER 1985• 3-State Buffer-Type Outputs Drive Bus-LinesDirectly• Bus-Structured PinoutoProvide Extra Bus Driving LatchesNecessary for Wider Address/Data Paths orBuses with Parityo Buffered Control Inputs to Reduce DCLoadingo Power-Up High Impedance• Package Options Include Both Plastic andCeramic Chip Carriers in Addition to Plasticand Ceramic DIPs• Dependable Texas Instruments Quality andReliabilitydescriptionThese 9-bit latches feature three-state outputsdesigned specifically for driving highly capacitiveor relatively low-impedance loads. They areparticularly suitable for implementing bufferregisters, I/O ports, bidirectional bus drivers, andworking registers.The nine latches are transparent Ootype. The'ALS843 and' AS843 have noninverting data (0)inputs. The' ALS844 and' AS844 have invertingo inputs.A buffered output control (OC) input can be usedto place the nine outputs in either a normal logicstate (high or low levels) or a high-impedancestate. In the high-impedance state, the outputsneither load nor drive the bus lines significantly.The high-impedance state and increased driveprovide the capability to drive the bus lines in abus-organized system without need for interfaceor pull-up components.The output control (OC) does not affect theinternal operation of the flip-flops. Old data canbe retained or new data can be entered while theoutputs are off.The -1 versions of the SN74ALS843 andSN74ALS844 parts are identical to the standardversions except that the recommendedmaximum IOL is increased to 48 milliamperes.There are no -1 versions of the SN54ALS843and SN54ALS844.SN54ALS843. SN54AS843 ... JT PACKAGESN74ALS843. SN74AS843 ... OW OR NT PACKAGE(TOP VIEW)6C 24 VCC10 23 102D 3 22 203D 21 304D 20 4050 6 19 506D 18 607D 17 70SO 16 SO90 10 15 90CLR 11 14 PREGND 12 13 CSN54ALS843. SN54AS843 ... FK PACKAGESN74ALS843. SN74AS843 ... FN PACKAGE(TOP VIEWl~ ~Ig ~ ~~ ~4 3 2 1 2827 2612 131415 161718SN54ALS844. SN54AS844 ... JT PACKAGESN74ALS844. SN74AS844 ... OW OR NT PACKAGE6C(TOP VIEW)VCC102035 21 3045 20 4055 6 19 5065 18 6075 17 70s5 16 so95 10 15 90CLR 11 14 PREGND 12 13 CSN54ALS844. SN54AS844 ... FK PACKAGESN74ALS844. SN74AS844 ... FN PACKAGE(TOP VIEW)u1~1~lg ~ ~~ ~4 3 2 1 28 27 2635 3045 4055 7 50NCNC65 6075 70s5 11 SG12131415161718t/)Q)U'SQ)cen..JNC - No internal connectionPRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments~~~~~~~~i~a{~~I~~~ ~!~~~~ti~t" fllo::~:~:t:r~~s notTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1983. Texas Instruments Incorporated2-173

SN54ALS843, SN54AS843, SN54ALS844, SN54AS844SN74ALS843, SN74AS843, SN74ALS844, SN74AS8449·BIT BUS INTERFACE D·TYPE LATCHES WITH 3·STATE OUTPUTSThe SN54ALS843, SN54AS843, SN54ALS844, and SN54AS844 are characterized for operation overthe full military temperature range of - 55°C to 125°C. The SN74ALS843, SN74AS843, SN74ALS844,and SN74AS844 are characterized for operation from OOC to 70°C.'ALS843. 'AS843 FUNCTION TABLEINPUTSOUTPUTPRE CLR OC C D QL X L X X H'H L L X X LH H L H L LH H L H H HH H L L X 00X X H X X Z, ALS843, , AS843 logic diagram (positive logic)6C (1)PRE .:.;( 1,-,,4)'---- 2'\720 (3)3D (4)40 (5)50 (6)60 (7)70 (B)BO (9)90 (10)(23) lQ(22) 2Q(21) 3Q(20) 4Q(19) 5Q(18) 6Q(17) 7Q(16) BQ(15) 9Q40 '(5)(19) SQtThis symbol is in accordance with ANSI/IEEE Std91-1984 andlEe Publication 617-12.Pin numbers shown are for OW. JT. and NT packages.(17) 7QBO (9)(16) SQ90 (10)2-174'TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54ALS843, SN54AS843, SN54ALS844, SN54AS844SN74ALS843, SN74AS843, SN74ALS844, SN74AS8449·BIT BUS INTERFACE D·TVPE LATCHES WITH 3·STATE OUTPUTS'ALS844, 'AS844 FUNCTION TABLEINPUTSOUTPUTPRE CLR OC C D 0L X L X X HH L L X X LH H L H L HH H L H H LH H L L X 00X X H X X Z, ALS844, , AS844 logic diagram (positive logic)6C (1)_(14)PRE10 (2), ALS844, , AS844 logic symbol t20 (3)3D (4)(23) 10(22) 20(21) 30(20) 40(19)50(18) 60(17) 70(16) 80(15)9Qt This symbol is in accordance with ANSI/IEEE Std 91-1984 andlEe Publication 617-12,Pin numbers shown are for DW, JT, and NT packages,40 (5)50 (6)60 (7)70 (8)enQ)(,)'SQ)Cen..J80 (9)9'0 (10)absolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, Vee "" , , , ......................................... _ . _ . . . . .. 7 VInput voltage .............................................................. 7 VVoltage applied to a disabled 3-state output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VOperating free-air temperature range: SN54ALS', SN54AS' ............. _ . .. - 55 DC to 125 DCSN74ALS', SN74AS' .................... , oDe to 70 D eStorage temperature range ......................................... - 65 DC to 150 DCTEXAS "J}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-175

SN54ALS843, SN54ALS844SN74ALS843, SN74ALS8449·BIT BUS INTERFACE D·TVPE LATCHES WITH 3·STATE OUTPUTSrecommended operating conditionsSN54ALS843SN54ALS844MIN NOM MAXVee Supply voltage 4.5 5 55VIH High-level input voltage 2VIL Low-level input voltage 0.8IOH High-level output current -112IOL Low-level output currenttw Pulse durationI eLR or PRE low 40I C high 25tsu Setup time, data before enable e! 16th Hold time, data after enable e! 7TA Operating free-air temperature - 55 125SN74ALS843SN74ALS844MIN NOM MAXUNIT4.5 5 5.5 V35202 V0.8 V-2.6 mA2448 t mAns10 ns5 ns0 70 °etThe 48-mA limit applies for SN74ALS843-1 and SN74ALS844-1 only and only if Vee is maintained between 4.75 V and 5.25 V.. electrical characteristics over recommended operating free-air temperature range (unless otherwiseBnoted) .rencCD

, ALS843 switching characteristics (see Note 1)SN54ALS843, SN54ALS844SN74ALS843, SN74ALS8449·BIT BUS INTERFACE O·TVPE LATCHES WITH 3·STATE 'OUTPUTSVcc - 5 V. vec - 4.5 V to 5.5 V.Cl - 50 pF. Cl = 50 pF.R1 .. 500 n. R1 - 500 n.FROMTOPARAMETER R2 - 500 n. R2 - 500 n. UNIT(INPUT)(OUTPUT)TA - 25°e TA - MIN to MAX'AlS843 SN54AlS843 SN74AlS843MIN TVP MAX MIN MAX MIN MAXtpLH 7 11 2 15 2 13D Q nstpHL 11 15 4 20 4 18tpLH 12 18 5 25 5 21C QtPHL 16 23 8 30 8 26nstpLH13 19 5 25 5 22PREQtpHL 19 26 4 35 6 30nstpLH19 26 4 35 6 30CLRQtpHL 14 21 6 27 6 23nstpZH7 10 2 14 2 12OCQtpZL 9 12 4 16 4 14tpHZ6 9 2 12 2 10OCQtPLZ 7 10 2 14 2 12, ALS844 ~witching characteristics (see Note 1)Vee = 5 V. vee" 4.5 V to 5.5 V.el .. 50 pF.el = 50 pF.R1 - 500 n. R1 .. 500 n.FROMTOPARAMETER R2 .. 500 n. R2 - 500 n. UNIT(INPUT)(OUTPUT)TA .. 25°e TA - MIN to MAX'AlS844 SN54AlS844 SN74AlS844MIN TVP MAX MIN MAX MIN MAXtpLH11 16 4 22 4 20DQtpHL 9 13 3 17 '3 15tpLH 17 24 8 32 8 29CQtpHL 14 19 6 26 622tpLH13 19 5 25 5 22PREQtpHL 19 26 4 35 6 30tpLH19 26 4 35 6 30CLRQtpHL 16 23 8 29 825tpZH10 15 2 19 4 17OCQtpZL 12 18 3 22 520tpHZ7 10 1 12 1 11OCQtpLZ 5 9 1 14 1 12nsnsnsnsnsnsnsns•NOTE 1: Load circuit and voltage waveforms are shown in Section 1,TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652·177

SN54AS843. SN54AS844SN74AS843. SN74AS8449·BIT BUS INTERFACE D·TYPE .LATCHES WITH 3·STATE OUTPUTSIrOOCCD

SN54AS843, SN54AS844SN74AS843, SN74AS8449·BIT BUS INTERFACE O·TYPE LATCHES WITH 3·STATE OUTPUTSI AS843 switching characteristics (see Note 1)PARAMETERFROM(INPUT)TO(OUTPUT)Vee = 4.5 V to 5.5 V,el = 50 pF,R1 = 500 {l,R2 = 500 {l,TA = MIN to MAXSN54AS843SN74AS843MIN MAX MIN MAXtpLH 1 8.5 1 6.5DQtpHL 110 1 9tpLH 2 13 2 12C 0 nstpHL 2 13 2 12tpLH PRE Q 2 12 2 10 nstpHL CLR Q 2 14 2 13 nstpZH2 13.5 2 10.5OCQtpZL 2 15 2 13.5nstpHZOCQ1 10 1 13nstpLZ 1 10 1 8UNITns'AS844 switching characteristics (see Note 1)PARAMETERVee = 4.5 V to 5.5 V,el = 50 pF,R1 = 500O,FROMTOR2 = 500O,(INPUT)(OUTPUT)TA = MIN to MAXUNITSN54AS844 SN74AS844MIN MAX MIN MAXtpLHDQ1 11 1 8.5tpHL 1 11 1 10nstpLH2 14 2 12.5C 0tpHL 2 14 2 13nstpLH PRE Q 2 12 2 10 nstpHL CLR Q 2 14.5 2 13.5 nstpZH2 14.5 2 12OCQtpZL ·2 15 2 13.5nstpHZOCQ1 10 1 8nstpLZ 1 10 1 8tnQ)(JoS;cQ)en-INOTE 1: Load circuit and voltage waveforms are shown in Section 1.TEXAS -1!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-179

SN54ALS843, SN54AS843, SN54ALS844, SN54AS844SN74ALS843, SN74AS843, SN74ALS844, SN74AS8449·81T BUS INTERFACE D·TYPE LATCHES WITH 3·STATE OUTPUTSD latch signal conventionsIt is normal TI practice to name the outputs and other inputs of a O-type latch and to draw its logic symbolbased on the assumption of true data (0) inputs. Then outputs that produce data in phase with the datainputs are called Q and those producing complementary data are called Q. An input that causes a Q outputto go high or a Q output to go low is called Preset; an input that causes a Q output to go high or a Qoutput to go low is called Clear. Bars are used over these pin names (PRE and CLR) if they are active low.The devices on this data sheet are second-source designs and the pin-name conventions used by the originalmanufacturer have been retained. That makes it necessary to designate the data inputs and outputs ofthe inverting circuit '5 and Q.In some applications it may be advantageous to redesignate the inputs and outputs '5 and Q for thenoninverting circuits or 0 and Q for the inverting circuits. In that case signal names should change as shownbelow. Also shown are corresponding changes in the logic symbols.Notice that Q becoming Q causes PRE and CLR to exchange their names and their Sand R function labels.The presence or absense of polarity indicators ( ~ ) changes at the data inputs and outputs, but not atPRE, CLR, and OC since these inputs are still active-low .lEIrCJ)CCD

SN54ALS845, SN54AS845, SN54ALS846, SN54AS846SN74ALS845, SN74AS845, SN74ALS846, SN74AS8468-BIT BUS INTERFACE D-TVPE LATCHES WITH 3-STATE OUTPUTS02825, DECEMBER 1983-REVISED JANUARY 1986• 3-State Buffer-Type Outputs Drive Bus-LinesDirectly• Bus-Structured Pinout• Provides Extra Bus Driving LatchesNecessary for Wider Address/Data Paths orBuses with Parity• Buffered Control Inputs to Reduce DCLoading'• Power-Up High-Impedance State• Package Options Include Both Plastic andCeramic Chip Carriers in Addition to Plasticand Ceramic DIPs• Dependable Texas Instruments Quality andReliabilitydescriptionThese 8-bit latches feature three-state outputsdesigned specifically for driving highly capacitiveor relatively low-impedance loads. They areparticularly suitable for implementing bufferregisters, I/O ports, bidirectional bus drivers, andworking registers.The eight latches are transparent D-type. The'ALS845 and' AS845 have noninverting data (D)inputs. The' ALS846 and' AS846 have inverting5 inputs. Since CLR and PRE are independent ofthe clock, taking the CLR input low will causethe eight Q outputs to go low. Taking the PREinput low will cause the eight Q outputs to gohigh. When both PRE and CLR are taken low, theoutputs will follow the preset condition.The buffered output control inputs (OC 1, OC2,and OC3) can be used to place the eight outputsin either a normal logic state (high or low levels)or a high-impedance state. In the highimpedancestate, the outputs neither load nordrive the bus lines significantly. The highimpedancestate and increased drive provide thecapability to drive the bus lines in a busorganizedsystem without need for interface orpull-up components. The output controls do notaffect the internal operation of the latches. Olddata can be retained or new data can be enteredwhile the outputs are in the high-impedancestate.SN54ALS845. SN54AS845 . , . JT PACKAGESN74ALS845. SN74AS845 ... OW OR NT PACKAGE(TOP VIEW)3D 3040 4050 5060 6070 7080 10 15 80CLR 11 14 PREGND 12 13 CSN54ALS845. SN54AS845 ... FK PACKAGESN74ALS845. SN74AS845 ... FN PACKAGENC(TOP VIEW)01~lu u 1318 a -ooz>o_4 3 2 1 28 27 26203040NC506070SN54ALS846. SN54AS846 ... JT PACKAGESN74ALS846. SN74AS846 ... OW OR NT PACKAGE(TOP VIEW)607580 10CLR 11GND 12151413VCCOC31020304050607080PRECSN54ALS846. SN54AS846 ... FK PACKAGESN74ALS846. SN74AS846 ... FN PACKAGE45NC(TOP VIEW)191QIg ~ ~IQ ~4 3 2 1 28 27 2675 1112 13 14 15 16 17 18203040NC5060IIt/)Q)CJ"S:Q)cen..JNC - No internal connectionThis document contains information on products inmore than one phase of development. The status ofeach device is indicated on the pagels) specifying itselectrical characteristics.TEXAS l!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1983, Texas Instruments Incorporated2-181

SN54ALS845, SN54AS845, SN54ALS846, SN54AS846SN74ALS845, SN74AS845, SN74ALS846, SN74AS8468·BIT BUS INTERFACE O·TVPE LATCHES WITH 3·STATE OUTPUTSThe -1 versions of the SN74ALS845 and SN74ALS846 parts are identical to the standard versions exceptthat the recommended maximum IOL is increased to 48 milliamperes. There are no -1 versions of theSN54ALS845 and SN54ALS846.The SN54ALS845. SN54AS845. SN54ALS846. and SN54AS846 are characterized for operation overthe full military temperature range of - 55°C to 125°C. The SN74ALS845. SN74AS845. SN74ALS846.and SN74AS846 are characterized for operation from ooe to 70°C.FUNCTION TABLES• ALS845 •• AS845• ALS846 •• AS846II~ logic symbols tCCD

SN54ALS845, SN54AS845, SN54ALS846, SN54AS846SN74ALS845, SN74AS845, SN74ALS846, SN74AS8468-BIT BUS INTERFACE OoTYPE LATCHES WITH 3-STATE OUTPUTSlogic diagrams (positive logic)I ALS845, I AS845I ALS846, I AS846OC'l -:-(1::.;.)____,OC2~(2~)-----~OC3 ..:.;;(20.0 3 .:..)------'PRE (14)OCl7:(l,,) ____,Oc2 ,--(2-,)_____ ~OC3 _(2_3)___----'PRE~C (13)5210 (3)(22) 1010 _(3_) ----+-+---+-(:..;...16;;...:,.) 7075~--t-++--~(~15...:..) 8085 (10 )R(15)>---80Pin numbers shown are for DW. JT. and NT packages.absolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage. Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VInput voltage ............................................................ '.. 7 VVoltage applied to a disabled 3-state output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VOperating free-air temperature range:SN54ALS845. SN54AS845. SN54ALS846. SN54AS846 ............... -55°Cto 125°eSN74ALS845. SN74AS845. SN74ALS846. SN74AS846 ................. -DoC to 70 0 eStorage temperature range ......................................... - 65°C to 150 °eTEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-183

SN54ALS845, SN74ALS8458·BIT BUS INTERFACE D·TYPE LATCHES WITH 3·STATE OUTPUTSrecommended operating conditionsMINSN54ALS845SN74ALS845NOM MAX MIN NOM MAXVee Supply voltage 4.5 5 5.5 4.5 5 5.5 VVIH High-level input voltage 2 2 VVIL Low·level input voltage 0.8 0.8 V10H High-level output current -1 - 2.6 mA12 24IOL Low·level output current48 t mAPulse duration IeLR or PR~ low 40 35twI e high 25 20 nstsu Setup time. data before enable e~ 16 10 nsth Hold time. data after enable e~ 7 5 nsTA Operating free·air temperature -55 125 0 70 DetThe extended limit applies only if Vee is maintained between 4.75 V and 5.25 V. The 48 mA limit applies for SN74ALS845-1 only.UNITrencCD

SN54ALS845, SN74ALS8458·BIT BUS INTERFACE O·TVPE LATCHES WITH 3·STATE OUTPUTSswitching characteristics (see Note 1)Vce - 5 V. Vee - 4.5 V to 5.5 V.eL - 50 pF. CL - 50 pF.R1 - 500 fl. R1 - 500 fl.FROMTOPARAMETER R2 - 500 fl. R2 - 500 fl. UNIT(INPUT) (OUTPUT)TA - 25°e TA - MIN to MAX'ALS845 SN54ALS845 SN74ALS845MIN TYP MAX MIN MAX MIN MAXtpLH 7 11 2 15 2 130 Q nstpHL 11 15 4 20 4 18tpLH 12 18 5 25 5 21C Q nstpHL 16 23 8 30 8 26tpLH13 19 5 25 6 22 nsPREQtpHL 19 26 4 35 6 30 nstpLH19 26 4 35 6 30 nsCLRQtpHL 16 22 6 28 6 24 nstpZH9 14 2 18 3 16OCQnstpZL 12 17 4 20 5 18tpHZ4 9 1 12 1 11OCQnstpLZ 6 11 2 14 2 12NOTE 1: Load circuit and voltage waveforms are shown in Section 1.IIenQ)(.)0$Q)CC/)...IPRODUCTION DATA documents contain informationcurrent as of 'publication date. Products conform tothese specifications per the terms of TexasInstruments standard warranty. Productionprocessing does not necessarily include testing of allparameters.TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-185

SN54ALS846, SN74ALS8468·BIT BUS INTERFACE D·TYPE LATCHES WITH 3·STATE OUTPUTSPRODUCTPREVIEWrecommended operating conditionsSN54AlS846MIN NOM MAXVee Supply voltage 4.5 5 5.5VIH High-level input voltage 2Vil low-level input voltage 0.810H High-level output current -11210l low-level output currenttw Pulse durationtsu Setup time, data before enable e!th Hold time, data after enable e!IelR or PRE lowI e highTA Operating free-air temperature -55 125SN74AlS846UNITMIN NOM MAX4.5 5 5.5 V2 V0.8 V-2.6 mA2448 tmAnsnsns0 70 °etThe extended limit applies only if Vee is maintained between 4.75 V and 5.25 V. The 48 mA limit applies for SN74AlS846-1 only.electrical characteristics over recommended operating free-air temperature range (unless otherwiseBnotedlr(IJCCDc::n"CDenPARAMETERTEST CONDITIONSVIK Vee = 4.5 V, II = -18 mAVee = 4.5 V to 5.5 V, 10H = -0.4 mAVOH Vee = 4.5 V, 10H = -1 mAVee = 4.5 V, 10H - -2.6 mAVee = 4.5 V,10l = 12 mAVOL Vee = 4.5 V, 10l = 24 mA(lOl = 48 mA for -1 versions)10ZH Vee = 5.5 V, . Vo = 2.7 V10Zl Vee = 5.5 V, Vo = 0.4 VII Vee = 5.5 V, VI = 7 VIIHI Vee = 5.5 V, VI = 2.7 VIII Vee = 5.5 V, VI = 0.4 Vlo§ Vee = 5.5 V, Vo = 2.25 VI Outputs highlee Vee = 5.5 V L Outputs lowI Outputs disabledSN54AlS846SN74AlS846MIN TYP* MAX MIN TYP* MAX~ All typical values are at Vee = 5 V, T A = 25°e.§ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.UNIT-1.2 -1.2 VVcc- 2 Vcc- 22.4 3.3 V0.25 0.4Additional information on these products can be obtained from the factory as it becomes available.2.4 3,20.35 0.520 20 JlA-20 -20 JlA0.1 0.1 mA20 20 JlA-0.1 -0.1 mA-30 -112 -30 -112 mAVmAPRODUCT PREVIEW documents contain informationC!1 pred!!!:!! i~ the le'r:::!!;: cr d;:i;:I p'ha.a Gf2-186 ::::i~~~a~i~~~ a~h~!:rgt:r~~~il~. f:::s I~~~ru:~~~~reserves the right to change or discontinue theseproducts without notice..: ..TEXAS '91./1INSTRUMENTSPOST OFFiCe BOX 225012 • DALLAS. TeXAS 75265

PRODUCTPREVIEWSN54ALS846, SN74ALS8468·BIT BUS INTERFACE D·TVPE LATCHES WITH 3·STATE OUTPUTSswitching characteristics (see Note 1)VCC ,- 5 V. VCC - 4.5 V to 5.5 V.CL - 50 pF. CL - 50 pF.R1 - 500 n. R1 - 500 n.FROMTOPARAMETER R2 - 500 n. R2 - 500 n. UNIT(INPUT)(OUTPUT)TA - 25°C TA - MIN to MAX'ALS846 SN54ALS846 SN74ALS846MIN TYP MAX MIN MAX MIN MAXtpLHD Q nstpHLtpLHC Q nstpHLtPLHPREQnstpHLnstpLHCLRQnstpHLnstpZHOC Q nstpZLtpHZOC Q nstpLZNOTE 1: Load circuit and voltage waveforms are shown in Section 1.Additional information on these products can be obtained from the factory as it becomes available.•r.nQ)(.)0>Q)cen...JPRODUCT PREVIEW documents contain informationon products in the formative or design phase ofdevelopment. Characteristic data and otherTEXAS ..specifications are design goals. Texas Instrumentsreserves the right to change or discontinue these INSTRUMENTSproducts without notice.POST OFFICE BOX 225012 • DALLAS, TEXAS 752652-187

SN54AS845, SN54AS846SN74AS845, SN74AS8468-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTSrecommended operating conditionsSN54AS845SN54AS846MIN NOM MAXVCC Supply voltage 4.5 5 5.5VIH High-level input voltage 2Vil low-level input voltage 0.8IOH High-level output current -24IOl low-level output current 32I ern or PRE low 5tw Pulse durationI C high 5tsu Setup time, data before enable C! 3.5th Hold time, data after enable C! 3.5tr Recovery timePRE 17I ClR 16TA Operating free-air temperature -55 125SN74AS845SN74AS846 UNITMIN NOM MAX4.5 5 5.5 V2 V0.8 V- 24 mA48 mA4ns42.5 ns2.5 ns15ns140 70 °celectrical characteristics over recommended operating free-air temperature range (unless otherwiseBnoted)SN54AS845SN74AS845rencCD

, AS845 switching characteristics (see Note 1)SN54AS845, SN54AS846SN74AS845, SN74AS8468·BIT BUS INTERFACE O·TVPE LATCHES WITH 3·STATE OUTPUTSVcc - 4.5 V to 5.5 V.CL - 50 pF.R1 - 500 n.FROMTOPARAMETER R2 - 500 n. UNIT(INPUT)(OUTPUT)TA - MIN to MAXSN54AS845SN74ASU45MIN MAX MIN MAXtpLH 1 8.5 1 6.5D Q nstpHL 1 10 1 9tpLH 2 13 2 12C Q nstpHL 2 13 2 12tpLH PRE Q 2 12 2 10 nstpHL CLR Q 2 14 2 13 nstpHLOCQ2 13.5 2 10.5tpZL 2 15 2 13.5tpHZ1 10 1 8OCQtpLZ 1 10 1 8, AS846 switching characteristics (see Note 1)Vcc - 4.5 V to 5.5 V.CL - 50 pF.R1 - 500 n.FROMTOPARAMETER R2 - 500 n. UNIT(INPUT)(OUTPUT)TA - MIN to MAXSN54AS846SN74AS846MIN MAX MIN MAXtPLH 1 11 1 8.5D Q nstpHL 1 11 1 10tpLH 2 14 2 12.5C Q nstpHL 2 14 2 13tpLH PRE Q 2 12 2 10 nstpHL CLR Q 2 14.5 2 13.5 nstpHLOCQ2 14.5 2 12tpZL 2 15 2 13.5tpHZ1 10 1 8OCQtpLZ 1 10 1 8nsnsnsnsII(J)Q)(.)os:Q)cen-INOTE 1: Load circuit and voltage waveforms are shown in Section 1.PRODUCTION DATA documents contain informationcurrent as of publication date. Products conform t~specifications per the terms of Texas Instruments~~~~~:~~i~a{~~I~lJe ~!~:i~~ti~r ~~o::~:~:t~rOs~s notTEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-189

IrencCD

SN74AS850, SN74AS8511 OF 16 DATA SELECTORS/MULTIPLEXERS WITH 3·STATE OUTPUTS02822, DECEMBER 1983-REVISED JANUARY 1986• 4·Line to 1·Line Data Selectors/MultiplexersThat Can Select 1 of 16 Data Inputs.Typical Applications:Boolean Function GeneratorsParallel·to·Serial ConvertersData Source Selectors• Cascadable to n·Bits• 3·State Bus Driver Outputs• • AS850 Offers Clocked Selects; • AS851Offers Enable·Controlied Selects• Has a Master Output Control (G) forCascading and Individual Output Controls(GY. GW) for Each Output• Package Options Include both Plastic andCeramic Carriers in Addition to Plastic andCeramic DIPs• Dependable Texas Instruments Quality andReliabilitydescriptionThese four·line to one-line dataselectors/multiplexers provide full binarydecoding to select one-of-sixteen' data sourceswith complementary Y and W outputs. The• AS850 has a clock-controlled select registerallowing for a symmetrical presentation of theselect inputs to the decoder while the' AS851has an enable-controlled select register allowingthe user to select and hold one particular dataline.A buffered group of output controls (G, GY, GW)can be used to place the two-outputs in eithera normal logic (high or low logic level) or a highimpedancestate. In the high-impedance statethe outputs neither load nor drive the bus linessignificantly. The high-impedance third state andincreased drive provide the capability to drive thebus lines in a bus-organized system without theneed for interface or pull-up components.SN74AS850; SN74AS851 ... N PACKAGED7D6D5D4D3D2D1DOGYGGWCLK/SC*WGND(TOP VIEW)VCCD8D9D10D11D12D13D14D15ySOS1S2S3SN74AS850, SN74AS851 ... FN PACKAGED3 5D2 6D1 7DO 8GY 9G 10GW 11(TOP VIEW)Uq-LO004 3 2 1 28272612 131415161718*:S:ClMN.-OIU z (f) (f) (f) (f)~ t9~...JU25242322212019'ClK for 'AS850 or SC for 'AS851The output controls do not affect the internal operations of the data selector/multiplexer. New data canbe' setup while the outputs are in the high-impedance state.The SN74AS850 and SN74AS851 are characterized for operation from ooe to 70oe.010011012013014015YEllenQ)(,)0>Q)cen-IPRODUCTION DATA documents containinformation currant as of publication data.:fod~~~~:onl~:~ut~:~:;ifi;:i~~~~Nar !~~::~~~Production processing does not necassarJyinclude testing of all parameters.TEXAS ~INSTR(jMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1983, Texas Instruments Incorporated2-191

SN74AS850. SN74AS8511 OF 16 DATA SELECTORS/MULTIPLEXERSWITH 3-STATE OUTP.UTSIIrencCD

SN74AS850, SN74AS8511 OF 16 DATA SELECTORS/MULTIPLEXERSWITH 3·STATE OUTPUTS, AS850 logic diagrams (positive logic) (see inset for' AS851)'AS851SELECTIONLATCHES00(81~1IORi(7101(6102(5103(4104(310506 (21(1107EllU)Q)(.)oSQ)Cen-I08 (27109 (261010 (251011 (241012 (231013 (221(211014015 (201TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-193

SN74AS850, SN74AS8511 OF 16 DATA SELECTORS/MULTIPLEXERSWITH 3-STATE OUTPUTStsu Setup time. select inputs before elKi 10 nsIrencCD

SN74AS8501 OF 16 DATA SELECTORS/MULTIPLEXERSWITH 3·STATE OUTPUTSSN74AS850 switching characteristics (see Note 1)Vee = 4.5 V to 5.5 V.PARAMETERf maxtpLHtpHLtpLHtpHLtpLHtpHLtpLHtpHLtpZHtpZLtpHZtpLZtpZHtpZLtpHZtpLZtpZHtpZLtpHZtpLZtpZH. tpZLtpHZtPLZFROM(INPUT)Any DAny DCLKCLKITITITITGYGYGWGWTOeL = 50 pF.R1 = 500 fl.(OUTPUT) R2 - 500 fl.YWYWYYWWYYWWTA - oDe to 70°CMINMAXUNIT60 MHz3 10.53 113 81 63 14.53 17.53 153.5 132 83 111 62 82 83 211 62 82 83 111 62 82 103 251 62 11nsnsnsnsnsnsnsnsnsnsnsnsIIU)Q)(.)'SQ)cen...JNOTE 1: Load circuit and voltage waveforms are shown in Section 1.TEXAS -Ii}INSTRUMENTSPOST OFFICE BOX 225012 • OALLAS. TEXAS 752652-195

SN74AS8511 OF 16 DATA SELECTORS/MULTIPLEXERSWITH 3-STATE OUTPUTSSN74AS851 recommended operating conditionsVeeVIHVILIOHIOLtwtsuthTASupply voltageHigh-level input voltageLow-level input voltageHigh·level output currentLow-level output currentPulse duration. se lowSetup time. select inputs before setHold time. select inputs after SetOperating free-air temperatureMIN NOM MAX UNIT4.5 5 5.5 V2 V0.8 V-15 mA48 mA10 ns4.5 ns0 ns0 70 °eSN74AS851 electrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)IIPARAMETER TEST CONDITIONS MIN Typt MAX UNITVIK Vee = 4.5 V. II = -18 mA -1.2 eVOHVee = 4.5 V to 5.5 V. 10H = -2 mA VCc- 2Vee = 4.5 V. 10H = -15 mA 2 3.3VOL Vee = 4.5 V. 10L = 48 mA 0.35 0.5 VIOZH Vee = 5.5 V. Vo = 2.7 V 50 /lAIOZL Vee = 5.5 V. Vo = 0.4 V -50 /lAII Vee = 5.5 V. VI = 7 V 0.1 mAIIH Vee = 5.5 V. VI = 2.7 V 20 /lAID.G -1IlLVee = 5.5 V. VI = 0.4 V mA-0.5I All otherslot Vee = 5.5 V. Vo = 2.25 V -30 -112 mAOutputs active 50 81lee Vee = 5.5 V mAI Outputs disabled52 85Vt All typical values are at Vee = 5 V. T A = 25 °C.t The output conditions have been chosen to produce a current that closely approximates one-half of the true short·circuit current. lOS.2-196 TEXAS -1.!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN74AS8511 OF 16 DATA SELECTORS/MULTIPLEXERSWITH 3-STATE OUTPUTSSN74AS851 switching characteristics (see Note 1)Vee = 4.5 V to 5.5 V.PARAMETERtpLHtpHLtpLHtpHLtpLHtpHLtpLHtpHLtpLHtpHLtpLHtpHLtpZHtpZLtpHZtpLZtpZHtpZLtpHZtpLZtpZHtpZLtpHZtpLLtpZHtpZLtpHZtpLZFROM(INPUT)Any 0Any 050.51.52.5350.51.52.535C5CGGGGGYGYGWGWTO(OUTPUT)YWYWYWYYWWYYWWeL = 50 pF.Rl = 500 fl.R2 = 500 fl.TA = oDe to 70 D eMINMAX3 10.53 113 81 63 183 193 163 153 183 203 163152 83 111 62 82 83211 6282 83 111 62 82 103251 62 11UNITnsnsnsnsnsnsnsnsnsnsnsnsnsnsenQ)(J"S;Q)cen..JNOTE 1: Load circuit and voltage waveforms are shown in 5ection 1.TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-197

SN74AS850, SN74AS8511 OF 16 DATA SELECTORS/MULTIPLEXERSWITH 3-STATE OUTPUTSTYPICAL APPLICATION DATAThe 'AS850 or' AS851 can be used as a 1-of-16 Boolean function generator. Figure 1 shows the' AS850in one example.rrn- cCD-BIN/OCTLJO ~IEN ~~3 !:::--,Iuk!4 ...... ~~1 5'"~2 6~-,r4 7 ......•-~ 'AS850~-D4~G20 MUX~ 20EN21GW20EN22ClKC23SO~708809 9'AS163 010 10CTROIV16 011- 11rut-..... 5CT=0 r---i 01212lOAQ..,...."D13Ml13RCaL M2 3CT=15 ~IDJ ~ 14ENTG3 ~ 15ENPG4ClK ~ C5/2 34+ -ABC0-, , , ,.1,50OAOBOC~~"""'-L~V~L[>FIGURE 1. 1-of-16 BOOLEAN FUNCTION GENERATORSl~ D] 0S2GiSS323 D3DO0011 21'\7 ~ y022D334D55 22'\7 ~ W06 6a-_2-198 TEXAS ""f!IINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPICAL APPLICATION DATASN74AS8501 OF 16 DATA SELECTORS/MULTIPLEXERSWITH 3·STATE OUTPUTS'AS850G'G20MUXGY20EN21GW20EN22CLKCLOCK--------------------~~~~~ C238081S2 GiS8323 03DO0A--------------~+_~01223 OJ 0B---------------+~~ 456C--------------~. 789o-------------e 101112E 131415YWY2345 22'\76789101112014 131401515WFIGURE 2. 1·of·32 DATA SELECTOR/MUL TIPLEXERTEXAS -1.!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652·199

SN74AS8501 OF 16 DATA SELECTORS/MULTIPLEXERSWITH 3·STATE OUTPUTSIIIr-encCD

SN54AS852, SN74ASD52D-BIT UNIVERSAL TRANSCEIVER PORT CONTROLLERSD2810. JUNE 1984-REVISED JANUARY 1986• Included among the Package Options areCompact, 24-Pin, 300-mil-Wide DIPs andBoth 28-Pin Plastic and Ceramic ChipCarriersoBuffered 3-State Outputs Drive Bus LinesDirectly• Cascadable to n-BitsoooEight Selectable Transceiver/Port Functions:A to B or B to ARegister to ~ or BShifted to A from B or Shifted toBfrom AOff-Line Shifts (A and B PortsTransceiving or in High-ImpedanceState)Register ClearParticularly Suitable for Use in DiagnosticsCircuitrySerial Register Provides:- Parallel Storage of Either A or B InputDataSerial Transmission of Data from EitherA or B Port• Dependable Texas Instruments Quality andReliabilitydescriptionThe' AS852 features two 8-bit I/O ports (A 1-ASand 81-8S), and S-bit parallel-load, serial-in,parallel-out shift register, and control logic. Withthese features, this device is capable ofperforming eight selectable transceiver or portfunctions, depending on the state of the threeselect lines SO, S 1, and S2. These functionsSN54AS852 ... JT PACKAGESN74AS852 ... OW or NT PACKAGE(TOP VIEW)soS1VeeelKS2SERINA1 81A2 82A3 83A4 84A5 85A6 86A7 87A8 88GNDQ8SN54AS852 ... FKPACKAGESN74AS852 ... FN PACKAGE(TOP VIEW)4 3 2 1 282726A1 25 8124 8223 8322 NC21 8410 20 8511 19 8612131415161718NC-No internal connectioninclude: transferring data from port A to port 8 or vice versa (Le., the transceiver function), transferringdata from the register to either port, serial shifting data to either port from the opposite port, performingoff-line shifts (with A and 8 ports in high-impedance state), and clearing the register. The 'ASS52 cansimultaneously transfer data from A to 8 or 8 to A and perform an off-line serial shift of data in the register.Synchronous parallel loading of the internal register can be accomplished from either port on the positivetransition of the clock while serially shifting data in via the SERIN input. The I AS852 is ideally suited forapplications implementing diagnostic circuitry to enhance system verification and/or fault analysis. All serialdata is shifted right. All outputs are buffer-type outputs designed specifically to drive bus lines directlyand all are 3-state except for QS, which is a totem-pole output.The SN54AS852 is characterized for operation over the full military temperature range of - 55 °e to 125 °e.The SN74ASS52 is characterized for operation from ooe to 70oe.(/)Q)CJoSQ)cen...JPRODUCTION DATA documents containinformation current as of publication date.~;odT~!~~onl::~u~:~::ifi~:at~~~~ger ~~~::~~~Production processing does not necessariTyinclude testing of all parameters.TEXAS '1!1INSTRUMENlSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1983. Texas Instruments Incorporated2-201

SN54AS852, SN74AS8528·BIT UNIVERSAL TRANSCEIVER PORT CONTROLLERSlogic diagram (positive logic)lEIrencCD

SN54AS852, SN74AS8528·BIT UNIVERSAL TRANSCEIVER PORT CONTROLLERSFUNCTION TABLEMODE5251 50CLOCK 5ERIN A1 01 B1 A2 Q2 B2L L L H or L X Z an A1 Z On A2L L L t X Z A1 A1 Z A2 A2L L H H or L X B1 On Z B2 On ZL L H t X B1 B1 Z B2 B2 ZL H L H or L X X On 01 X On 02L H L t X Z A1 A1 Z A2 A2L H H H or L X 01 On X 02 On XL H H t X 81 81 Z 8282 ZH L L H or L X Z On A1 Z On A2H L L t H Z H A1 Z 01 A2H L L t L Z L A1 Z 01 A2H L H H or L X B10 n Z 82 On ZH L H t H 81 H Z 8201 ZH L H t L 81 L Z 8201 ZH H L H or L X Z On Z Z On ZH H L t H Z H Z Z 01 ZH H L t L Z L Z Z 01 ZH H H H or L X Z On Z Z OnH H H t X Z L Z Z L ZA3 03 B3 A4 04 B4 A5 05 B5 A6 06 86 A7 0787 A8 08 B8Z On A3 Z On A4 Z On A5 Z On A6 Z On A7 Z On A8A A3 A3 Z A4 A4 Z A5 A5 Z A6 A6 Z A7 A7 Z A8 A8B3 On Z B4 On Z B5 On Z B6 On Z B7 On Z B8 On ZB3 B3 Z 84 B4 Z B585 Z 86 B6 Z B787 Z 88 B8 ZX On 03 X On 04 X On 05 X On 06 X On 07 X On 08Z A3 A3 Z A4 A4 Z A5 A5 Z A6 A6 Z A7 A7 Z A8 A803 On X 04 On X 05 On X 06 On X 07 On X 08 On XB383 Z 8484 Z B585 Z 8686 Z B787 Z 8888 ZPORTFUNCTIONA TO B8 TO AON TO 8NON TO ANZ On A3 Z On A4 Z On A5 Z On A6 Z On A7 Z On A8 SHIFTZ 02 A3 Z 03 A4 Z 04 A5 Z 05 A6 Z 06 A7 Z 07 A8 ANDZ 02 A3 Z 03 A4 Z 04A5 Z 05 A6 Z 06 A7 Z 07 A8 A TO 883 On Z 84 On Z 85 On Z 86 On Z 87 On Z 88 On Z SHIFTB302 Z 8403 Z 8504 Z 8605 Z 8706 Z 8807 Z AND8302 Z 8403 Z 8504 Z 8605 Z B706 Z 8807 Z B TO AZ On Z Z On Z Z On Z Z On Z Z On Z Z On ZZ 02 Z Z 03 Z Z 04 Z Z 05 Z Z 06 Z Z 07 Z SHIFTZ 02 Z Z 03 Z Z 04 Z Z 05 Z Z 06 Z Z 07 ZZ On Z Z On Z Z On Z Z On Z Z On Z Z On ZZ L Z Z L Z Z L Z Z L Z Z L Z Z L Zn = level of 0n(n = 1,2, ... 8) established on the most recent t transition of ClK. 01 through 08 are the shift register outputs;only 08 is available externally. The double inversions that take place as data travels from port to port are ignored in this table.logic symbolt50 (1151 (2152 (31[PORT CONTROllERICLEARfI)Cl)(.)'S;Cl)CCI)...JClK (231(0/2110011/3110012Z14BlA2:11=0(0/2110015B2(1/31100Z17AS;'11=0(0/21100(1/3110033Z3535tThis symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12.Pin numbers shown are for DW, JT, and NT packages.TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DAllAS. TEXAS 752652-203

SN54AS852, SN74AS8528·BIT UNIVERSAL TRANSCEIVER PORT CONTROLLERSabsolute maximum ratings over free-air temperature rangeSupply voltage, Vee ......................................................... 7 VInput voltage: All inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VI/O ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VVoltage applied to a disabled 3-state output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VOperating free-air temperature range: SN54AS852 ....................... - 55°C to 125°CSN74AS852 ........................... ooe to 70°CStorage temperature range ......................................... - 65°C to 150°Crecommended operating conditionsVeeVIHVILIOHIOLfclocktwtsuthTASupply voltageHigh·level input voltageLow-level input voltageHigh-level output currentLow-level output currentClock frequencyDuration of clock pulseSetup time before eLK IHold-time, data after CLK IOperating free-air tempertureA 1-A8. 81-8808A1-A8.81-8808MIN4.52a11A1-A8. 81-88, 5ERIN 5.550. 51. 52 5.5A1-A8. 81-88, 5ERIN50,51,52 a-55aSN54AS852NOM5MAX5.50.8-12-2322045125SN74AS852MIN NOM MAXUNIT4.5 5 5.5 V2 V0.8 V-15-2mA48mA20a 50 MHz10 ns5.55.5nsaa. nsa 70 °C2-204TEXAS -I.!}INSTRUMENTSPOST OFFICE BOX 225012 • OALLAS. TEXAS 75265

SN54AS852, SN74AS8528-BIT UNIVERSAL TRANSCEIVER PORT CONTROLLERSelectrical characteristics over recommended operating free-air temperature range(unless otherwise noted)PARAMETERTEST CONDITIONSSN54AS852SN74AS852MIN Typt MAX MIN Typt MAXVIK Vee = 4.5 V, II = -18 mA -1.2 -1.2A1-A8,81-88Vee = 4.5 V, 10H = -12 mA 2.4 3.2VOH Vee = 4.5 V, 10H = -15 mA 2.4 3.3All outputs Vee = 4.5 V to 5.5 V, 10H = -2 mA Vcc- 2 vcc- 2ValIIVee = 4.5 V, 10l = 32 mA 0.3 0.5All outputs except 08 Vee = 4.5 V, 10l = 48 mA 0.35 0.508 Vee = 4.5 V, 10L = 20 mA 0.25 0.5 0.25 0.550,51,52 0.3 0.3Vee = 5.5 V,VI = 7 VelK and SERIN0.1 0.1A1-A8,81-88 Vee = 5.5 V, VI = 5.5 V 0.2 0.2SO, S1, S2 60 60IIH eLK and SERIN Vee = 5.5 V, VI = 2.7 V 20 20A1-A8,81-88 t 70 70SO, S1,52 -1 -1IlL eLK and SERIN Vee = 5.5 V, VI = 0.4 V -0.5 -0.5A1-A8,81-88 t -0.5 -0.510§Except 08 -30 -112 -30 -112Vee = 5.5 V, Va = 2.25 V08 -20 -112 -20 -112lee Vee = 5.5 V 136 220 136 220t All typical values are at Vce = 5 V, T A = 25 De.tFor 1/0 ports, the parameters IIH and IlL include the output currents 10ZH and 10ZL, respectively.§The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.switching characteristics (see Note 1)PARAMETERRl - 4.5 V to 5.5 V,el - 50 pF,R1 - 500 n,FROM TO R2 - 500 n,(INPUT) (OUTPUT) TA = MIN to MAXSN54AS852SN74AS852MIN MAX MIN MAXf max 45 50 MHztpLHtpHLAny A portAny 8 po~t2 9 2 7.53 12.5 3 11tpLHAny 8 portAny A port2 9 2 7.5tpHL3 12.5 3 11tpLHtpHLSO, S1, S2'Any A or 8 3 11.5 3 10port3 12 3 10.5tpLH Any A or 8 2 11 2 9CLKtpHL port 3 14 3 12.5tpLH 2 10.5 2 8eLK 08 nstpHL 3 11.5 3 10tpHZ 2 9 2 7tpLZ Any A or 8 3 13 310.5SO,S1, S2tpZHport2 9 2 7tpZL 3 13 3 10.5UNITVVVrnA{tArnAmArnAUNITnsnsnsnsnsnsenQ)ooS;Q)CCJ)...JNOTE 1: Load circuit and voltage waveforms are shown in Section 1., The positive transition of S1 control pin will cause lOW-level data on the A or 8 bus to be invalid for 17.5 ns.TEXAS.INSTRUMENlSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-205

SN54ASB52. SN74ASB52B·BIT UNIVERSAL TRANSCEIVER PORT CONTROLLERSTYPICAL APPLICATION DATABUS A TO BUS B ORSERIAL TRANSMISSION ,BUS B TO BUS A ORSERIAL TRANSMISSIONSERIAL INCLKSERIAL INCLKIAIII REGIII1 6IIII1 6IIIrencCD

SN54AS856, SN74AS8568-BIT UNIVERSAL TRANSCEIVER PORT CONTROLLERS02814, DECEMBER 1983 - REVISED MARCH 1985• Included Among the Package Options areCompact, 24-Pin, 300-mil-Wide DIPs andBoth 28-Pin Plastic and Ceramic ChipCarriersoBuffered 3-State Outputs Drive Bus LinesDirectly• Cascadable to n-Bits• Eight Selectable Transceiver/Port Functions:- B to A- Register to A and/or B- Off-Line Shifts (A and B Ports in High-Impedance State)- Shifted to A and/or B• Particularly Suitable for Use in DiagnosticsAnalysis Circuitryo Serial Register Provides:Parallel Storage of Either A or B InputDataSerial Transmission of Data from EitherA or B Port- Readback Mode B to Ao Dependable Texas Instruments Quality andReliabilitySN54AS856 ... JT PACKAGESN74AS856 ... OW or NT PACKAGE(TOP VIEW)OEBVCCOEAClKMODESERINA1B1A2B2A3B3A4B4A5B5. A6 B6A7B7A8B8GND 08SN54AS856 ... FK PACKAGESN74AS856 ... FN PACKAGE(TOP VIEW)WZOWWUU...Jwo,q: 1m U ~ ii:~OOZ>ucn4 3 2 1 28 27 26A1 25 B1A2 6 24 B2A3 7 23 B3NC 8 22 NCA4 9 21 B4A5 10 20 B5A6 11 19 B612 13 14 15 16 17 18(IJQ)(..)0>Q)cen..JNC-No internal connectiondescriptionThe' AS856 features two 8-bit I/O ports (A 1-A8 and B 1-B8), an 8-bit parallel-load, serial-in, parallel-outshift register, and control logic. With these features, this device is capable of performing eight selectabletransceiver or port functions, depending on the state of the three control lines OEA, OEB, and MODE. Thesefunctions include: transferring data from port A to port B or vice versa (i.e., the transceiver function), serialshifting data to either or both ports, and performing off-line shifts (with A and B ports active as transceiversin a high-impedance state). Synchronous parallel loading of the internal register can be accomplished fromeither port on the positive transition of the clock while serially shifting data in via the SERIN input. The'AS856 is ideally suited for applications needing signature-analysis circuitry to enhance system verificationand/or fault analysis. All serial data is shifted right. All outputs are buffer-type outputs designed specificallyto drive bus lines directly and all are 3-state except for 08, which is a totem-pole output.The SN54AS856 is characterized for operation over the full military temperaure range of - 55 °e to 125 °e.The SN74AS856 is characterized for operation from ooe to 70oe.PRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments~~~~~:~~i~a{~:I~~e ~!~~~~tigr fI\o::~:~~t:~s~s notTEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265Copyright © 1983, Texas Instruments Incorporated2-207

SN54AS856, SN74AS8568·BIT UNIVERSAL TRANSCEIVER PORT CONTROLLERSlogic diagram (positiye logic)OEB ...:..i1;.:..)----aOEA ...:.:(2:..:,.)_---aMODE ...,;.;(3:..:.)_----1CLK...:.:(2=3~) -~ ~0------+4-~------------,SE R IN ..::(2=2)~---a">-------.J-.I.-I-.....(21) B1rtf)(20) B2CCD

SN54AS856, SN74AS8568·BIT UNIVERSAL TRANSCEIVER PORT CONTROLLERSFUNCTION TABLEMODEMODE OEAOEBCLOCK SERIN Al 01 BlL L L H or L X 010101L L L t X 010101L L H H or L X 81 01 ZL L H t X 81 81 ZL H L H or L X Z 0101L H L t X Z Al AlL H H H or L X Z 01 ZL H H t X Z Al ZH L L H or L X 01 On 01H L L t H H H HH L L t L L L LH L H H or L X 01 On ZH L H t H H H ZH L H t L L L ZH H L H or L X Z On 01H H L t H Z H HH H L t L Z L LH H H H or L X Z On ZH H H t H Z H ZH H H t L Z L HA2 02 B2 A3 03 B3 A4 04 B4 A5 05 B5 A6 06 B6 A7 07 B7 A8 08 B8020202 030303 040404 050505 060606 Q7 Q7 07 080808020202 030303 040404 050505 060606 Q7 07 07 080808FUNCTIONFEEDBACKB202 Z B303 Z B404 Z B505 Z B606 Z 8707 Z B808 Z 8 to A8282 Z 83 83 Z 8484 Z 8585 Z 8686 Z 8787 Z 8888 Z A to 0Z 0202 Z 0303 Z 0404 Z 0505 Z 0606 Z 0707 Z 0808 A to 0Z A2 A2 Z A3 A3 Z A4 A4 Z A5 A5 Z A6 A6 Z A7 A7 Z A8 A8 o to 8Z 02 Z Z 03 Z Z 04 Z Z 05 Z Z 06 Z Z 07 Z Z 08 ZZ A2 Z Z A3 Z Z A4 Z Z A5 Z Z A6 Z Z A7 Z Z A8 ZA to 002 On 02 03 On 03 04 On 04 05 On 05 06 On 06 07 On 07 08 On 08 SHIFT010101 02 02 02 030303 040404 050505 060606 07 07 07 TO010101 020202 030303 040404 050505 060606 07 Q7 Q7 A and 802 On Z 03 On Z 04 On Z 05 On Z 06 On Z 07 On Z 08 On Z SHIFT0101 Z 0202 Z 0303 Z 0404 Z 0505 Z 0606 Z 07 Q7 Z TO0101 Z 0202 Z 0303 Z 0404 Z 0505 Z 0606 Z 07 Q7 Z AZ On 02 Z On 03 Z On 04 Z On 05 Z On 06 Z On 07 Z On 08Z 0101 Z 0202 Z 0303 Z 0404 Z 0505 Z 0606 Z 0707 TOZ 0101 Z 0202 Z 0303 Z '0404 Z 0505 Z 0606 Z 0707 BZ On Z' Z On Z Z On Z Z On Z Z On Z Z On Z Z On ZZ 01 Z Z 02 Z Z 03 Z Z 04 Z Z 05 Z Z 06 Z Z 07 ZZ 01 Z Z 02 Z Z 03 Z Z 04 Z Z 05 Z Z 06 Z Z 07 Zn = level of 0n1n = 1, 2 ... 8) established on most recent i transition of ClK. 01 through 08 are the shift register outputs; only 08is available externally. The double inversions that take place as data travels from port to port are ignored in this table.logic symbol tOEBOEAMODEClKSERINAlA2A3A4A5A6A7A8(1)(2)(3)(23)(22)(4)(5)(6)(71(8)(9)(10)(11)r-.. EN3r-.. EN4.'" MO1.-. MlZ2.,Z6>14- Z7\714- Z10\714- Z28\7 1-->{C5.,r1-06 1,507 0,50 31>~Z81-0r)Z910 0,50 31>~Zll1-0""'"-Z12-28 0,50 3[>~Z29Z30....r(21)(191(181(17)(16)(15)... (1!)......r (13)BlB2B3B4B5B6B7B808SHIFTSHIFT•(J)Q)o"S;Q)cen..JPin numbers shown are for OW, JT, and NT packages.tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.TEXAS "!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-209

SN54AS856, SN74AS8568-BIT UNIVERSAL TRANSCEIVER PORT CONTROLLERSabsolute maximum ratings over free-air temperature rangeSupply voltage, Vee ......................................................... 7 VInput voltage: All inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VI/O ports ..................................................... 5.5 VVoltage applied to a disabled 3-state output ...................................... 5.5 VOperating free-air temperature range: SN54AS856 ....................... - 55°C to 125°CSN74AS856 ........................... ooe to 70°CStorage temperature range ......................................... - 65°C to 150°Crecommended operating conditionsISetupSN54AS856SN74AS856MIN NOM MAX MIN NOM MAXUNITVCC Supply voltage 4.5 5 5.5 4.5 5 5.5 VVIH High-level input voltage 2 2 VVil low-level input voltage 0.8 0.8 VIOH High-level output currentA1-A8. B1-B8 -12 -1508-2 -2mAA1-A8. B1-B8 32 48IOl low-level output currentmA0820 20fclock Clock frequency 0 45 0 50 MHztw Duration of clock pulse 11 10 nsA1-A8. B1-B8 SERIN 5.5 5.5tsutime before ClK tnsOEB. OEA. MODE 5.55.5th Hold-time. data after ClKtA1-A8. B1-B8 SERIN 0 0OEB. OEA. MODE 0 0nsTA Operating free-air temperature -55 125 0 70 °c2-210 TEXAS -1.!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54AS856, SN74AS8568·BIT UNIVERSAL TRANSCEIVER PORT CONTROLLERSelectrical characteristics over recommended operating free-air temperature range(unless otherwise noted)PARAMETERTEST CONDITIONSSN54AS856SN74AS856MIN Typt MAX MIN Typt MAXVIK Vee = 4.5 V, II = -18 mA -1.2 -1.2Al-AS Vee = 4.5 V, 10H = -12 mA 2 3.2VOH Sl-BS Vee = 4.5 V, 10H = -15 mA 2 3.3All outputs Vee = 4.5 V to 5.5 V, 10H = -2 mA vcc- 2 vcc- 2ValIIVee = 4.5 V, 10l = 32 mA 0.25 0.5All outputs except OSVee = 4.5 V, 10l = 4S mA 0.35 0.5Q8 Vee = 4.5 V, 10l = 20 mA 0.5 0.5OEB, OEA, MODE 0.2 0.2Vee = 5.5 V,VI = 7 VelK and SERIN0.1 0.1Al-AS, Bl-BS Vee = 5.5 V, VI = 5.5 V 0.2 0.2OEB, OEA, MODE 40 40IIH elK and SERIN Vee = 5.5 V, VI = 2.7 V 20 20Al-AS, Bl-BSt 70 70OEB, OEA, MODE -1 -1III elK and SERIN Vee = 5.5 V, VI = 0.4 V -0.5 -0.5Al-AS, Bl-BSt -0.5 -0.510§Except OS -30 -112 -30 -112Vee = 5.5 V, Va = 2.25 VQ8 -20 -112 -20 -112lee Vee = 5.5 V 118 200 118 200t All typical values are at Vee = 5 V, T A = 25 De.+For 1/0 ports, the parameters IIH and III include the output currents 10ZH and 10Zl, respectively.§The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.switching characteristics (see Note 1)PARAMETERVcc = 4.5 V to 5.5 V,Cl - '" 50 pF,Rl - 500 {},FROM TO R2 - 500 {},(INPUT) (OUTPUT) TA - MIN to MAXSN54AS856SN74AS856MIN MAX MIN MAXf max 45 50 MHztplH 2 8 2 7Any B portAny A porttpHl 2 10.5 29.5tPlHAny A or B 2 8.5 2 7.5tMODE'tpHl port 5 20 5 19tplH Any A or B 2 8.5 2 7.5tPHl~MODEport 2 9.5 2 8tplH Any A or B 3 12 3 9elKtpHl port 3 12 3 11tplH 2 9 2 7.5elK OS nstpHl 2 10 2 9tpHZ 2 9 2 7tPlZAny A or B 2 12 29.5OEA or OEBtpZH port 2 8 2 7tpZl 2 11 2 10~The positive transition of the MODE control will cause low-level data at the A output Bus or stored in Q to be invalid for 12 ns.NOTE 1: load circuit and voltage waveforms are shown in Section 1.UNITVVVmAp.AmAmAmAUNITnsnsnsnsnsns•t/)C1)CJ'S;C1)cen-ITEXAS -1!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-211

IIIrencCD

SN54AS867, SN54AS869, SN74AS867, SN74AS869SYNCHRONOUS 8-BIT UP/DOWN COUNTERS02661, DECEMBER 1982-AUGUST 1985• Included among the Package Options areCompact. 24-Pin. 300-mil-Wide DIPs and2B-Pin Ceramic Chip CarriersooooFully Programmable with SynchronousCounting and Loading• ASB67 Has Asynchronous Clear •• ASB69Has Synchronous ClearFully Independent Clock Circuit SimplifiesUseRipple Carry Output for n-Bit Cascading• Improved Performance Compared toSchottky TTL:Typical Power Reduced by 3B%- Maximum Count Frequency is 25%HigherodescriptionDependable Texas Instruments Quality andReliabilitySN54AS867, SN54AS869 .... JT PACKAGESN74AS867, SN74AS869 .... DW OR NT PACKAGEsoS1ABCDEFGHENTGND(TOP VIEW)VCCENPQAQBQCQDQEQFQGQHClKRCOSN54AS867, SN54AS869 .... FK PACKAGEBC 6D 7NC 8E 9F 10G 11(TOP VIEW)~ 0 U ~I~ Q)cen..JPRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms, of Texas Instruments~~~~~:~~i~a{~~1~1~ ~!~~~~ti~r :I~o::~:~:t:r~~s notTEXAS .Jt!}INSTRUMENTSPOST OFFICE BOX 225012 • OALLAS. TEXAS 75265Copyright © 1983, Texas Instruments Incorporated2-213

SN54AS867, SN54AS869, SN74AS867, SN74AS869SYNCHRONOUS 8·BIT UP/DOWN COUNTERSThese counters feature a fully independent clock circuit. With the exception of the asynchronous clearon the' AS867, changes at control inputs (SO, S 1) that will modify the operating mode have no effecton the Q outputs until clocking occurs. Anytime the ENP and/or ENT is taken high, ReO will either goor remain high. The function of the counter (whether enabled, disabled, loading, or counting) will be dictatedsolely by the conditions meeting the stable setup and hold times.The SN54AS867 and SN54AS869 are characterized for operation over the full military temperature rangeof - 55 DC to 125 DC. The SN74AS867 and SN74AS869 are characterized for operation from oDe to 70 D e.logic symbols t'AS867'AS869lEIrOOCCD

SN54AS867, SN54AS869, SN74AS867, SN74AS869SYNCHRONOUS 8·BIT UP/DOWN COUNTERSlogic diagram (positive logic)A (3)B (4)c (5)(6)0ElltJ)Q)(.)"S;Q)cen...J(7)E----------------~--~~~~(8)F---------------+------~(9)G---------------+~----~(10)H--~~HPin numbers shown are for DW, JT, and NT packages. '--------------....TEXAS "'!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS; TEXAS 752652-215

SN54AS867, SN74AS867SYNCHRONOUS 8-BIT UP/DOWN COUNTERS WITH ASYNCHRONOUS CLEARrecommended operating conditionsrencCD

SN54AS869, SN74AS869SYNCHRONOUS 8-BIT UP/DOWN COUNTERS WITH SYNCHRONOUS CLEARrecommended operating conditionsSN54AS869SN74AS869MIN NOM MAX MIN NOM MAXVee Supply voltage 4.5 5 5.5 4.5 5 5.5 VVIH High-level input voltage 2 2 VVIL Low-level input voltage 0.8 0.8 V10H High··level output current -2 -2 mA10L Low-level output current 20 20 mAfclock Clock frequency 0 40 0 45 MHztw(clock) Duration 12.5 11 nsData inputs A-H 6 5 nsEnable P (ENP) orEnable T (ENT)10 9tsu Setup time t SO or 51 (load) 13 11 nsSO or 51 (clear) 13 11 nsSO or 51 (count down) 52 50 nsSO or 51 (count up) 52 50 nsth Hold time at any input with respect to clock i 0 0 nsTA Operating free-air temperature -55 125 0 70 °etThis setup time is required to ensure stable data.electrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)PARAMETERTEST CONDITIONSSN54AS869 SN74AS869MIN Typt MAX MIN Typt MAXVIK Vee = 4.5 V, . 11= 18 mA -1.2 -1.2 VVOH Vee = 4.5 V to 5.5 V, 10H = -2 mA vee - 2 Vee- 2 VVOL Vee = 4.5 V, 10L = 20 mA 0.34 0.5 0.34 0.5 VII Vee = 5.5 V, VI = 7 V 0.1 0.1 mAENT 40 40IIH Vee = 5.5 V, VI = 2.7 V p.AOther inputs 20 20ENT -4 -4IlL Vee = 5.5 V, VI = 0.4 V mAOther inputs -2 -2lo§ Vee = 5.5 V, Va = 2.25 V - 30 -112 -30 -112 mAICC Vee = 5.5 V 125 180 125 180 mAUNITnsUNITIIC/)Q)(,)'S;Q)cen-It All typical values are at Vee = 5 V, T A = 25°e.§The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-217

SN54AS867, SN54AS869, SN74AS867, SN74AS869SYNCHRONOUS 8·BIT UP/DOWN COUNTERS'AS867 switching characteristics (see note 1)PARAMETERf maxtplHtpHltplHtpHltplHtpHltplHtpHltpHlFROM(INPUTClKClKENTENPClear(50.51 low)TOOUTPUTRCaAny QRCaReOI · AS869 switching characteristics (see note 1)rtJ>CCDc:::n'CDenPARAMETERf maxtplHtpHltplHtpHltPlHtpHltplHtpHlFROM(INPUT)ClKClKENTENPAny QTO(OUTPUT)RC5Any QReORCaNOTE 1: load circuit and voltage waveforms. are shown in Section 1.Vcc - 4.5 V to 5.5 V.CL - 50 pF.RL - 500 n.TA - MIN to MAXSN54AS867 SN74AS867MIN MAX MIN MAX40 505 31 5 226 19 6 163 12 3 114 16 4 153 19 3 105 21 5 175 14 5 145 21 5 177 23 7 21VCC - 4.5 V to 5.5 V.CL - 50 pF.RL - 500 flTA = MIN to MAXSN54AS869 SN74AS869MIN MAX MIN MAX40 45'6 35 6 356 20 6 183 12 3 114 16 4 153 25 3 156 21 6 175' 27 5 196 21 6 18UNITMHznsnsnsnsnsUNITMHznsnsnsns2·218 TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54AS870, SN54AS871, SN74AS870, SN74AS871DUAL 16·8Y·4 REGISTER FILESD2661, DECEMBER 1982-REVISED JANUARY 1986• • AS870 in 24·Pin Small Outline. 300-mil DIPand Both Plastic and Ceramic 28-Pin ChipCarriers• • AS871 in 28-Pin 600-mil DIP and BothPlastic and Ceramic Chip Carriers• 3-State Buffer-Type Outputs Drive Bus LinesDirectly• Typical Access Time is 11 ns• Each Register File Has Individual WriteEnable Controls and Address Lines• Designed Specifically for MultibusArchitecture and Overlapping File Operations• Prioritized B Input Port Prevents WriteConflicts During Dual Input Mode• Dependable Texas Instruments Quality andReliabilitydescriptionThese devices feature two 16-word by 4-bitregister files. Each register file has individualwrite-enable controls and address lines. The• AS870 has two 4-bit data I/O ports(OQA1-00A4 and 00B1-00B4). The 'AS871has one 4-bit data I/O port (OOB 1-00B41 withthe other data port having individual data inputs(OA 1-0A41 and data outputs (OA 1-0A41. Thedata I/O ports can output to Bus A and Bus B;receive input from Bus A and Bus B, receive inputfrom Bus A and output to Bus B, or output toBus A and receive input from Bus B. To preventwriting conflicts in the dual-input mode, the Binput port takes priority. Two select lines, SO andS 1, control which port has access to whichregister. S2 determines whether the A ports arein the input or the output modes and S3 doeslikewise for the B ports. The address lines(1 AO-1 A3 or 2AO-2A31 are decoded by aninternal 1-of-16 decoder to select which registerword is to be accessed. All outputs are 3-statebuffer-type outputs designed specifically to drivebus lines directly.The SN54AS870 and SN54AS871 arecharacterized for operation over the full militarytemperature range of - 55°C to 125°C. TheSN74AS870 and SN74AS871 are characterizedfor operation from OOC to 70°C.SN54AS870 ... JT PACKAGESN74AS870 ... OW OR NT PACKAGE(TOP VIEW)50 Vee512A3lA32Al2AO2WDOAl 53DOA2D084DOA3D083DOA4D082GNDD081SN54AS871 ... JO PACKAGESN74AS871 ... N PACKAGE(TOP VIEW)DAl 28 VecDA2 27 DA450 26 DA3lAO 4 25 51lAl 24 2A3lA2 .23 2A2lA3 22 2Al'-W 21 2AO52 20 2WOAl 10 19 53OA2 11 18 D084OA3 12 17 D0830A4 13 16 D082GND 14 15 D081SN54AS870 ... FK PACKAGESN74AS870 ... FN PACKAGE(TOP VIEW).- a u cry~~OU u~~...- ..... tnZ>CJ')NlA2lA3lW 7DOAl 104 3 2 1 28 27 2612 13 14 15 1617 18SN54AS871 ... FK PACKAGESN74AS871 ... FN PACKAGE(TOP VIEW)ON,.... uo::t M~o~~ U~~~VlOO>OO432128272612 1314 15 1617 18512A32A22Al2AO2WS3•(/)Q)(.)oSQ)cen...INC - No intern al connectionPRODUCTION DATA documents contain inlormationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments. ~~~~~:~~i~a{~:1~18 ~!~~~~ti~r :llo::~:~:t:~~s not, TEXAS"INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1982, Texas Instruments Incorporated2-219

SN54AS870, SN54AS871, SN74AS870, SN74AS871DUAL 16·BV·4 REGISTER FILESlogic symbols t'AS870'AS871[REG FILE 16X41lAO (4)lAl (5)lA2 (6)lA3 17l2AO (21)2Al (22)2A2 (23)2A3 (24)SO (3)Sl (25)[REG FILE 16 X 41S2 (9)MUXRAM16Xl[REG 11DaB 1RAM16Xl[REG11DOBIrrncCD

SN54AS87U, SN54AS871, SN74AS870, SN74AS871DUAL 16·BV·4 REGISTER FILESlogic diagram (positive logic)1AO1A11A21A3soS1S2S3.:>l.)t T::::- T I-Dt>-I~~ 1-1-DECODER~1234~fs~16DECODER"""'iiNiY10 215 34-2AO2A12A22A31iN.---DA1rASS71 )DQA1rASS70)IIII---+IIIQA1 --'-rASS71)r.~ aJ~~~FLJ1616~Afsr-~~l (---E116REG2r"fi'A'M"i6.iAfs-r-rP~il~~116rJ>rTHREE IDENTICAL CHANNELS NOT SHOWN--~ DQB1EllU)Q)(J'SQ)cen..JTEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652·221

SN54AS870, SN54AS871, SN74AS870, SN74AS871DUAL 16·BV·4 REGISTER FILESIrtJ)CCD

SN54AS870, SN54AS871, SN74AS870, SN74AS871DUAL 16-8Y-4 REGISTER FILES'AS870 electrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)PARAMETERTEST CONDITIONSSN54AS870SN74AS870MIN Typt MAX MIN Typt MAXVIK Vee = 4.5 V. II = -18 mA - 1.2 -1.2 VVee = 4.5 V to 5.5 V 10H = -2 mA vee' 2 Vee 2VOH Vee = 4.5 V. 10H = -12 mA 2.4 3.2 VValIIVee = 4.5 V. 10H = -15 mA 2.4 3.2Vee = 4.5 V. 10l = 32 mA 0.25 0.5Vee = 4.5 V. 10l = 48 mA 0.35 0.5Control inputs Vee = 5.5 V. VI = 7V 0.1 0.1DOA and DaB ports Vee = 5.5 V. VI = 5.5 V 0.2 0.21W and 2W 20 20IIH Other control inputs Vee = 5.5 V. VI = 2.7 V 40 40 p.ADOA and DaB ports + 50 50IIIControl inputs -·2 -2Vee = 5.5 V. VI = 0.4 V mADOA and DaB ports1'-2 -2lo§ Vee = 5.5 V. Va = 2.25 V -30 -·112 - 30 -112 mAICC Vee = 5.5 V 120 190 120 190 mA'AS871 electrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)PARAMETERTEST CONDITIONSSN54AS871SN74AS871MIN Typt MAX MIN Typt MAXVIK VCC = 4.5 V. II = -18 mA -1.2 -1.2 VVec = 4.5 V to 5.5 V. 10H = -2 mA vee 2 Vee 2VOH Vee = 4.5 V. 10H = -12 mA 2.4 3.2 VValVee = 4.5 V. 10H = -15 mA 2.4 3.2Vec = 4.5 V. 10l = 32 mA 0.25 0.5Vee = 4.5 V. 10l = 48 mA 0.35 0.510ZH OA outputs Vee = 5.5 V. Va = 2.7 V 50 50 p.A10Zl OA outputs Vee.= 5.5 V. Va = 0.4 V - 50 - 50 p.AControl and DA inputs Vce - 5.5 V. VI = 7V 0.1 0.1IImADaB ports Vec - 5.5 V. VI = 5.5 V 0.2 0.21W. 2W. and DA inputs 20 20IIH Other control inputs Vce = 5.5 V. VI = 2.7 V 40 40 p.ADaB ports1' 50 50Control and DA inputs -2 -2III Vee 5.5 V. VI = 0.4 V mADaB ports1' -2 -2lo§ Vee ., 5.5 V. Va = 2.25 V -30 -112 -30 -112 mAICC Vce ," 5.5 V 120 190 120 190 mAUNITVmAUNITVEll(f)Q)o0:;cQ)en-It All typical values are at Vee = 5 V. T A = 25°C.1'For I/O ports, the parameters IIH and III include the off-state output current.§The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit current, lOS.TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-223

SN54AS870, SN54AS871, SN74AS870, SN74AS871DUAL 16·BY·4 REGISTER FILES, AS870 switching characteristics (see Note 1)PARAMETERFROM(INPUT!TO(OUTPUT)talA) Any A Any OQt a(5)tdisten50 Any OQA51 Any OQS52 Any OQA53 Any OQS52 Any OQA53 Any OQSWAny OQtpd OQA OQSOQSOQAVce - 4.5 V to 5.5 V.CL - 50 pF.R1 - 500 fl.R2 - 500 fl.UNITTA - MIN to MAXSN54AS870SN74AS870MIN MAX MINMAX5 20 515 ns3 15 3133 15 313ns3 12 3113 12 311ns3 15 3123 15 312ns5 23 5195 25 522 ns5 25 522lI'AS871 switching characteristics (see Note 11~CJ)CCD

SN54AS877, SN74AS8778-BIT UNIVERSAL TRANSCEIVER PORT CONTROLLERS• Included Among the Package Options areCompact, 24-Pin, 300-mil-Wide Dips andBoth 28-Pin Plastic and Ceramic ChipCarriers• Buffered 3-State Outputs Drive Bus LinesDirectly• Cascaded to n-Bits• Eight Selectable Transceiver/Port Functions:A to B or B to ARegister to A or Register to BShifted to A or Shifted to BOff-Line Shifts (A and B Ports in HighImpedance State)Registet ClearGParticularly Suitable for Use in SignatureAnalysis Circuitry• Serial Register Provides:Parallel Storage of Either A or B InputDataSerial Transmission of Data from Either Aor B PortoDependable Texas Instruments Quality andReliability02661. DECEMBER 1982-REVISED AUGUST 1985SN54AS877 ... JT PACKAGESN74AS877 ... DW OR NT PACKAGE,(TOP VIEW)SOVCCS1ClKS2SERINA1B1A2B2A3B3A4B4A5B5A6B6A7B7A8B8GND 08NC 8 22 NCdescriptionA4 9 21 B4The' AS877 features two 8-bit I/O ports (A 1-ASA5 1020 B5and B1-BS), an S-bit parallel-load, serial-in,A6 1119 B6parallel-out shift register, and control logic. With12 13 14 15 1617 18these features, this device is capable ofperforming eight selectable transceiver or portfunctions, depending on the state of the threeNC - No internal connectionselect lines SO, S 1, and S2. These functionsinclude: transferring data from port A to port Bor vice versa (i.e., the transceiver function),transferring data from the register to either port,serial shifting data to either port, performing off-line shifts (with A and B ports in high-impedance state),and clearing the register. Synchronous parallel loading of the internal register can be accomplished fromeither port on the positive transition of the clock while serially shifting data in via the SERIN input. The'AS877 is ideally suited for applications needing signature-analysis circuitry to enhance system verificationand/or fault analysis. All serial data is shifted right. All outputs are buffer-type outputs designed specificallyto drive bus lines directly and all are 3-state except for OS, which is a totem-pole output.The SN54ASS77 is characterized for operation over the full military temperature range of - 55°C to 125°C.The SN74ASS77 is characterized for operation from a °C to 70 DC.A1A2A3SN54AS877 .... FK PACKAGESN74AS877 .... FN PACKAGE(TOP VIEW)zU~ a:N~ aU U.J UJen en enz >U en4 3 2 1 2827 265 25 B16 24 B27 23 B3Ellt/)Q)(.)oS;cQ)en-JPRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments~~~~~:~~i~a{::I~~e ~!:~~~ti~r :llo::~:~:t:r~~S notTEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1982. Texas Instruments Incorporated2-225

SN54AS877, SN74AS8778-BIT UNIVERSAL TRANSCEIVER PORT CONTROLLERSIHrC/)MODES2 S1 SOCLOCK SERIN A1 01 B1FUNCTION TABLEA2 02 B2 A3 03 B3 A4 04 B4 A5 05 B5 A6 06 B6 A7 07 B7 A8 08 B8L L L H or L X Z On A1 Z On A2 Z On A3 Z On A4 Z On A5 Z On A6 Z On A7 Z On A8L L L f X Z A1 A1 Z A2 A2 Z A3 A3 Z A4 A4 Z A5 A5 Z A6 A6 Z A7 A7 Z A8 A8L L H H or L X B1 On Z B2 On Z B3 On Z B4 On Z B5 On Z B6 On Z B7 On Z B8 On ZL L H f X B1 B1 Z B2 B2 Z B3 B3 Z B4 B4 Z B5 B5 Z B6 B6 Z B7 B7 Z B8 B8 ZL H L H or L X X On 01 X On 02 X On 03 X On 04 X On 05 X On 06 X On 07 X On 08L H L f X Z A1 A1 Z A2 A2 Z A3 A3 Z A4 A4 Z A5 A5 Z A6 A6 Z A7 A7 Z A8 A8L H H H or L X 01 On X 02 On X 03 On X 04 On X 05 On X 06 On X 07 On X 08 On XL H H f X B1 B1 Z B2 B2 Z B3 B3 Z B4 B4 Z B5 B5 Z B6 B6 Z B7 B7 Z B8 B8 ZPORTFUNCTIONA TO BB TO AON TO BNON TO ANH L L H or L X Z On 01 Z On 02 Z On 03 Z On 04 Z On 05 Z On 06 Z On 07 Z On 08 SHIFTH L L f H Z H H Z 0101 Z 0202 Z 03 03 Z 04 04 Z 05 05 Z 06 06 Z 07 Q7 TOH L L f L Z L L Z 0101 Z 0202 Z 03 03 Z 04 04 Z 05 05 Z 06 06 Z 07 07 BH L H H or L X 01 On Z 02 On Z 03 On Z 04 On Z 05 On Z 06 On Z 07 On Z 08 On Z SHIFTH L H f H H H Z 0101 Z 0202 Z 0303 Z 0404 Z 0505 Z 0606 Z 0707 Z TOH L H f L L L Z 0101 Z 0202 Z 0303 Z 0404 Z 0505 Z 0606 Z 0707 Z AH H L H or L X Z On Z Z On Z Z On Z Z On Z Z On Z Z On Z Z On Z Z On ZH L f H Z H Z Z 01 Z Z 02 Z Z 03 Z Z 04 Z Z 05 Z Z 06 Z Z 07 Z SHIFTH H L f L Z L Z Z 01 Z Z 02 Z Z 03 Z Z 04 Z Z 05 Z Z 06 Z Z 07 ZH H H H or L X Z On Z Z On Z Z On Z Z On Z Z On Z Z On Z Z On Z Z On ZH H H f X Z L Z Z L Z Z L Z Z L Z Z L Z Z L Z Z L Z Z L Zn = level of 0n(n = 1.2 ... 81 established on most recent f transition of CLK. 01 thru 08 are the shift register outputs; only 08 is availableexternally. The double inversions that take place as data travels from port to port are ignored in this table.c(1) logic symbol t

SN54AS877, SN74AS8778·BIT UNIVERSAL TRANSCEIVER PORT CONTROllERSlogic diagram (positive logic)EllFOUR IDENTICAL CHANNELS NOT SHOWNINPUTS/OUTPUTS NOT SHOWN:(6) A3 (19) 83(7) A4 (la) 84(a) A5 (17) 85(9) A6 (16) 86Pin numbers shown are for OW, JT, and NT packages.(13)~------------------~~-----------------aaTEXAS ".!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-227

SN54AS877, SN74AS8778-BIT UNIVERSAL TRANSCEIVER PORT CONTROLLERSabsolute maximum ratings over free-air temperature rangeSupply voltage, Vee ......................................................... 7 VInput voltage: All inputs ................. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VI/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VVoltage applied to a disabled 3-state output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VOperating free-air temperature range: SN54AS877 ....................... - 55 °e to 125°eSN74AS877 ........................... oDe to 70 0 eStorage temperature range ......................................... - 65 °e to 150 0 erecommended operating conditionsIIIrenc(1)< (i0(I)CJ)SN54AS877SN74AS877MIN NOM MAX MIN NOM MAXVCC Supply voltage 4.5 5 5.5 4.5 5 5.5 VVIH High-level input voltage 2 2 VVil low-level input voltage O.S 0.8 VAl-A8.81-8S -12 -15IOH High-level output current mA08 -2 -2Al-A8.81-8S 32 48IOl low-level output current mA08 20 20fclock Clock frequency 0 45 0 50 MHztw Duration of clock pulse 11 10 nsAl-AS.81-8Stsu Setup time before ClK t SERIN5.5 5.5ns50.51.52 5.5 5.5Al-A8,81-8Sth Hold time, data after ClKt 5ERIN0 0ns50,51,52 0 0TA Operating free-air temperature -55 125 0 70 DCUNIT2-228 TEXAS.INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54AS877, SN74AS8778·BIT UNIVERSAL TRANSCEIVER PORT CONTROLLERSelectrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)PARAMETERTEST CONDITIONSSN54AS877 SN74AS877MIN Typt MAX MIN Typt MAXVIK Vee = 4.5 V. II = -18 mA -1.2 -1.2 VAl-A8 Vee = 4.5 V. 10H = -12 mA 2 3.2VOH Bl-B8 Vee = 4.5 V. 10H = -15 mA 2 3.3 VAll outputs Vee = 4.5 V to 5.5 V. 10H = -2 mA Vee- 2 Vee- 2VOLAll outputs except 08Vee = 4.5 V. 10l = 32 mA 0.25 0.5Vee = 4.5 V. 10l = 48 mA 0.35 0.5 V08 Vee = 4.5 V. 10l'i 20 mA 0.25 0.5 0.25 0.5SO.Sl.S2 0.3 0.3Vee = 5.5 V. VI =7VII elK and SERIN 0.1 0.1 mAAl-A8. Bl-B8 Vee = 5.5 V. VI = 5.5 V 0.2 0.2SO. Sl. S2 60 60IIH elK and SERIN Vee = 5.5 V. VI = 2.7 V 20 20 flAAl-AS. Bl-B8 t 70 70SO. Sl. S2 -1 -1III elK and SERIN Vee = 5.5 V. VI = 0.4 V -0.5 -0.5 mAAl-AS. Bl-BSt -0.75 -0.75Except OS -30 -112 -30 -112lo§ Vee = 5.5 V. Vo = 2.25 V mAOS -20 -112 -20 -112ICC Vee = 5.5 V 136 220 136 220 mAt All typical values are at Vee = 5 V. TA = 25 ae.tFor 110 ports. the parameters IIH and III include the output currents 10ZH and IOZl. respectively.§The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current. lOS·switching characteristics (see Note 1)FROMTOVcc ~ 4.5 V to 5.5 V.CL - 50 pF.R1 = 500 n.PARAMETER R2 = 500 n. UNIT(INPUT)(OUTPUT)TA = MIN to MAXSN54AS877SN74AS877MIN MAX MIN MAXf max 45 50 MHztplH 2 8.5 2 7Any A portAny B porttpHl3 10.5 3 9tplH 2 9 2 7.5Any B portAny A porttpHl3 10.5 3 9tplHtpHlSO. Sl. S2'Any A or B 3 11.5 3 10port2 9.5 2 StPlH Any A or B 2 11 2 9elKtpHl port 3 13 3 11.5tplH 2 10.5 2 SelK OB nstpHl 3 10 3 8.5tpHZ 2 7.5 2 6.5tplZAny A or B 3 13 3 10.5SO. Sl. S2tpZH port 2 9 2 7tpZl 3 11.5 3 9.5NOTE 1: load circuit and voltage waveforms are shown in Section 1.'The positive transition of 52 will cause low-level data at the A output Bus or stored in the shift register to be invalid for 12 ns.UNITnsnsnsnsnsnsEllenQ)(.)oS;cQ)en..JTEXAS -1!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-229

SN54AS877, SN74AS8778·BIT UNIVERSAL TRANSCEIVER PORT CONTROLLERSTYPICAL APPLICATION OAT ABUS A TO BUS B ORSERIAL TRANSMISSIONSERIAL IN -----....,ClK --.-----.BUS B TO BUS A ORSERIAL TRANSMISSIONSERIAL IN _____.....,ClK-...... -~I REGIAIIIII IBIIIIIBII.1IIIBIII REG II IAI 1 8I II ISERIALOUTSERIALOUTSERIAL IN TO A PORTSERIAL IN _____....,ClK-----,SERIAL IN TO 8 PORTSERIAlIN _____ --.ClK------,III BIIHi·ZHi·ZII1 8IISERIALOUTSERIALOUT2-230 TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54AS882A, SN74AS882A32·81T LOOK·AHEAD CARRY GENERATORS• Directly Compatible with 'AS181B,'AS1181, 'AS881B, and 'AS1881 ALUs• Included among the Package Options areCompact, 24-Pin, 300-mil-Wide DIPs andBoth 28-Pin Plastic and Ceramic ChipCarriers• Capable of Anticipating the Carry Across aGroup of Eight 4-Bit Binary Adders• Cascadable to Perform Look-Ahead Acrossn"Bit Adders• Typical Carry Time, Cn to Any Cn + i, isLess Than 6 ns• Dependable Texas Instruments Quality andReliabilitydescriptionCn +8Cn +16Cn +24Cn +32The' AS882A is a high-speed look-ahead carrygenerator" capable of anticipating the carry~cross a group of eight 4-bit adders permittingthe designer to implement look-ahead for a32-bit ALU with a single package or, bycascading 'AS882A's, full look-ahead is possibleacross n-bit adders.The SN54AS882A is characterized for operationover the full military temperature range of- 55 DC to 125 DC. The SN74AS882A ischaracterized for operation from 0 DC to 70 DC.'AS882A LOGIC EQUATIONSG1 +P1GO+P1POCnG3+P3G2+P3P2G1+P3P2P1GO+ P3P2P1 POC nG5 + P5G4 + P5P4G3 + P5P4P3G2+P5P4P3P2G1+P5P4P3P2P1GO+ P5P4P3P2P1 POC nG7+P7G6+P7P6G5+P7P6P5G4+ P7P6P5P4G3 + P7P6P5P4P3G2+ P7P6P5P4P3P2G1 + P7P6P5P4P3P2P1 GO+P7P6P5P4P3P2P1POC n02661, DECEMBER 1982 - REVISED NOVEMBER 1985SN54AS882A ... JT,PACKAGESN74AS882A ... ow OR NT PACKAGE(TOP VIEW)C nVCCGONCPO Cn +32

SN54AS882A, SN74AS882A32·BIT LOOK·AHEAD CARRY GENERATORSlogic symbol tCPG"";';';---f C1C01(6) Cn+8C03(11)Cn+16C05(17) Cn+24C07(22)Cn+32IIIr-OO tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.Pin numbers shown are for DW. JT. and NT packages.cCD

SN54AS882A, SN74AS882A32·81T LOOK·AHEAD CARRY GENERATORSFUNCTION TABLEFOR Cn + 32 OUTPUTG7LXXXXXXXXG6 65X XL XX LX XX XX XX XX XX X64 63 62 G1X X X XX X X XX X X XL X X XX L X XX X L XX X X LX X X XX X X XINPUTS60XXXXXXXLX))7XLLLLLLLLPGXXLLLLLLLP5XXXLLLLLLP4XXXXLLLLLAll other combinationsP3XXXX.XLLLLOUTPUTP2 P1 ]So Cn Cn +32X X X X HX X X X HX X X X HX X X X HX X X X HX X X X HL X X X HL L X X HL L L H HLFUNCTION TABLEFOR Cn + 24 OUTPUTG5LXXXXXXG4XLXXXXXG3 G2 G1X X XX X XL X XX L XX X LX X XX X XFUNCTION TABLEFOR Cn + 16 OUTPUTINPUTSOUTPUTGO P5 P4 P3 P2 P1 PO Cn Cn +24X X X X X X X X HX L X X X X X X HX L L X X X X X HX L L L X X X X HX L L L L X X X HL L L L L L X X HX L L L L L L H HAll other combinationsLFUNCTION TABLEFOR Cn + B OUTPUTU)Q)CJ"SQ)c(/)..oJG3 G2L XX LX XX XX XINPUTSP3 P2 P1 PO CnX X X X XL X X X XL L X X XL L L X XG1 GOX XX XL XX LX X L L L L HAll other combinationsOUTPUTCn +16 61 GOINPUTSP1 PO CnHL X X X XHX L L X XHX X L L HHAll other combinationsHLOUTPUTCn+BHHHLAny inputs not shown in a given table are irrelevant with respect to that output.TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-233

~SN54AS882A, SN74AS882A32·81T LOOK·AHEAD CARRY GENERATORSlogic diagram (positive logic)157(21)=:f)-P6P4(19)(16)(14)a~P3Pl(10)(8)(5)'== F?:::::t)-(22)Cn + 32~ }--PO(3)~)-rt/)CCD

SN54AS882A, SN74AS882A32-BIT LOOK·AHEAD CARRY GENERATORSabsolute maximum ratings over operating free·air temperature range (unless otherwise noted)Supply voltage, Vee ..... ' .................................................... 7 VInput voltage ......................................... -..................... 7- VOperating free-air temperature range: SN54AS882A . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°CSN74AS822A .......................... ooe to 70°CStorage temperature range ......................................... - 65°C to 150 °erecommended operating conditionsSN54AS882ASN74AS882AMIN NOM MAX MIN NOM MAXVee Supply voltage 4.5 5 5.5 4.5 5 5.5 VVIH High-level input voltage 2 2 VVIL Low·level input voltage 0.8 0.8 VIOH High·level output current -2 -2 mAIOL Low-level output current 20 20 mATA Operating free·air temperature - 55 125 0 70 °eUNIT(/)Q)CJoS;cQ)en-ITEXAS ~INSTRUMENlSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-235

SN54AS882A, SN74AS882A32·81T LOOK·AHEAD CARRY GENERATORSIIIrenc(I)

SN54AS882A, SN74AS882A32·BIT LOOK·AHEAD CARRY GENERATORSswitching characteristics (see Note 1)PARAMETERtpLHtpHLtpLHtpHLtpLHtpHLtpLHtpHLFROM(INPUT)C n15 orGTO(OUTPUT)Any outputCn +815 orG Cn +1615 or GCn +24tPLH 15 or G Cn +32tpHLNOTE 1: Load circuits and voltage waveforms are shown in Section 1.Vcc - 4.5 V to 5.5 V.CL - 50 pF.RL - 500 n.TA - MIN to MAXSN54AS822ASN74AS882AMIN MAX MIN MAX2 10 2 93 15 3 142 8 2 72 8 2 72 8 2 72 8 272 8 2 72 11 2 101.5 9 2 82 13 2 12UNITnstnQ)(,)0>Q)cen...JTEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-237

~SN54AS882A, SN74AS882A32·81T LOOK·AHEAD CARRY GENERATORSTYPICAL APPLICATION DATAThe application given in Figure 1 illustrates how the' AS882A can implement look-ahead carry for a 32-bitALU (in this case, the popular' AS881 A) with a single package. Typical carry times shown are derivedusing the standard Advanced Schottky load circuit.PO GO PI Gl Cn+BFIGURE 1Likewise, Figure 2 illustrates the same 32-bit ALU using two' AS882s. This shows the worst-case delayfrom LSB to MSB to be 19 ns as opposed to 25 ns in Figure 1.MS8'AS881A;.~'AS881A'AS881A!}~'AS8.81A'AS881A-::~'ASB81A'), -:',~.. Cn6 nsL-r-t--.,......,..J 1':/1 ~r- ~~ 11 ~~'-PO:i GO PI Gl Cn +8 P2 G2F!F~ Cn6 ns! WFF-L..-.,-""""",,,[:;J I~ Cn6 ns'-r-I"!""T'r't.:Dt ,~~ ~~~~I I ~~ s1': G3 Cn + 16 P4 G4 P5 G5 Cn +24 P6 G6 : P7 G7.... -----lC n 'AS882A:~ C n +32 f-+1 IPO GO PI Gl Cn +8P2 G2 'AS882A P3 G3 Cn+ 16 ~::;:P4S'2G4CJl~~6~nS)';:::"'::::'P~) G5 Cn+24P6 G6P7 G7Cn +32FIGURE 22-238TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54AS885, SN74AS8858·BIT MAGNITUDE COMPARATORS02661, DECEMBER 1982-REVISED MARCH 1985• Included among the Package Options AreCompact, 24-Pin, 300-mil DIPs and Both28-Pin Ceramic and Plastic Chip Carriers• Latchable P Input Ports with Power-UpClearo Choice of Logical or Arithmetic(2's Complement) Comparison• Data and PLE Inputs Utilize P-N-P InputTransistors to Reduce DC Loading Effects• Approximately 35% Improvement in ACPerformance Over Schottky TTL whilePerforming More Functions• Cas cad able . to n-Bits while Maintaining HighPerformanceo 10% Less Power than STTL for an 8-BitComparisonoDependable Texas Instruments Quality andReliabilitydescriptionThese advanced Schottky devices are capableof performing high-speed arithmetic or logiccomparisons on two 8-bit binary or two'scomplement words. Two fully decoded decisionsabout words P and Q are externally available attwo outputs. These devices are fully expandableto any number of bits without external gates.The P > Q and P < Q outputs of a stagehandling less-significant bits may be connectedto the P > Q and P < Q inputs of the next stagehandling more-significant bits to obtaincomparisons of words of longer lengths. Thecascading paths are implemented with only atwo-gate-Ievel delay to reduce overallcomparison times for long words. Twoalternative methods of cascading are shown inthe typical application data.SN54AS885 .... JT PACKAGESN74AS885 .... OW OR NT PACKAGE(TOP VIEW)070605NC040302LlAVCCPOINP707 P606 P505 P404 P303 P202 P101 PO00 POOUTSN54AS885 .... FK PACKAGESN74AS885 ... ~ FNPACKAGE(TOP VIEW)zzddA V 1« U U wU.....J ,....o..o..:::Jz >0.. 0..678910114 3 2 1 2827262524232221201912 131415 1617 18.-OQUf-f-OOOzz::>::>o..t.? 0000A V0..0..The latch is transparent when P Latch Enable (PLE) is high; the P input port is latched when PLE is low.This provides the designer with temporary storage for the P data word. The enable circuitry is implementedwith minimal delay times to enhance performance when cascaded for longer words. The PLE and P andQ data inputs utilize p-n-p input transistors to reduce the low-level current input requirement to typically- 0.25 mA, which minimizes dc loading effects.The SN54AS885 is characterized for operation over the full military temperature range of - 55°C to ·125 DC.The SN 74AS885 is characterized for operation from OOC to 70°C.P6P5P4NCP3P2P1CJ)Q)(J'>cQ)en-IpRODUCTION DATAThis document contains information current asof publication date. Products conform tospecifications per the terms of Texas InstrumentsTEXAS -II}~~nnd::~s~~rl~ar~~iu~~Ot~~~~!~nor~~f~~~~n~e~~~s~ INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265Copyright © 1982, Texas Instruments Incorporated2-239

SN54AS885, SN74AS8858·BIT MAGNITUDE COMPARATORSlogic diagram (positive logic)r-encCD 0in vP< °inlOGIC~}'P7 - 07~ P6~06~PS=OS-r l.......:n P3=03}'), P2 = 02Pl = 01;,IIPO = 00~II~.~ f4MSB=}-}->-:-= =-::ti3t=t(13j(14) PGPin numbers shown are for DW. JT. and NT packages.2-240 ~EXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • OALLAS, TEXAS 75265

SN54AS885. SN74AS8858·BIT MAGNITUDE COMPA~ATORSlogic symboltCOMPPOP1P2P3P4P5P6P7P>

SN54AS885, SN74AS8858·BIT MAGNITUDE COMPARATORSrencCDc:::ri'CDenrecommended operating conditionsPARAMETERSN54AS885SN74AS885MIN NOM MAX MIN NOM MAXVee Supply voltage 4.5 5 5.5 4.5 5 5.5 VVIH High-level input voltage 2 2 VVIL Low-level input voltage 0.8 0.8 VIOH High-level output current -2 -2 mAIOL Low-level output current 20 20 mAtsu Setup time to PLE! 2 2th Hold time after PLE! 4 4TA . Operating free-air temperature - 55 125 0 70 °eelectrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)PARAMETERTEST CONDITIONSSN54AS885 SN74AS885MIN Typt MAX MIN Typt MAXVIK Vee = 4.5 V, II = -18 mA -1.2 -1.2 VVOH Vee = 4.5 to 5.5 V, 10H = -2 mA Vee- 2 Vee- 2 VVOL Vee = 4.5 V, 10L = 20 mA 0.35 0.5 0.35 0.5 VII Vee = 5.5 V, VI = 7 V 0.1 0.1 flALlA 40 40IIH Vee = 5.5 V, VI = 2.7 V flAOthers 20 20IlLLlA -4 -4P> QinP < QinVee = 5.5 V, VI = 0.4 V -2 -2 mAP, Q, PLE -1 -1lot Vee = 5.5 V, Va = 2.25 V -20 -112 -20 -112 mAlee Vee = 5.5 V See Note 1 130 210 130 210 mAt All typical values are at Vee = 5 V, T A = 25 °e.tThe output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit current, lOS .. NOTE 1: Ice is measured with all inputs high except LlA, which is low.switching characteristics (see Note 2)UNITnsUNITPARAMETERVCC = 4.5 V to 5.5 V,CL = 50 pF,FROM TO RL = 500 n,(INPUT) (OUTPUT) TA - MIN to MAXSN54AS885 SN74AS885MIN Typt MAXMIN Typt MAXtpLH 8.5 14 8.5 13LlAtpHL 7.5 14 7.5 13tpLH P < Qin P < Q, 5 10 5 8tpHLP> Qin P > Q 5.5 10 5.5 8tPLH Any P or Q 13.5 21 13 .. 5 17.5tpHLData Input 10 17 10 15UNITnsnsnst All typical values are at Vee = 5 V, TA = 25 °e.NOTE 2: Load circuit and voltage waveforms are shown in Section 1.2-242 TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54AS885, SN74AS8858·BIT MAGNITUDE COMPARATORSTYPICAL APPLICATION DATAThe' AS885 can be cascaded to compare words longer than 8-bits. Figure 1 shows the comparison of two32-bit words; however, the design is expandable to n-bits. Figure 1 shows the optimum cascading arrangementfor comparing words of 32 bits or greater. Typical delay times shown are at Vee = 5 V, T A = 25 o e, anduse the standard Advanced Schottky load of RL = 500 n, eL = 50 pF.PLEP1 1161 IIIcoP2(17)~P3 UBIP4 (19)::cpst201PGt211P7t221P>O 131H OR LPQ)Cen-JH OR LPt(16)P2(171P3(18)P4t19\P51201P61211IIIcoco(I)::cP71221p>o (3) (131P

SN54AS885, SN74AS8858-BIT MAGNITUDE COMPARATORSTYPICAL APPLICATION DATAThe method shown in Figure 2 is the fastest cascading arrangement for comparing 16-bit or 24-bit words. Typicaldelay times shown are at Vee = 5 V, T A = 25°e, and use the standard Advanced Schottky load of Rl = 500 g,el = 50 pF.LATCH __ ~ ______________________ ~~ ______________________ ,ENABLE(1)LlAIIr-enCCD~.0CDfJ)PLE (23)LSB PO PO (15)LtlPlPl (16) Ltl Ltlco co cocoP2P2 (17) co coen en enP3 ~ P3 (1S) ~ ~P4P4 (19)P5 (20) P5 (20)P6 (21) P6 (21)(22)P7P7 (22) P7 (221P>O (3) P>O (13) P>O (3) P>O(13) MSB P>O (3)P>O(13)P

SN54AS887, SN74AS8878-BIT PROCESSORS• STL-AS Technology• Parallel 8-Bit ALU with Expansion Inputsand Outputs• 13 Arithmetic and Logic Functions• 8 Conditional Shifts (Single and DoubleLength)o 4 Instructions that Manipulate Bitso Add and Subtract Immediate Instructionso Absolute Value InstructionoSigned Magnitude to/from Two'sComplement Conversion• Single- and Double-Length Normalize• Select Functionso Signed and Unsigned Divides with OverflowDetection; Input does not Need to bePrescaledo Signed, Mixed, and Unsigned MultipliesdescriptionoThree-Operand, 16-Word Register Fileo Full Carry Look Ahead SupportFEBRUARY 1986o Sign; Carry Out, Overflow, and Zero-DetectStatus Capabilitieso Excess-3 BCD Arithmetico Internal Shift Multiplexers that Eliminate theNeed for External Shift Control Parts'• ALU Bypass Path to Increase Speeds ofMultiply, Divide, and Normalize Instructionsand to Provide New Instructions such as BitSet, Bit Reset, and Bit Testo 3-0perand Register Files to Allow anOperation and a Move Instruction to beCombinedo Bit Masks that are Shared with RegisterAddress Fields to Minimize Control StoreWord Width" 3 Data Input/Output Paths to MaximizeData ThroughputEllThese 8-bit Advanced Schottky TTL integrated circuits are designed to implement high performance digitalcomputers or controllers. An architecture and instruction set has been chosen that supports a fast systemclock, a narrow micro-code word width, and a high system throughput. The powerful instruction set allowshigh-speed system architecture to be implemented and also allows an existing system's performance tobe upgraded while protecting software investments. These processors are non-cascadable versions of the'AS888. They are designed for 8-bit applications only.The SN54AS887 is characterized for operation over the full military temperature range of - 55 DC to 125 DC.The SN74AS887 and SN74AS887-1 are characterized for operation from ooe to 70°C.Package options include both plas'tic and ceramic chip carriers in addition to a 68-pin grid array ceramicpackage.PRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments~~~~~~~~i~at~:I~~~ ~!~:i~~ti~r fl\o::~;~~t:ros~s notTEXAS -Ij}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1986, Texas Instruments Incorporated2-245

SN54AS887. SN74AS8878·BIT PROCESSORSIr0-C/)ABCDEFGHJKLSN54AS887. SN74AS887 ... GB PACKAGE(TOP VIEW)2 3 4 5 6 7 8 9 10 11• • • • • • • • • •• 0· • • • • • • 0·• • • •• • • •• • • •• • • •• • • •• • • •• • • •• 0· • • • • • 0·• • • • • • • •SN54AS887 ... FK PACKAGESN74AS887 ... FN PACKAGE(TOP VIEW)"ICD CDW~CDO~NM~MN~OMN~O0OOwwCDCDCDCD ~~~~UUUU9 8 7 6 5 4 3 2 1 68 67 666564 63 62 61DB6 10 60DB5 11 59DB4 12 58DB3 13 57DB2 14 56DBl 15 5516 5417 5318 5219 5120 5021 4922 4823 4724 4625 4526 442728293031323234353637383940414243CKDA7DA6DA5DA4DA3DA2DAlDAOGNDEAOEAVCClVCC2171615C(t)

SN54AS887, SN74AS8878-BIT PROCESSORSPIN GRID CHIPARRAY CARRIERNAMEA-10 28 TESTB-7 29 SSFA-9 30 ZEROA-8 31 OVRA-7 32 NA-6 33 Cn +8I/OII/OI/O000DESCRIPTIONTest input pin. Connected to ground for normal operation.Special shift function. Used to transfer required information between packages duringspecial instruction execution.Device zero detection. open collector. Input during certain special instructions.ALU overflow. low active.ALU negative. low active.ALU ripple carry output.B-6 34 SI07A-5 35 QI07A-4 36 QIOOA-3 37 SIOOA-2 38 CnI/OI/OI/OI/OIBidirectional shift pin. low active.ALU carry input.B-4 39 10B-3 40 11B-1 41 12B-2 42 13B-5 43 14C-1 44 15D-1 45 16E-1 46 17C-2 47 VCC2D-2 '48 VCC1E-2 49 OEAF-1 50 EAF-2 51 GNDG-2 52 DAOH-2 53 DA1G-1 54 DA2H-1 55 DA3J-1 56 DA4J-2 57 DA5K-l 58 DA6K-2 59 DA7L-2 60 CKK-3 61 COL-3 62 C1K-4 63 C2L-4 64 C3K-5 65 AOL-5 66 A1L-6 67 A2K-6 68 A3IIIIIIIIIII/OI/OI/OI/OI/OI/OI/OI/OIIIIIIIIIInstruction input.Low voltage power supply (2 V).I/O interface supply voltage (5 V).DA bus enable. low active.ALU input operand select. High state selects external DA bus and low state selectsregister file.Ground pin.A port data bus. Outputs register file data (EA = 0) or inputs external data (EA = 1).Clocks all synchronous registers on positive edge.Register file write address select.Register file A port read address select.IItJ)Q)CJ'S;Q)cen..JTEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-247

SN54AS887, SN74AS8878·BIT PROCESSORSI'r(/)CCD

SN54AS887, SN74AS8878·BIT PROCESSORSfunctional block diagram4C3·COA3·AODA7·DAO4816 X 8REGISTER FILEWECKB3·BOOEBDB7·DBOOEAEAN +--OVR +--Cn +8 4-ZERO ....-Si07QI07TEST ......-SSF~17·10 ~OEYEBOEB1C nSIOO0100IIIU)Q)(,)0>Q)Cen...J----4 VCC1SELY ... ------.......Y7·YO-----. VCC2~GNDTEXAS l!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-249

SN54AS887, SN74AS8878·BIT PROCESSORSEIDB portarchitectural elements3-port register fileWorking registers consist of 128 storage elements organized into sixteen 8-bit words. These storageelements appear to the user as 16 positive edge-triggered registers. The three port addresses, one write(C) and two reads (A and B). are completely independent of each other to implement a 3-operand registerfile. Data is written into the register file when WE is low and a low-to-high clock transition occurs. TheADD and SUBTRACT immediate instructions require only one source operand. The B address is used asthe source address, and the bits of the A address are used to provide a constant field. The SET, RESET,and TEST BIT instructions use the B addressed register as both the source and destination register whilethe A and C addresses are used as masks. These instructions are explained in more detail in the instructionsection.S multiplexerThe S multiplexer selects the ALU operand, as follows:EB1 EBO S busLow Low RF dataLow High MO dataHigh Low DB dataHigh High MO dataThe 8-bit bidirectional DB port inputs external data to the ALU or outputs the register file. If OEB is low,the DB bus is active; if OEB is high, the DB bus is in the high impedance state. Notice that the DB portmay be isolated at the same time that register file data is passed to the ALU.R multiplexerDA portALUThe R multiplexer selects the other operand of the ALU. Except for those instructions that require constantsor masks, the R bus will contain DA if EA is high or the RF data pointed to by A if EA is low.T.he 8-bit bidirectional DA port inputs external data to the ALU or outputs the register file. If OEA is low,the DA bus is active; if OEA is high, the DA bus is in the high-impedance state.Notice that the DA bus may be isolated while register file data is passed to the ALU.The shift instructions are summarized in Table 4 and illustrated in Figure 2. The ALU can perform sevenarithmetic and six logical instructions on two 8-bit operands. It also supports multiplication, division,normalization, bit set, reset, test, byte operations, and excess-3 BCD arithmetic. These source operandsare the outputs of the Sand R multiplexers.ALU and MQ shiftersALU and MO shifters perform all of the shift, multiply, divide, and normalize functions. Table 4 showsthe value of the SI07 and 0107 pins of the most significant package. The standard shifts may be madeinto conditional shifts and the serial data may be input or output with the aid of two three-state gates.These capabilities are discussed further in the arithmetic and logic section.2-250 TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54AS887, SN74AS8878-BIT PROCESSORSMQ registerY busstatusThe multiplier-quotient (MQ) register has specific functions in multiplication, division, and normalization.This register may also be used as a temporary storage register. The MQ register may be loaded if theinstruction code on pins 17-10 is E1-E7 or E9-EE (See Table 1).The Y bus contains the output of the ALU shifter if OEY is low and is a high impedance input if OEY ishigh. SEL Y must be low to pass the internal ALU shift bus and must be high to pass the external Y busto the register file.Four status pins are available on the most significant package, overflow (OVR), sign (N)' carry out (Cn + 8),and zero (ZERO). The Cn + 8 line signifies the ALU result while OVR, ZERO, and N refer the status afterthe ALU shift has occurred. Notice that the ZERO pin cannot be used to detect whether an input placedon a high impedance Y bus is zero.divide BCD flip-flopsThe multiply-divide flip-flops contain the status of the previous multiply or divide instruction. They are ~affected by the following instructions: ~DIVIDE REMAINDER FIXSIGNED DIVIDE QUOTIENT FIXSIGNED MULTIPLYSIGNED MULTIPLY TERMINATESIGNED DIVIDE INITIALIZESIGNED DIVIDE STARTSIGNED DIVIDE ITERATEUNSIGNED DIVIDE STARTUNSIGNED DIVIDE ITERATEUNSIGNED MULTIPLYSIGNED DIVIDE TERMINATEUNSIGNED DIVIDE TERMINATEThe excess-3 BCD flip-flops are affected by all instructions except NOP. The clear function clears theseflip-flops. They preserve the carry from each nibble (4-bits) in excess-3/BCD operations.tJ)Q)CJos:Q)Cen..Jtest pin (test)This pin should be connected to ground.special shift function (SSF) pinConditional shifting algorithms may be implemented via control of the SSF pin. The applied voltage to thispin may be set as a function of a potential overflow condition (the two most significant bits are not equal)or any other condition (see Group 1 instructions).instruction setThe' AS887 bit-slice processor uses bits 17-10 as instruction inputs. A combination of bits 13-10 (Group 1instructions) and bits 17-14 (Group 2-5 instructions) are used to develop the 8-bit op code for a specificinstruction. Group 1 and Group 2 instructions can be combined to perform arithmetic or logical functionsplus a shift function in one instruction cycle. A summary of the instruction set is given in Table 1.TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-251

SN54AS887, SN74AS8878·BIT PROCESSORSTABLE 1. INSTRUCTION SETEIrVJCCD

SN54AS887, SN74AS8878·BIT PROCESSORSTABLE 1. INSTRUCTION SET (Continued)GROUP 3 INSTRUCTIONSINSTRUCTION BITS (17-10)HEX CODEMNEMONICFUNCTION08 SET1 Set Bit18 SETO Reset Bit28 TB1 Test Bit (One)38 TBO Test Bit (Zero)48 ABS Absolute Value58 SMTC Sign Magnitude/Two's Complement68 ADDI Add Immediate78 SUBI Subtract Immediate88 Reserved98 ReservedA8ReservedB8ReservedC8Reserved08 ReservedE8ReservedF8ReservedGROUP 4 INSTRUCTIONSINSTRUCTION BITS (l7-10)HEX CODEMNEMONICFUNCTION00 Reserved10 SEL Select SIR20 SNORM Single Length Normalize30 DNORM Double Length Normalize40 DIVRF Divide Remainder Fix50 SDIVQF Signed Divide Quotient Fix60 SMUll Signed Multiply Iterate70 SMULT Signed Multiply Terminate80 SDIVIN Signed Divide Initialize90 SDIVIS Signed Divide StartAO SDIVI Signed Divide IterateBO UDIVIS Unsigned Divide StartCO UDIVI Unsigned Divide IterateDO UMULI Unsigned Multiply IterateEO SDIVIT Signed Divide TerminateFO UDIVIT Unsigned Divide TerminateIItJ)Q)t)'SQ)c(J)...JTEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-253

SN54AS887, SN74AS8878·BIT PROCESSORS-grouprenCCD

SN54AS887, SN74AS8878·BIT PROCESSORSGroup 1 instructions (excluding hex codes 0, 8, and F), shown in Table 2, may be used in conjunctionwith Group 2 shift instructions to perform arithmetic or logical functions plus a shift function t in oneinstruction cycle (hex codes 0, 8, and F are used to access Group 4, 3, and 5 instructions, respectively).Each shift may be made into a conditional shift by forcing the special shift function (SSF) pin into the properstate. If the SSF pin is high or floating, the shifted ALU output will be sent to the output buffers. If theSSF pin is pulled low externally, the ALU result will be passed directly to the output buffers. Conditionalshifting is useful for scaling inputs in data arrays or in signal processing algorithms.These instructions set the BCD flip-flop for the excess-3 correct instruction. The status is set with thefollowing results (C n + 8 is ALU carry out and is independent of shift operation; others are evaluated aftershift operation).tDouble-precision shifts involve both the ALU and MO register.Status is set with the following results:ArithmeticNOVRCn +8ZLogicNOVRCn +8Zgroup 2 instructionsMSB of resultSigned arithmetic overflowCarry out equal oneResult equal zeroMSB of resultNone (force to zero)None (force to zero)Result equal zeroTABLE 3. GROUP 2 INSTRUCTIONSIIU)Q)CJoSQ)cen...IINSTRUCTION BITS 117-141HEX CODEMNEMONICFUNCTION0 SRA Arithmetic Right Single1 SRAD Arithmetic Right Double2 SRL Logical Right Single3 SRLD Logical Right Double4 SLA Arithmetic Left Single5 SLAD Arithmetic Left Double6 SLC Circular Left Single7 SLCD Circular Left Double8 SRC Circular Right Single9 SRCD Circular Right DoubleA MOSRA Pass (F .... y) and Arithmetic Right MOB MOSRL Pass (F .... y) and Logical Right MOC MOSLL Pass (F .... y) and Logical Left MOD MOSLC Pass (F .... y) and Circular Left MOE LOADMO Pass (F .... y) and Load MO (F = MO)F PASS Pass (F .... y)TEXAS -I!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-255

SN54AS887, SN74AS8878·BIT PROCESSORSThe processor's shift instructions are implemented using Group 2 instructions (Table 3). The connectionsare the same on all instructions including multiply, divide, and normalization functions.The following external connections are required:SI07 to SIOO0107 to 0100Single· and double-precision shifts are supported. Double-precision shifts assume the most significant halfhas come through the ALU and will be placed (if WE is low) into the register file on the rising edge ofthe clock and the least significant half lies in the MO register. All Group 2 shifts may be made conditional.(see previous page)IIrCJ)CCD

SN54AS887, SN74AS8878·81T PROCESSORSSerial input may be performed using the circuitry shown in Figure 1 . A single-lor double-precision arithmeticleft or logical right shift fills the complement of the data on SIOO and SI07 into the LSB or MSB of thedata word(s). Note that if SIOO and SI07 are floating (HI-Z), a zero will be filled as an end condition.Serial output may be performed with circular instructions.The shift instructions are summarized in Table 4 and illustrated in Figure 2. In Figure 2 and all succeedingfigures that illustrate instruction execution,' the following definitions apply:QBT End fill for signed divide.MQF End fill ·for unsigned divide.SRF End fill for signed mUltiply and the arithmetic right shifts.TABLE 4. SHIFT INSTRUCTIONSOPSI07 • SIOO 0107· 0100SHIFT FUNCTION~CODEt WIRED VALUE WIRED VALUEON Arithmetic Right Single ALU-LSB Output -IN Arithmetic Right Double MQ-LSB Output ALU-LSB Output2N Logical Right Single Input to ALU-MSB ALU-LSB Output3N Logical Right Double Input to ALU-MSB ALU-LSB Output4N Arithmetic Left Single Input to ALU-LSB ALU-MSB Output5N Arithmetic Left Double Input to MQ-LSB MQ-MSB Output6N Circular Left Single ALU-MSB Output -7N Circular Left Double ALU-MSB Output MQ-MSB Output8N Circular Right Single ALU-LSB Output -9N Circular Right Double MQ-LSB Output ALU-LSB OutputAN Arithmetic Right (MQ only) MQ-LSB Output MQ-LSB OutputBN Logical Right (MQ only) MQ-LSB Output Input to MQ-MSBCN Logical Left (MQ only) Input to MQ-LSB MQ-MSB OutputON Circular Left (MQ only) MQ-MSB Output MQ-MSB Outputtop Code N *' 0, 8, or F; these select special instruction Groups 4,3, and 5 respectively,tShift 1/0 pins are active low. Therefore, inputs and outputs must be inverted if truelogical values are required.II(/)Q)CJoSQ)cen...JStatus is set with the following results:ArithmeticNOVRCn +8ZLogicNOVRCn +8ZResult MSB equal oneSigned arithmetic overflow tCarry out equal oneResult equal zeroResult MSB equal oneZeroZeroResult equal zerot For the SLA and SLAD instructions, OVR is set if signed arithmetic overflow or if the ALU result MSB XOR MSB-l equals one.TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-257

SN54AS887. SN74AS8878·BIT PROCESSORSARITHMETIC RIGHT SINGLEIrencCD

SN54AS887, SN74AS8878·BIT PROCESSORSFILLS ZERO IF NOT FORCEDLOGICAL RIGHT SINGLEFILLS ZERO IF NOT FORCEDLOGICAL RIGHT DOUBLEEllC/)Q)(.)"SQ)cen-IFIGURE 2. SHIFT INSTRUCTIONS (Continued)TEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-259

SN54AS887, SN74AS8878·BIT PROCESSORSARITHMETIC LEFT SINGLEFILLS ZERO IF NOT FORCEDIIrrncCD

SN54AS887, SN74AS8878·BIT PROCESSORSCIRCULAR LEFT SINGLECIRCULAR LEFT DOUBLEEllCJ)Q)(.)oSQ)cen..oJFIGURE 2. SHIFT INSTRUCTIONS (Continued)TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-261

SN54AS887, SN74AS8878·BIT PROCESSORSCIRCULAR RIGHT SINGLEICIRCULAR RIGHT DOUBLEALU7 6 5 4 3 2 oao~FIGURE 2. SHIFT INSTRUCTIONS (Continued)2-262TEXAS.INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54AS887. SN74AS8878·BIT PROCESSORSARITHMETIC RIGHT (MO ONL VISERIAL DATA OUTr-.0:2LOGICAL RIGHT (MO ONL VIALU7 6 5 4 3 2 000:2enQ)()oSQ)Cen...JFILLS ZERO IF NOT FORCEDFIGURE 2. SHIFT INSTRUCTIONS (Continued)TEXAS -Ij}INSTRUMENTSPOST OFFICE BOX 225012 • OALLAS. TEXAS 752652-263

SN54AS887, SN74AS8878·BIT PROCESSORSLOGICAL LEFT (MO ONL VIFILLS ZERO IF NOT FORCEDIICIRCULAR LEFT (MO ONL VIr-- u.o a::~ enALU7 6 5 4 3 2 oo~FIGURE 2. SHIFT INSTRUCTIONS (Concluded)2-264TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54AS887, SN74AS8878·BIT PROCESSORSgroup 3 instructionsHex code 8 of Groupsummarized in Table 5.instructions is used to access Group 3 instructions. Group 3 instructions areTABLE 5. GROUP 3 INSTRUCTIONSINSTRUCTION BITS (17-10)OP CODE (HEX)MNEMONICFUNCTION08 SETl Set Bit18 SETO Reset Bit28 TBl Test Bit (One)38 TBO Test Bit (Zero)48 ABS Absolute Value58 SMTC Sign Magnitude/Two's Complement68 AOOI Add Immediate78 SUBI Subtract Immediate88 Reserved98 ReservedA8ReservedB8ReservedC8Reserved08 ReservedE8ReservedF8ReservedenQ)U'>Q)cen...Jli EXAS ,~>INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-265

SN54AS887. SN74AS8878·BIT PROCESSORSset bit instruction (set1): INO ... 0816This instruction (Figure 3) is used to force selected bits to one (any combinatio!,,) of zero to eight bits).The desired bits are specified by an 8-bit mask (C3-CO):: (A3-AO) t consisting of register file address portsthat are not required to support this instruction. All bits that are in the same bit positions as ones in themask are forced to a logical one. The 83-80 address field is used for both source and destination of thisinstruction. The S bus is the source word for this instruction. SIOO must be forced low for proper operation.If SIOO is high, data on the S bus is passed unaltered. The status set by the set bit instruction is as follows:NNone (force to zero)OVR None (force to zero)Cn + 8 None (force to zero)ZResult equal zerot The symbol '::' is concate'nation operatorreset bit instruction (setO): 17·10 .. 1816rC/)CCD

SN54AS887, SN74AS8878·BIT PROCESSORStest bit (one) instruction (TB1): 17·10 = 2816This instruction (Figure 4) is used to test selected bits for ones. Bits to be tested are specified by an 8-bitmask (C3-CO)::(A3-AO) consisting of register file address ports that are not required to support thisinstruction. Write Enable (WE) is internally disabled during this instruction. The test will pass if the selectedbyte has ones at all bit locations specified by the ones of the mask (Figure 5). The 5 bus is the sourceword for this instruction. 5100 must be forced low for proper operation. The status set by the test bit(one) instruction is as follows:NOVRCn +8ZNone (force to zero)None (force to zero)None (force to zero)PassSELECTPASS/FAILZERO'SI070107Cn +8PGTESTSIOO0100C n-=•(J)Q)(,)"S;Q)Cen..Jtest bit (zero) instruction (TBO): 17·10 = 3816NOTES: 1. Force 5100 low for proper operation.2. Bit mask (C3·COI::(A3-AOI will define bits for testing.3, Pass/fail is indicated on Z output.FIGURE 4. TEST BITThis instruction (Figure 4) is used to test selected bits for ones. Bits to be tested are specified by an B-bitmask (C3-CO)::(A3-AO) consisting of register file address ports that are not required to support thisinstruction. Write Enable (WE) is internally disabled during this instruction. The test will pass if the selectedbyte has zeros at all bit locations specified 'by the ones of the mask (Figure 6). The 5 bus is the sourceword for this instruction. 5100 must be forced low for proper operation. The status set by the test bit(zero) instruction is as follows:NOVRCn +8ZNone (force to zero)None (force to zero)None (force to zero)PassTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-267

SN54ASBB7, SN74ASBB7B·BIT PROCESSORSTEST PASSES "'" ZERORsl' I' I' I' 1 0 1 0 101 01C::AI,I,I,I,IIOIOIOIOISIOOA3·AO83·80C3·CO"0"IIIrC/)Cm

SN54AS887, SN74AS8878·BIT PROCESSORSabsolute value instruction (ABS): 17-10 = 4816This instruction is used to convert two's complement numbers to their positive value. The operand placedon the S bus is the source for this instruction. The' AS887 will test the sign of the S bus and force theSSF pin to the proper value. The status set by the absolute value instruction is as follows:NOVRCn +8ZInput MSB equal oneInput equal 80 (hex)S = 0Result equal zerosign magnitude/two's complement instruction (SMTC): 17-10 = 5816This instruction allows conversion from two's complement representation to sign magnitude representation,or vice-versa, in one clock cycle. The operand placed on the S bus is the source for this instruction.When a negative zero (80 hex) is converted, the result is 00 with an overflow. If the input is in two'scomplement notation, the overflow indicates an illegal conversion. The status set by the signmagnitude/two's complement instruction is as follows:NOVRCn +8ZResult MSB equal oneInput equal 80 (hex)Input equal 00 (hex)Result equal zeroadd immediate instruction (ADDI): 17-10 = 6816This instruction is used to add a specified constant value to the operand placed on the S bus. The constantwill be between the values of 0 and 1 5. The constant value is specified by the unused register file address(A port) not required to support this instruction. Forcing the carry input will add an additional one to theresult. The status set by the add immediate instruction is as follows:NOVRCn +8ZResult MSB equal oneArithmetic signed overflowCarry out equal oneResult equal zero(/)Q)(.)'SQ)cen-Isubtract immediate instruction (SUBI): 17-10 = 7816This instruction is used to subtract a specified constant value from the operand placed on the S bus. Theconstant value is specified by the unused register file address (A port) that is not required to support thisinstruction. The constant applied is the least significant four bits of a two's complement number. The devicesign extends the constant over the entire word length. The status set by the subtract immediate instructionis as follows:NOVRCn +8ZResult MSB equal oneArithmetic signed overflowCarry out equal oneResult equal zeroTEXAS ~INSTRUMENTSPOST OFFICE BOX,225012 • DALLAS, TEXAS 752652-269

SN54AS887, SN74AS8878·BIT PROCESSORSgroup 4 instructionsHex code 0 of Groupsummarized in Table 6.instructions is used to access Group 4 instructions. Group 4 instructions areTABLE 6. GROUP 4 INSTRUCTIONSrOOCCDc:::c:;CDtnINSTRUCTION BITS (17-10)OP CODE (HEX)select SIR instruction (SELl: 17-10 = 1016MNEMONIC00 Reserved10 SEL Select SIRFUNCTION20 SNORM Single Length Normalize30 DNORM Double Length Normalize40 DIVRF Divide Remainder Fix50 SDIVQF Signed Divide Quotient Fix60. SMUll Signed Multiply Iterate70 SMULT Signed Multiply Terminate80 SDIVIN Signed Divide Initialize90 SDIVIS Signed Divide StartAO SDIVI Signed Divide IterateBO UDIVIS Unsigned Divide StartCO UDIVI Unsigned Divide IterateDO UMULI Unsigned Multiply IterateEO SDIVIT Signed Divide TerminateFO UDIVIT Unsigned Divide TerminateThis instruction is used to pass either the S bus or the R bus to the output depending on the state of theSSF input pin. Normally, the preceding instruction would test the two operands and the resulting statusinformation would be used to force the SSF input pin. SSF = 0 will output the R bus and SSF = 1 willoutput the S bus. The status set by the select SIR instruction is as follows:NOVRCn +8ZResult MSB equal oneNone (force to zero)None (force to zero)Result equal zerosingle-length normalize instruction (SNORMI: 17-10 = 2016This instruction will cause the contents of the MO register to shift toward the most significant bit. Zerosare shifted in via the 0100 input. The number of shifts performed can be counted and stored in one ofthe register files by forcing a high at the Cn input. When the two most significant bits are of oppositevalue, normalization is complete. This condition is indicated on the microcycle that completes thenormalization at the OVR output.The chip contains conditional logic that inhibits the shift function (and also inhibits the register file increment)if the number within the MO register is already normalized at the beginning of the instruction (Figure 7).The status set by the single-length normalize instruction is as follows:NOVRCn +8ZMSB of resultMSB XOR 2nd MSBCarry out equal one,Result equal zero2-270 TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54AS887. SN74AS8878·81T PROCESSORSSINGLE-LENGTH NORMALIZEDOUBLE-LENGTH NORMALIZEtnQ)CJ0>Q)cen...JFIGURE 7. SINGLE- AND DOUBLE-LENGTH NORMALIZETEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-271

SN54AS887. SN74AS8878·BIT PROCESSORSdouble-length normalize instruction (DNORM): 17-10 = 3016This instruction will cause the contents of a double-length word (register file contains the most significanthalt and the MO register contains the least significant half) to shift toward the most significant bit. Zerosare shifted in via the 0100 input. When the two most significant bits are of opposite value, normalizationis. complete. This condition is indicated on the microcycle that completes the normalization at the OVRoutput.The chip contains conditional logic which inhibits the shift function if the number is already normalizedat the beginning of the instruction (Figure 7). The most significant half of the operand must be placedon the S bus. The status set by the double-length normalize instruction is as follows:NOVRCn +8ZMSB of resultMSB XOR 2nd MSBNone (force to zero)Result equal zeromultiply operationsIIr,encCD

SN54AS887. SN74AS8878·BIT PROCESSORSSMUll, SMUl TUMULIIIenQ)(.)'S:Q)cUJ..JFIGURE 8. MULTIPLICATION OPERATIONSTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-273

SN54AS887, SN74AS8878·BIT PROCESSORSThe unsigned multiply iterate (UMULI) performs an unsigned mUltiplication iteration. This instructioninterprets M(S-J) as the S-J bit of the multiplier. The shift is a double-precision right shift with the carryout from the P(J) + Multiplicand x M(S-J) operation forced into bit S of P(J + 1). This instruction is usedin unsigned and mixed multiplication.signed multiplicationSigned multiplication performs a ten clock cycle, two's complement mUltiply. The instructions necessaryto produce an algebraically correct result proceed in the following manner:Zero register to be used for accumulatorLoad MQ with multiplierSMUll (repeat 7 times)SportR portF portAccumulatorMultiplicandIteration ResultIIrCJ)CCD

SN54AS887, SN74AS8878·BIT PROCESSORSThe status set by the unsigned multiply iteration is meaningless except on the final execution of theinstruction. The status set by the unsigned multiply iteration instruction is as follows:NOVRCn+SZResult MSB equal oneForced to zeroCarry out equal to oneDouble-precision result is zeromixed multiplicationMixed multiplication multiplies a signed multiplicand times an unsigned multiplier to produce a signed resultin ten clocks. The steps are as follows:Zero register used for accumulatorLoad MQ with unsigned multipler .SMUll (S times)SportR portF portAccumulatorMultiplicandIteration resultUpon completion. the accumulator will contain the S most significant bits and MQ will contain the 8 leastsignificant bits of the product.The following status is set by the last SMUll instruction:NOVRCn+SZdivide operationsResult MSB equal oneForced to zeroCarry out equal to oneDouble-precision result is zeroThe divide uses a nonrestoring technique to perform both signed and unsigned division of a 16 bit integerdividend and an S bit integer divisor (Figure 9). It produces an 8 integer quotient and remainder.The remainder and quotient will be such that the following equation is satisfied:(Quotient) x (Divisor) + Remainder = DividendThe processor has the following divide instructions:1. UNSIGNED DIVIDE START (UDIVIS): 17-10 = B0162. UNSIGNED DIVIDE ITERATE (UDIVI): 17-10 = C0163. UNSIGNED DIVIDE TERMINATE (UDIVIT): 17-10 = F0164. SIGNED DIVIDE INITIALIZE (SDIVIN): 17-10 = 80165. SIGNED DIVIDE OVERFLOW TEST (SDIVO): 17-10 = AF166. SIGNED DIVIDE START (SDIVIS): 17-10 = 90167. SIGNED DIVIDE ITERATE (SDIVI): 17-10 = A0168. SIGNED DIVIDE TERMINATE (SDIVIT): 17-10 = E0169. DIVIDE REMAINDER FIX (DIVRF): 17-10 = 401610. SIGNED DIVIDE QUOTIENT FIX (SDIVQF): 17-10 = 5016t/)Q)(.)oS;cQ)en...JTEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • OALLAS. TEXAS 752652-275

SN54AS887, SN74AS8878·BIT PROCESSORSSDIVIN, SDIVS, SDIVIlEISDIVTFIGURE 9. DIVIDE OPERATIONS2-276TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54AS887. SN74AS8878·BIT PROCESSORSUDIVS. UDIVIUDIVT(J)Q)(,)'S;Q)cen...JFIGURE 9. DIVIDE OPERATIONS (Continued)TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-277

SN54AS887, SN74AS8878·BIT PROCESSORSThe unsigned divide iterate start (UDIVIS) instruction begins the iterate procedure while testing for overflow.Overflow is reported when the first subtraction of the divisor from the MSH of the dividend produces carryout. The test detects quotient overflow and divide by zero.The unsigned divide iterate terminate (UDIVIT) instruction completes the iterate procedure generating thelast quotient bit.The signed divide initialize (SDIVIN) instruction prepares for iteration by shifting the dividend and storingthe sign of the dividend for use in the following instructions and overflow tests.The signed divide overflow test (SDIVO) checks for overflow possibilities. This instruction may be deletedfrom the divide operation if the OVR pin is ignored. If it is removed some overflow conditions will goundetected. WE must be high (writing inhibited) when this instruction is used.The signed divide iterate start (SDIVIS) instruction calculates the difference between the divisor and MSHof the dividend. Partial detection of overflow is also done during this instruction. Operations with like signs(positive quotient) and division by zero will overflow during this instruction (including zero divisor). Operationswith unlike signs are tested for overflow during the signed divide quotient fix instruction (SDIVQF). Partialoverflow results are saved and will be used during SDIVQF when overflow is reported.IrQ)cCD

SN54AS887. SN74AS8878·BIT PROCESSORSsigned divide usageThe instructions necessary to perform an algebraically correct division of signed numbers are as follows:Load MQ with the least significant half of the dividendSDIVIN Sport MSH of dividendR port DivisorF port Intermediate resultSDIVO Sport Result of SDIVINR port DivisorF port Test result(WE must be high)SDIVIS Sport Result of SDIVINR port DivisorF port Intermediate resultSDIVI (SN-2 times) Sport Result of SDIVIS (or SDIVI)R port DivisorF port Intermediate resultSDIVIT Sport Result of last SDIVIR port DivisorF port Intermediate resultDIVRF Sport Result of SDIVITR port DivisorF port RemainderSDIVQF Sport MQ registerR port DivisorF port QuotientThe status of all_signed divide instructions except SDIVIN, DIVRF, and SDIVQF is as follows: .NOVRCn+SZForced to zeroForced to zeroCarry out equal to oneIntermediate result is zeroIIItJ)Q)(.)'SQ)Cen...JThe status of the SDIVIN instruction is as follows:NOVRCn+SZForced to zeroForced to zeroForced to zeroDivisor is zeroThe status of the DIVRF instruction is as follows:NOVR'Cn+SZForced to zeroForced to zeroCarry out equal to oneRemainder is zeroTEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-279

SN54ASQ87, SN74AS8878·BIT PROCESSORSThe status of the SDIVQF instruction is as follows:NOVRCn+SZSign of quotientDivide overflowCarry out equal to oneQuotient is zeroThe quotient is stored in the MQ register and the remainder is stored in the register file location that originallyheld the most significant word of the dividend. If fractions are divided, the quotient must be shifted rightone bit and the iemainder right three bits to obtain the correct fractional representations.The signed division algorithm is summarized in Table 7.TABLE 7. SIGNED DIVISION ALGORITHMrC/)CCD

SN54AS887. SN74AS8878·BIT PROCESSORSThe status of the UDIVIS instruction is as follows:NOVRCn +8ZForced to zeroDivide overflowCarry out equal to oneIntermediate result is zeroIf fractions are divided, the remainder must be shifted right two bits to obtain the correct fractionalrepresentation. The quotient is correct as is. The quotient is stored in the MQ register at the completionof the divide.The unsigned division algorithm is summarized in Table 8.TABLE 8. UNSIGNED DIVISION ALGORITHMgroup 5 instructionsOP CLOCK INPUT INPUT OUTPUTMNEMONICCODE CYCLES SPORT R PORT F PORTE4 LOADMQ 1 Dividend (LSH) - Dividend (LSH)BO UDIVIS 1 Dividend (MSH) Divisor RemainderCO UDIVI 7 Remainder Divisor RemainderFO UDIVIT 1 Remainder Divisor Remainder (Unfixed)40 DIVRF 1 Remainder (Unfixed) Divisor RemainderHex code F of Group instructions is used to access Group 5 instructions. Group 5 instructions aresummarized in Table 9.INSTRUCTION BITS (17-10)OP CODE (HEX)TABLE 9. GROUP 5 INSTRUCTIONSMNEMONICOF CLR Clear1F CLR Clear2F CLR Clear3F CLR Clear4F CLR Clear5F CLR Clear6F CLR Clear7F BCDBIN BCD to Binary8FReservedFUNCTION~F EX3C Excess-3 Word CorrectionAF SDIVO Signed Divide Overflow CheckBF CLR ClearCF CLR ClearOF BINEX3 Binary to Excess-3EF CLR ClearFF NOP No OperationIIC/)Q)(J0:;cQ)en..JTEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-281

SN54AS887, SN74AS887B·BIT PROCESSORSIrencCD

SN54AS887, SN74AS8878·BIT PROCESSORSThe following code illustrates the BCD to binary conversion technique.Let ACC be an accumulator registerLet NUM be the register which contains the BCD numberLet MSK be a mask registerLOADMQ NUMSUB ACC, ACC, SLCMQSUB, MSK, MSK, SLCMQSLCMQSLCMQADD I ACC, MSK, 1510AND MQ, MSK, R1, SLCMQADD, ACC, R1, R1, SLCMQBCDBIN, R1, R1, ACCBCDBIN, ACC, R1, ACCAND MQ, MSK, R1ACC+R1 - ACC; LOAD MQ WITH BCD NUMBER; CLEAR ACC AND ALIGN MQ; CLEAR MSK AND ALIGN MQ; ALIGN; ALIGN; MSK = 1510; EXTRACT ONE DIGIT; ALIGN MQ; ACC + DIGIT; IS STORED IN R1; ALIGN MQ; 4 x (ACC + DIGIT); IS STORED IN ACC; ALIGN MQ; 10 x (ACC + DIGIT); IS STORED IN ACC; ALIGN MQ; FETCH LAST DIGIT; ADD IN LAST DIGITThe previous code generates a binary number by executing the standard conversion formula for a 2-digitBCD number.AB = A x 10 + BNotice that the conversion begins with the most significant BCD digit and that the addition is performedin radix 2.EllCJ)Q)(J'>Q)cen..Jbinary to excess-3 instructions (BINEX3): 17-10 -= DF16This instruction (Figure 11) allows the user to convert an 8-bit binary number to 2-digit excess-3 numberrepresentation in 19 clocks. The data on the Rand S ports are summed with the MSB of the MQ register.The MQ register is simultaneously shifted left circularly. The status set by the binary to excess-3 instructionis as follows: .NOVRCn +8ZMSB of resultSigned arithmetic overflowCarry out equal oneResult equal zeroTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-283

SN54AS887, SN74AS8878·BIT PROCESSORSBCDBINIrC/)FIGURE 10. BCD TO BINARYBINEX3CCD~.nCDt/)FIGURE 11. BINARY TO EXCESS-32-284TEXAS -I.!}INSTRUMENTSPOST OFFice BOX 225012 • DALLAS. TeXAS 75265

SN54AS887, SN74AS8878·BIT PROCESSORSThe following illustrates the binary to excess-3 conversion technique.Let NUM be a register containing an unsigned binary numberLet ACC be an accumulatorM1:M2:M3:L 1:L2:LOADMQ NUMCLEAR ACCSET1 ACC H/33/BINEX3 ACC, ACC, ACCEX3C ACC, ACC; LOAD MQ WITH BINARY; NUMBER; CLEAR ACC; ACC -+ HEX/3333 .; DOUBLE ACC AND ADD IN; MSB OF MQ; ALIGN MQ; EXCESS 3 CORRECT; REPEAT L 1 AND L2; 7 TIMESThe previous code generates an excess-3 number by executing the standard conversion formula for a binarynumber.an2n + an - 12n - 1 + an - 22n - 2 + ... ao20 = [(2an + an - 1)2 + an - 212 + ... aoNotice that the conversion begins with the most significant binary bit and that the addition is performedin radix-10 (excess-3).decimal arithmeticDecimal numbers are represented in excess-3 code. Excess-3 code numbers may be generated by addingthree to each digit of a Binary Coded Decimal (BCD) number. The hardware necessary to implement excess-3arithmetic is only slightly different from binary arithmetic. Carries from one digit to another during additionin BCD occur when the sum of the two digits plus the carry-in is greater than or equal to ten. If both numbersare excess-3, the sum will be excess-6, which will produce the proper carries. Therefore, every additionor subtraction operation may use the binary adder. To convert the result from excess-6 to excess-3, onemust consider two cases resulting from a BCD digit add: (1) where a carry-out IS produced, and (2) wherea carry-out is not produced. If a carry-out is not produced, three must be subtracted from the resultingdigit. If a carry is produced, the digit is correct as a BCD number. For example, if BCD 5 is added to BCD 6,the excess-3 result would be 8 + 9 = 1 (with a carry). A carry rolls the number through the illegal BCDrepresentations into a correct BCD representation. Binary 3 must be added to digit positions that producea carry-out to correct the result to an excess-3 representation. Every addition and subtraction instructionstores the carry generated from each 4-bit digit location for use by the excess-3 correction function. Thecorrection instruction must be executed in the clock cycle immediately after the addition or subtractionoperation.IIen(1)CJ"S;(1)cen...JTEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-285

SN54AS887, SN74AS8878·BIT PROCESSORSabsolute maximum rating over operating free-air temperature range (unless otherwise noted)Supply voltage, Vee1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VSupply voltage, Vee2 ........................................................ 3 VInput voltage .............................................................. 7 VHigh-level voltage applied to 3-state outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VOperating case temperature range: SN54AS887. . . . . . . . . . . . . . . . . . . . . . . . .. - 55 °e to 125°eOperating free-air temperature range: SN74AS887, SN74AS887-1 ..... , ......... ooe to 70 0 eStorage temperature range ......................................... - 65 °e to 150 °erecommended operating conditionsSN54AS887SN74AS887SN74AS887-1MIN NOM MAX MIN NOM MAXVCCl I/O supply voltage 4.5 5 5.5 4.5 5 5.5 VVCC2 STL internal logic supply voltage 1.9 2 2.1 1.9 2 2.1 VVIH High-level input voltage 2 2 VVIL Low-level input voltage 0.8 0.8 V10H High-level output current -1 -2.6 mAI All output except N and ZERO' 8 810L Low-level output current I N 16 16 mAI ZERO 48 48TC Operating case temperature -55 125TA Operating free-air temperature 0 70electrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)PARAMETERTEST CONDITIONSSN54AS887SN74AS887SN74AS887-1MIN TYpt MAX MIN Typt MAXVIK VCCl = 4.5 V, 11= -18 mA -1.2 -1.2 VVOHAll outputsexcept ZEROVCCl = 4.5 V to 5.5 V, 10H = -0.4 mA VCC- 2 VCC-2VCC1 = 4.5 V, 10H = -1 mA 2.4 VVCCl = 4.5 V, 10H = -2.6 mA 2.410H ZERO VCCl = 4.5 V, VOH = 5.5 V 0.1 0.1 mAAll outputsVOLexcept N and ZEROVCCl = 4.5 V, 10L = 8 mA 0.5 0.5N VCCl = 4.5 V, 10L = 16 mA 0.5 0.5VIIZERO VCCl = 4.5 V, 10L = 48 mA 0.5 0.5I/O VCCl = 5.5 V, VI = 5.5 V 0.1 0.1All others VCCl = 5.5 V, VI = 7 V 0.1 0.1IIHt VCCl = 5.5 V, VI = 2.7 V 20 20 p.AIlL t VCCl = 5.5 V, VI = 0.5 V -0.4 -0.4 mA10§ VCCl = 5.5 V, Vo = 2.25 V -30 -112 -30 -112 mAICCl VCCl = 5.5 V 150 130 mAICC2 VCC2 = 2.1 V 410 390 mAt All typical values are at VCC = 5 V, T A = 25°C.tFor I/O ports, the parameters IIH and IlL include the off-state current.§The output conditions have been chosen to produce a current that closely approximates one-half the true short-circuit current, lOS.UNIT°cUNITmA2-286 TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54AS887, SN74AS8878·BIT PROCESSORSSN54AS887 maximum switching characteristics, Vee(see Note 1)4.5 V to 5.5 V, TePARAMETERFROMTO (OUTPUT)(INPUT) Y Cn +8 G, P zt N OVR DA DBA3-AOB3-BODA7-DAO,DB7-DBO62 42 48 69 62 60 18 1847 28 28 58 50 42 - -Cn 25 14 - 32 24 18 - -EA 54 32 35 62 52 52 - -EB 54 32 35 62 52 52 - -17-10 58 32 32 62 52 41 - -tpd OEB - - - - - - - 14OEY 14 - - - '- - - -QIO (n)Shift510 (n)Shift15 - - 24 - - - -15 - - 24 22 - - -CK 68 60 56 62 50 68 38 38OEA - - - - - - 14 -QIO655032585858----70-SID665032585858----70-UNITnst Load resistor R1 = 100 fl.NOTE 1: Load circuit and voltage waveforms are shown in Section 1.SN74AS887 maximum switching characteristics, VeeNote 1)PARAMETER4.5 V to 5.5 V, TAFROMTO (OUTPUT)(INPUT) Y Cn +8 G.P zt N OVRA3-AOB3-BO54 36 42 60 52 50DA7-DAO,DB7-DBO44 26 26 52 46 38Cn 25 8 - 32 24 18EA 49 29 29 58 49 47EB 49 29 29 58 49 4717-10 55 30 30 60 49 39tpd OEB - - - - - -OEY 12 - - - - -010 (n)Shift15 - - 24 - -SIO (n)Shift15 - - 24 19 -CK 58 55 52 61 52 62OEA - - - - - -t Load resistor R1 = 100 fl.NOTE 1: Load circuit and voltage waveforms are shown in Section 1.DADB18 18- -- -- -- -- -- 12- -- --' -35 3512 -o °e to 70 0 e (seeUNITQIO SIO58 5844 4431 3154 5454 5454 54- - ns- -- -- -60 60- -t/)Q)(,)oSQ)Cen-oJTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-287

SN54ASBB7, SN74ASBB7B·BIT PROCESSORSEIrrJ)CCD

SN54AS887, SN74AS8878-BIT PROCESSORSspecial instruction switching characteristicsThe SSF pin is used internally during certain instructions. The following tables list the instructions which forcethe SSF pin during their execution. The propagation delay from various inputs is also shown. The parameterwhich limits normal system performance is indicated by a dagger.SN54AS887 SSF PIN DELAYS AND SETUP TIMESHEX INPUT - SSF Insl SSF SETUPMNEMONICCODE Cn Ilnl CK BInI TIME InslSNORM 20 - 29 T 46 - 20DNORM 30 - 29 55 40t 20DIVRF 40 - 29t 46 - 20SDIVQF 50 - 26 t - - 18SMUll 60 - 26 t 43 - 0SDIVIN 80 - 48 64 44t 0SDIVIS 90 26 t 51 64 55 0SDIVI AO 26 t 51 64 55 0UDIVIS BO 18 t 45 64 46 0UDIVI CO 18t 50 54 40 0UMULI DO - 25 t 48 - 0SDIVIT EO 26 t 50 56 54 0ABX 48 - 34 62 39 t 20SMTC 58 - 29 58 39 t 20BINEX3 DF - 29t 58 - 18LOADMQ IArith) 23 t 34 62 40 0LOADMQ (Log) - 33 62 40t 0t This parameter limits normal system performance.ElltnQ)CJ"SQ)cen...JTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-289

SN54ASBB7. SN74ASBB7B·BIT PROCESSORSIIMNEMONICSN74AS887 SSF PIN DELAYS AND SETUP TIMESHEXINPUT'" SSF (ns)CODE Cn I(n) CKSNORM 20 - 26 T 40DNORM 30 - 26 52DIVRF 40 - 26 t 40SDIVQF 50 - 25 t -SMUll 60 - 25 t 40SDIVIN 80 - 38 60SDIVIS 90 24t 48 60SDIVI AO 24t 48 60UDIVIS 80 17t 43 60UDIVI CO 17t 44 52UMULI DO - 26 t 40SDIVIT EO 25 t 46 52A8X 48 - 32 60SMTC 58 - 26 5281NEX3 DF - 26 t 40LOADMQ (Arith) 22t 32 50LOADMQ (Log) - 32 50t This parameter limits norma) system performance.SSF SETUPB(n) TIME (ns)- 1737 t 17- 17- 17- 040t 052 052 045 037 0- 049 038 1738 t 17- 1738 038 t 02-290 TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54AS887, SN74AS8878·BIT PROCESSORSSN74AS887·' SSF PIN DELAYS AND SETUP TIMESHEXINPUT -+ SSF InslMNEMONICCODE C n Ilnl CKSNORM 20 - 23 f 28DNORM 30 - 23 40DIVRF 40 - 23 t 27SDIVQF 50 - 23 t -SMUll 60 - 22t 27SDIVIN 80 - 35 46SDIVIS 90 22t 42 48SDIVI AO 22t 42 46UDIVIS BO 16 t 42 46UDIVI CO 16 t 36 46UMULI DO - 22t 27SDIVIT EO 21t 40 44ABX 48 - 28 46SMTC 58 - 24 44BINEX3 DF - 23 t 27LOADMO IArithl 19 t 28 40LOADMO (Logl - 28 35SSF SETUPBInI TIME Insl- 1434t 14- 14- 14- 035 t 042 042 038 034 0- 042 030 t 1430 t 14- 1430 030 t 0t This parameter limits normal system performance.tJ)Q)(.)'S:Q)cen...JTEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-291

IIrC/)cCD

•STL-AS Technology0 Parallel a-Bit ALU with Expansion Inputsand Outputs0 13 Arithmetic and Logic Functions•a Conditional Shifts (Single and DoubleLength)0 9 Instructions that Manipulate Bytes0 4 Instructions that Manipulate Bits0 Add and Subtract Immediate Instructions0 Absolute Value Instruction., Signed Magnitude to/from Two'sComplement Conversiono Single- and Double-Length Normalizeo Select Functionso Signed and Unsigned Divides with OverflowDetection; Input does not Need to bePrescaledo Signed, Mixed, and Unsigned Multiplieso Three-Operand, 16-Word. Register Filedescription• Full Carry Look Ahead SupportSN54AS888, SN74AS8888-BIT PROCESSOR SLICESMARCH 1985-REVISED JANUARY 1986• Sign, Carry Out, Overflow, and Zero-DetectStatus CapabilitiesoExcess-3 BCD Arithmetico Internal Shift Multiplexers that Eliminate theNeed for External Shift Control Parts• ALU Bypass Path to Increase Speeds ofMultiply, Divide, and Normalize Instructionsand to Provide New Instructions such as BitSet, Bit Reset, Bit Test, Byte Subtract, ByteAdd, and Byte Logicalo 3-0perand Register Files to Allow anOperation and a Move Instruction to beCombinedo Byte Select Controlled by External 3-StateBuffers that may be Eliminated if Bit andByte Manipulation are not Neededo Bit and Byte Masks that are Shared withRegister Address Fields to Minimize ControlStore Word Widtho 3 Data Input/Output Paths to MaximizeData ThroughputThese 8-bit Advanced Schottky TTL integrated circuits are designed to implement high performance digitalcomputers or controllers. An architecture and instruction set has been chosen that supports a fast systemclock, a narrow micro-code word width, and a high system throughput. The powerful instruction set allowshigh-speed system architecture to be implemented and also allows an existing system's performance tobe upgraded while protecting software investments. These processors are designed to be cascadable toany word width 16 bits or greater.The SN54AS888 is characterized for operation over the full military temperature range of - 55°C to 125°C.The SN74AS888 and SN74AS888-1 are characterized for operation from ooe to 70°C.Package options include both plastic and ceramic chip carriers in addition to a 68-pin grid array ceramicpackage.•enQ)o'SQ)c(/)-IPRODUCTION OATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments~~~~~~~~i~ar~:I~~e ~!~ti~~ti~r fllo~:~:~:t:ros~s notTEXAS -I.!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265Copyright © 1982, Texas Instruments Incorporated2-293

~SN54AS888, SN74AS8888·BIT PROCESSOR SLICESr-t/)CCD

SN54AS888. SN74AS8888·BIT PROCESSOR SLICESPIN FUNCTIONAL DESCRIPTIONPIN GRID CHIPNAMEARRAY CARRIERA-l0 28 PPPB-7 29 SSFA-9 30 ZEROA-8 31 P/OVRA-7 32 G/NA-6 33 Cn +8I/OII/OI/O000DESCRIPTIONPackage position pin. Tri-Ievel input used to define package significance duringinstruction execution. Leave open for intermediate positions, tie to VCC for mostsignificant package, and tie to GND for least significant package.Special shift function. Used to transfer required information between packages duringspecial instruction execution.Device zero detection, open collector. Input during certain special instructions.ALU propagate/instruction overflow for most significant package, low active.ALU generate/negative result for most significant package, low active.ALU ripple carry output.B-6 34 SI07A-5 35 QI07A-4 36 QIOOA-3 37 SIOOA-2 38 CnB-4 39 10B-3 40 11B-1 41 12B-2 42 13B-5 43 14C-l 44 150-1 45 16E-l 46 17C-2 47 VCC20-2 48 VCClE-2 49 OEAF-l 50 EAF-2 51 GNDG-2 52 DAOH-2 53 DAlG-l 54 DA2H-l 55 DA3J-l 56 DA4J-2 57 DA5K-l 58 DA6K-2 59 DA7L-2 60 CKK-3 61 COL-3 62 ClK-4 63 C2L-4 64 C3K-5 65 AOL-5 66 AlL-6 67 A2K-6 68 A3I/OI/OI/OI/OIIIIIIIIIIII/OI/OI/OI/OI/OI/OI/OI/OIIIIIIIIIBidirectional shift pin, low active.ALU carry input.Instruction input.Low voltage power supply (2 V).I/O interface supply voltage (5 V).DA bus enable, low active.ALU input operand select. High state selects external DA bus and low state selectsregister file.Ground pin.A port data bus. Outputs register file data (EA = 0) or inputs external data (EA = 1).Clocks all synchronous registers on positive edge.Register file write address select.Register file A port read address select.fJIC/)Q)o"S;Q)CCJ)-ITEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-295

SN54AS888, SN74AS88B8·BIT PROCESSOR SLICESPIN FUNCTIONAL DESCRIPTIONIIPIN GRID CHIPARRAY CARRIERNAME 1/0K-7 1 WE IL-7 2 B3 IL-8 3 B2 IL-9 4 Bl IL-l0 5 BO IK-l0 6 EBO IK-ll 7 EBl 1K-9 8 OEB IK-8 9 DB7· 1/0H-l0 10 DB6 1/0J-ll 11 DB5 1/0H-ll 12 DB4 1/0G-ll 13 bB3 110F-ll 14 DB2 110E-ll 15 DBl 110G-l0 16 DBO 1/0J-l0 17 SELY I0-11 18 Y7 1/0C-ll 19 Y6 1100-10 20 Y5 110C-l0 21 Y4 110F-l0 22 Y3 1/0E-l0 23 Y2 110B-ll 24 Yl 110B-l0 25 YO 110B-9 26 DEY IF-2 27 GNDDESCRIPTIONRegister file (RF) write enable. Data is written into RF when WE is low and a low-to·highclock transition occurs. RF write is inhibited when WE is high.Register file B port read address select. (0 = LSB).ALU input operand select. EBO and EB 1 selects the source of data that the S multiplexerprovides for the S bus. Independent control of the DB bus and data path selection allowthe user to isolate the DB bus while the ALU continues to process data.DB bus enable, low active.B port data bus. Outputs register data (OEB = 0) or used to input external data(DEB = 1), (0 = LSB).Y bus select, high active.Y port data bus. Outputs instruction results (DEY = 0) or used to put external data intoregister file (DEY = 1).Y bus output enable, low active.Ground pin2-296TEXAS -IJ}INSTRUMENTSPOST OFFICE BOX 22.5012 • DALLAS. TEXAS 75265

SN54AS888, SN74AS8888·BIT PROCESSOR SLICESfunctional block diagram4C3-CO4A3-AO U--.r-t------i16 X 8REGISTER FILE4WECKB3-BO8DA7-DAO ~t--+--t---t~-----.88OEBDB7-DBOOEAEAU---t-----~P/OVR

SN54AS888, SN74AS8888·BIT PROCESSOR SLICESlEIrencen

SN54AS888, SN74AS8888·BIT PROCESSOR SLICESMQ registerY busstatusThe multiplier-quotient (MQ) register has specific functions in multiplication, division, and normalization.This register may also be used as a temporary storagEi! register. The MQ register may be loaded if theinstruction code on pins 17-10 is E1-E7 or E9-EE (See Table 1).The Y bus contains the output of the ALU shifter if OEY is low and is a high impedance input if OEY ishigh. SEL Y must be low to pass the internal ALU shift bus and must be high to pass the external Y busto the register file.Four status pins are available on the most significant package, overflow (OVR), sign (N)' carry out (C n + 8),and zero (ZERO). The Cn + 8 line signifies the ALU result while OVR, ZERO, and N refer the status afterthe ALU shift has occurred. Notice that the ZERO pin cannot be used to detect whether an input placedon a high impedance Y bus is zero.divide BCD flip-flopsThe multiply-divide flip-flops contain the status of the previous multiply or divide instruction. They areaffected by the following instructions:DIVIDE REMAINDER FIXSIGNED DIVIDE QUOTIENT FIXSIGNED MULTIPLYSIGNED MULTIPLY TERMINATESIGNED DIVIDE INITIALIZESIGNED DIVIDE STARTSIGNED DIVIDE ITERATEUNSIGNED DIVIDE STARTUNSIGNED DIVIDE ITERATEUNSIGNED MULTIPLYSIGNED DIVIDE TERMINATEUNSIGNED DIVIDE TERMINATEThe excess-3 BCD flip-flops are affected by all instructions except NOP. The clear function clears theseflip-flops. They preserve the carry from each nibble (4-bits) in excess-3/BCD operations.EllU)Q)CJ'SQ)cen-lpackage position pin (PPPIThe position of the processor in the system is defined by the voltage level applied to the package positionpin (PPP). Intermediate positions are selected by leaving the pin open. Tying the pin to Vce makes theprocessor the most significant package and tying the pin to GND makes the processor the least significantpackage.special shift function (SSFI pinConditional shifting algorithms may be implemented via control of the SSF pin. The applied voltage to thispin may be set as a function of a potential overflow condition (the two most significant bits are not equal)or any other condition (see Group 1 instructions).instruction setThe' AS888 bit-slice processor uses bits 17-10 as instruction inputs. A combination of bits 13-10 (Group 1instructions) and bits 17-14 (Group 2-5 instructions) are used to develop the 8-bit op code for a specificinstruction. Group 1 and Group 2 instructions can be combined to perform arithmetic or logical functionsplus a shift function in one instruction cycle. A summary of the instruction set is given in Table 1.TEXAS -I/}INSTRUMENTSPOST OFFICE BOX 225012 • OALLAS. TEXAS 752652-299

SN54AS888, SN74AS8888·BIT PROCESSOR SLICESTABLE 1. INSTRUCTION SETIIIINSTRUCTION BITS (13-10)HEX CODEGROUP 1 INSTRUCTIONSMNEMONICFUNCTION0 Accesses Group 4 instructions1 ADD R + S + C n2 SUBR R +S+Cn3 SUBS R +S+C n4 INCS S+Cn5 INCNS S+Cn6 INCR R+Cn7 INCNR R+C n8 Accesses Group 3 instructions9 XOR R XOR SA AND RAND SB OR R OR SC NAND R NAND SD NOR R NOR SE ANDNR RAND SFINSTRUCTION BITS (17-14)HEX CODEGROUP 2 INSTRUCTIONSMNEMONICAccesses Group 5 instructionsFUNCTION0 SRA Arithmetic Right Single1 SRAD Arithmetic Right Double2 SRL Logical Right Single3 SRLD Logical Right Double4 SLA Arithmetic Left Single5 SLAD Arithmetic Left Double6 SLC Circular Left Single7 SLCD Circular Left Double8 SRC Circular Right Single9 SRCD Circular Right DoubleA MOSRA Pass (F-V) and Arithmetic Right MOB MOSRL Pass (F-V) and Logical Right MOC MOSLL Pass (F-V) and Logical Left MOD MOSLC Pass (F--V) and Circular Left MOE LOADMQ Pass (F-V) and Load MO (F ~ MO)F PASS Pass (F-V)2-300 TEXAS.INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54AS888, SN74AS8888·BIT PROCESSOR SLICESTABLE 1. INSTRUCTION SET (Continued)GROUP 3 INSTRUCTIONSINSTRUCTION BITS (17·10)HEX CODEMNEMONICFUNCTION08 SET1 Set Bit18 SETO Reset Bit28 TB1 Test Bit (One)38 TBO Test Bit (Zero)48 ABS Absolute Value58 SMTC Sign Magnitude/Two's Complement68ADDI Add Immediate78SUBI Subtract Immediate88BADD Byte Add R to S98BSUBS Byte Subtract S from RA8BSUBR Byte Subtract R from SB8BINCS Byte Increment SC8BINCNS Byte Increment Negative S08BXOR Byte XOR Rand SE8BAND Byte AND Rand SF8BOR Byte OR Rand SINSTRUCTION BITS (17·10)HEX CODE00102030405060708090AOBOCODOEOFOGROUP 4 INSTRUCTIONSMNEMONICFUNCTIONReservedSEL Select SIRSNORM Single Length NormalizeDNORM Double Length NormalizeDIVRF Divide Remainder FixSDIVQF Signed Divide Quotient FixSMUll Signed Multiply IterateSMULT Signed Multiply TerminateSDIVIN Signed Divide InitializeSDIVIS Signed Divide StartSDIVI Signed Divide IterateUDIVIS Unsigned Divide StartUDIVI Unsigned Divide IterateUMULI Unsigned Multiply IterateSDIVIT Signed Divide TerminateUDIVIT Unsigned Divide Terminate(/)Q)(,)'SQ)cen...JTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-301

SN54ASBBB, SN74ASBBBB·BIT PROCESSOR SLICESTABLE 1. INSTRUCTION SET (Concluded)GROUP 5 INSTRUCTIONSINSTRUCTION BITS (17-10)HEX CODEMNEMONICFUNCTIONOF CLR ClearlF CLR Clear2F CLR Clear3F CLR Clear4F CLR Clear5F CLR Clear6F CLR Clear7F BCDBIN BCD to Binary8F EX3BC Excess-3 Byte Correction9F EX3C Excess-3 Word CorrectionAF SDIVO Signed Divide Overflow CheckBF CLR ClearCF CLR ClearOF BINEX3 Binary to Excess-3EF CLR ClearFF NOP No OperationrencCD

SN54AS888, SN74AS8888·BIT PROCESSOR SLICESGroup 1 instructions (excluding hex codes 0, 8, and Fl. shown in Table 2, may be used in conjunctionwith Group 2 shift instructions to perform arithmetic or logical functions plus a shift function t in oneinstruction cycle (hex codes 0, 8, and F are used to access Group 4, 3, and 5 instructions, respectively).Each shift may be made into a conditional shift by forcing the special shift function (SSF) pin into the properstate. If the SSF pin is high or floating, the shifted ALU output will be sent to the output buffers. If theSSF pin is pulled low externally, the ALU result will be passed directly to the output buffers. Conditionalshifting is useful for scaling inputs in data arrays or in signal processing algorithms.These instructions set the BCD flip·flop for the excess-3correct instruction. The status is set with thefollowing results (C n + 8 is ALU carry out and is independent of shift operation; others are evaluated aftershift operation).tDouble-precision shifts involve both the ALU and MO register.condition codeArithmeticNOVRCn +8ZLogicNOVRCn +8Zgroup 2 instructionsMSB of resultSigned arithmetic overflowCarry out equal oneResult equal zeroMSB of resultNone (force to zero)None (force to zero)Result equal zeroTABLE 3. GROUP 2 INSTRUCTIONStJ)Q)(.)'S;Q)C(/)-'INSTRUCTION BITS 07-14)HEX CODEMNEMONICFUNCTION0 SRA Arithmetic Right Single1 SRAD Arithmetic Right Double2 SRL Logical Right Single3 SRLD Logical Right Double4 SLA Arithmetic Left Single5 SLAD Arithmetic Left Double6 SLC Cifcular Left Single7 SLCD Circular Left Double8 SRC Circular Right Single9 SRCD Circular Right DoubleA MOSRA Pass (F~Y) and Arithmetic Right MOB MOSRL Pass (F~YI and Logical Right MOC MOSLL Pass (F~YI and Logical Left MOD MOSLC Pass (F~YI and Circular Left MOE LOADMO Pass (F~Y) and Load MO (F ~ MO)F PASS Pass (F~Y)TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-303

SN54AS888, SN74AS8888-BIT PROCESSOR SLICESThe processor's shift instructions are implemented by a combination of Group 2 instructions (Table 3)and certain wired connections on the packages used. The following external connections are required.On intermediate packages:SI07 is connected to SIOO of the next most significant package0107 is connected to 0100 of the next most significant packageSIOO is connected to SI07 of the next least significant package0100 is connected to 0107 of the next least significant packageOn the two end packages:SI07 on the most significant package is connected to SIOO of the least significant package0107 on the most significant package is connected to 0100 of the least significant packageThe connections are the same on all instructions including multiply, divide, CRC, and normaiization functions.Single- and double-precision shifts are supported. Double-precision shifts assume the most significant halfhas come through the ALu and will be placed (if WE is low) into the register file on the rising edge ofthe clock and the least significant half lies in the MO register. All Group 2 shifts may be made conditional(see previous page).rencCD

SN54AS888, SN74AS8888·BIT PROCESSOR SLICESSERIAL I/O (9900 CRU)Av.. 'LS446GAB-.,---aDIR ---:.-----1B•. tJ)Q)'S"Q)qen...I'AS888'AS888'AS88801001------1FIGURE 1. SERIAL 110TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54AS888, SN74AS8888·BIT PROCESSOR SLICESThe shift instructions are summarized in Table 4 and illustrated in Figure 2. In Figure 2 and all succeedingfigures that illustrate instruction execution, the following definitions apply:CRF CRC accumulator end fill.OBT End fill for signed divide.MOF End fill for unsigned divide.SRF End fill for signed multiply and the arithmetic right shifts.TABLE 4. SHIFT INSTRUCTIONSEIreno(])

SN54AS888, SN74AS8888-BIT PROCESSOR SLICESl-:>0e:(l- e:(c..J~a:wen5a:~I-:>0e:(I- e:(C..J~a:wen5a:0..en5:?..J0..en..Jw..JC-'2enl-:I:C-'a:ui=w2:I:!::c::e:(w..JCO:>0cI-:I:~e: a:ui=w2:I:!::a:e:(en20i=():>a:I- en~e: l- LLJ:enNwa::>C-'u::t/)Q)(.)0>Q)eC/)-ITEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-307

NWo00SERIAL DATA INPUT (CRU)(FILLS ZERO'IF NOT FORCED)sa::J!l\aa IS1 ILOGICAL RIGHT SINGLEC::OCl)=2-U"I-t~-Cl>:::eCl)CCOnCOmS=CI)CI)CI)c 2:::e"""~Cl)l>!::CI)nCOmCl)COco."a~~gz't5(J)~-l~t;:l~~ C l ")~~~~ ITIVJ~Z~ cri~x~'"MSPSERIAL DATA INPUT (CRU)IPLOGICAL RIGHT DOUBLELSPMSPIPLSPFIGURE 2. SHIFT INSTRUCTIONS (Continued)

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SN54AS888, SN74AS8888·BIT PROCESSOR SLICES2:e:{l e:{C..Je:{ex::..u(Ila..en..Ja..en...J>..J2:00~I- u.w..J..Je:{u(!)0..Ja..>..JZ00~I- u.w..Ja:e:{..J:::>Ua:U~:0-Q)"C:l(jc0~en2:0i=U::>a:I-en~I- LL~enNwa:::>(!)u:::fI1,.~~{, :itJ)Q)0'SQ)0en-oJ"r' ..,a..en~ l- :::>0e:{l- e:{c..Je:{ex:w(IlI- :::>0e:{I- e:{C..J~a:wena.CIl~TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-313

SN54AS888, SN74AS8888·BIT PROCESSOR SLICESgiQUp 3 instructionsHex code 8 of Groupsummarized in Table 5.instructions is used to access Group 3 instructions. Group 3 instructions areTABLE 5. GROUP 3 INSTRUCTIONSEIrenc

SN54AS888, SN74AS8888·BIT PROCESSOR SLICESset bit instruction (set1): 17·10 = 0816This instruction (Figure 3) is used to force selected bits of a desired byte(s) to one (any combination ofzero to eight bits). The desired bits are specified by an 8-bit mask (C3-CO)::(A3-AO) t consisting of registerfile address ports that are not required to support this instruction. All bits in the selected byte(s) that arein the same bit positions as ones in the mask are forced to a logical one. The 83-80 address field is usedfor both source and destination of this instruction. The desired byte is specified by forcing SIOO to a lowvalue. Nonselected packages pass the byte through unaltered. The S bus is the source word for thisinstruction. The status set by the set bit instruction is as follows:NOVRCn +8ZNone (force to zero)None (force to zero)None (force to zero)Result equal zerot The symbol '::' is concatenation operatorBYTEBYTE2BYTEBYTEoBYTE ..... -.----~------------~----~------------~-----+--------------.,INSTRUCTIONPPP OPENZERO ZERO SSF ZEROSi07 SIOOCn+8pGCnCn+8pGCnCONDITIONAL ----.,ENABLEFIGURE 3. SET BIT (OR RESET BIT)NOTES: 1. Force S'i"6O low to select byte.2. Bit mask (C3-CO)::(A3-AO) will set desired bits to one.reset bit instruction (setO): 17-10 = 1816This instruction (Figure 3) is used to force selected bits of a desired byte(s) to zero (any combination ofone to eight bits). The desired bits are specified by an 8-bit mask (C3-CO)::(A3-AO) consisting of registerfile address ports that are not required to support this instruction. All bits in the selected byte(s) that arein the same bit positions as ones in the mask are reset. The 83-80 address field is used for both sourceTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • OALLAS. TEXAS 752652-315

SN54AS888, SN74AS8888·BIT PROCESSOR SLICESand destination of this instruction. The desired byte is specified by forcing SIOO to a low value. Nonselectedpackages pass the byte through unaltered. The S bus is the source word for this instruction. The statusset by the reset bit instruction is as follows:NOVRCn +8ZNone (force to zero)None (force to zero)None (force to zero)Result equal zerotest bit (one) instruction (TB1): 17·10 - 2816This instruction (Figure 4) is used to test selected bits of a desired byte(s)(any combination of one to eightbits). Bits to be tested are specified by an 8-bit mask (C3-CO):: (A3-AO) consisting of register file addressports that are not required to support this instruction. Write Enable (WE) is internally disabled during thisinstruction. The desired byte is specified by forcing SIOO to a low value. The test will pass if the selectedbyte has ones at all bit locations specified by the ones of the mask (Figure 5). The S bus is the sourceword for this instruction. The status set by the test bit (one) instruction is as follows:EIr-enC(1)

SN54AS888, SN74AS888. 8-BIT PROCESSOR SLICEStest bit (zero) instruction (TBO): 17-10 = 3816This instruction (Figure 4) is used to test selected bits of a desired byte(s) (any combination of one toeight bits). Bits to be tested are specified by an 8-bit mask (C3-CO)::(A3-AO) consisting of register fileaddress ports that are not required to support this instruction. Write Enable (WE) is internally disabled duringthis instruction. The desired byte is specified by forcing 5100 to a low value. The test will pass if the selectedbyte has zeros at all bit locations specified by the ones of the mask (Figure 6). The 5 bus is the sourceword for this instruction. The status set by the test bit (zero) instruction is as 'follows:NOVRCn +8ZNone (force to zero)None (force to zero)None (force to zero)PassMSSA3·AOLSSB3·BO R511 111111 ,0,0 ,0 ,01A3·AOB3·BOC3·COc::AllI111111101010101 ZERO c::AIQQQ11101010101TEST PASSES "1" ZEROQi'OOt-----t0107SIOOSi07"0"MSSLSSA3·AOR511 11 I 0 11 1 0 I 01 0 I 0 1 B3·BO R511 11 1 , 11 I 0 I 0 I 0 I 01"1"A3·AOB3·BO(J)Q)(.)"$Q)cen-IC3·COC3-C0C::A\1111111110IoI0Iol ZERO c::AI1\111111101010101TEST FAILS "0" ZEROQiOo t-----t 0107SIOOSI07"0""1"FIGURE 5. TEST BIT ONE EXAMPLESTEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-317

SN54AS888, SN74AS8888·BIT PROCESSOR SLICESMSSRsl 0 I 0 I 0 I 0 11 I 0 11 I 0 IlSSA3-AO83-80 Rsll I d d 1 101110111C3-C0A3-AO83-80C3-COTEST PASSES "1" ZEROc::AllI111111101110111 ZERO c::AIQQQ11101110111010o1------t ffiOjSIOOSi07rencCD~.(')CDenTEST FAilS "0" ZEROMSSC::A 11 11 11 1111 011 10 11 I~ ________________ S_IO_O~absolute value instruction (ABS): 17-10 = 4816"0"A3-AOlSS83-80 Rsll 11 1111 I 01110111C3-COZEROc::AIQ11111110111011101001-----~0107 ~"0"FIGURE 6. TEST BIT ZERO EXAMPLES~S~10~7~ ____________ ~SI~0~0This instruction is used to convert two's complement numbers to their positive value_ The operand placedon the S bus is the source for this instruction_ The MSP will test the sign of the S bus and force the SSFpin to the proper value_ All other packages use the SSF pin as input to determine instruction execution.The status set by the absolute value instruction is as follows:NOVRCn +8ZInput MSB equal oneInput equal 8000 (hex)S = aResult equal zero"1""1"A3-AO83-80C3-C0sign magnitude/two's complement instruction (SMTC): 17-10 = 5816This instruction allows conversion from two's complement representation to sign magnitude representation,or vice-versa, in one clock cycle_ The operand placed on the S bus is the source for this instruction.When a negative zero (8000 hex) is converted, the result is 0000 with an overflow_ If the input is in two'scomplement notation, the overflow indicates an illegal conversion_ The status set by the signmagnitude/two's complement instruction is as follows:NOVRCn +8ZResult MSB equal oneInput equal 8000 (hex)Input equal 0000 (hex)Result equal zero2-318 TEXAS -Ij}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54AS888. SN74AS8888·BIT PROCESSOR SLICESadd immediate instruction (ADD!): 17·10 = 6816This instruction is used to add a specified constant value to the operand placed on the S bus. The constantwill be between the values of 0 and 15. The constant value is specified by the unused register file address(A port) not required to support this instruction. Forcing the carry input will add an additional one to theresult. The status set by the add immediate instruction is as follows:NOVRCn +8ZResult MSB equal oneArithmetic signed overflowCarry out equal oneResult equal zerosubtract immediate instruction (SUB!): 17·10 = 7816This instruction is used to subtract a specified constant value from the operand placed on the S bus. Theconstant value is specified by the unused register file address (A port) that is not required to support thisinstruction. The constant applied isthe least significant four bits of a two's complement number. The devicesign extends the constant over the entire word length. The status set by the subtract immediate instructionis as follows:NOVRCn +8Zbyte instructionsResult MSB equal oneArithmetic signed overflowCarry out equal oneResult equal zeroThere are eight byte instructions in Group 3. These instructions modify selected bytes of the operand onthe S bus. A byte is selected by forcing SIOO to a low value (same as SET1, SETO, TB1, and TBOinstructions). Multiple bytes may be selected only if they are adjacent to one another.NOTE: At least one byte must be nOli\selected during these instructions.The nonselected bytes are passed through unaltered. Byte status is forced through the most significantpackage except for the sign of the result (N), which is forced to zero (low). The status set by the byteinstructions is as follows:(Most Significant Package)IIU)Q)CJ'SQ)Cen...JN'OVRCn +8ZGpCn +8ZGpCn +8ZNone (force to zero)Byte signed overflowByte carry ouf equal oneByte result equal to zero(Selected BYTES-other than MSP)Normal generateNormal propagateNormal carry outResult equal to zero(Nons elected BYTES-other than MSP)No generate (force to one)Propagate (force to zero)C nNone (force to one)TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-319

SN54AS888, SN74AS8888·BIT PROCESSOR SLICESgroup 4 instructionsHex code 0 of Groupsummarized in Table 6.instructions is used to access Group 4 instructions. Group 4 instructions areIIrencCD

SN54AS888, SN74AS8888·BIT PROCESSOR SLICESQ.en...J'Q.C/)...IwN::::i«:2:a:0Z::I:l- t!)Zw...JW...Jt!)Zen~wN::::i«:2:a:0Z::I:I-t!)Zw...JW...JCO':::>0c~wN::::i«~a:0z::I:l-(!)zw...JW...JCO;:)0CcZ«W...J(!)zen....:wa:;:)(!)u::BIt/)Q)(JoSQ)Cen...JQ.en:2:TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • OALLAS. TEXAS 752652-321

SN54AS888. SN74AS8888·BIT PROCESSOR SLICESdouble·length normalize instruction (DNORM): 17·10 = 3016This instruction will cause the contents of a double-length word (register file contains the most significanthalf and the MO register contains the least significant half) to shift toward the most significant bit. Zerosare shifted in via the 0100 input. When the two most significant bits are of opposite value, normalizationis complete. This condition is indicated on the microcycle that completes the normalization at the OVRoutput.The chip contains conditional logic which inhibits the shift function if the number is already normalizedat the beginning of the instruction (Figure 7). The most significant half of the operand must be placedon the S bus. The status set by the double-length normalize instruction is as follows:NOVRCn +8ZMSB of resultMSB XOR 2nd MSBNone (force to zero)Result equal zeromultiply operationsIThe ALU performs three unique types of N by N multiplies each of which produces a 2N-bit result (Figure 8).All three types of multiplication proceed via the following recursion:P(J + 1) = 2[P(J) + Multiplicand x M (8N-J))whereP(J)NP(J + 1)partial product at iteration number Jnumber of 'AS888 packages that are cascadedpartial product at iteration number J + 1J varies from 0 to 8N [N = 2 for 16 X 16 multiply)M (8N-J) =mode bit (unique to multiply type)2 denotes some type of shift (unique to multiply)Notice that by proper choice of mode terms and shifting operations, signed, unsigned, and mixed multiplies(signed times unsigned) may be performed.All mUltiplies assume that the multiplier is stored in MO before the operation begins (in the case of mixedmultiply, the unsigned number must be the multiplier).The processor has the following multiply instructions:1. SIGNED MULTIPLY ITERATE (SMUll): 17-10 = 60162. SIGNED MULTIPLY TERMINATE (SMULT): 17-10 = 70163. UNSIGNED MULTIPLY ITERATE (UMULI): 17-10 = 0016TEXAS -Ij}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54ASBBB, SN74ASBBBB·BIT PROCESSOR SLICESIl.(/)...Jc..(I)..J.- ...J::J~(/):::i::J~(/)!::::i::J~::Jc..enz0j::«a::wc..0z0j::«u::::ic..j::...J:;)~cOwa:::;)C!Ju:::II(/)Q)(J'$Q)Cen....IIl.(/)~c..(I)~TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-323

SN54AS888, SN74AS8888·BIT PROCESSOR SLICESI he signed multiply iterate (SMUll) instruction performs a signed times signed iteration. This instructioninterprets M(BN-J) as the BN-J bit of the multiplier. The shift is a double-precision right shift one bit. Thisinstruction is repeated 15 times for a 16 x 16 signed mUltiply. This instruction will be used 16 consecutivetimes for a mixed multiplication.The signed multiply terminate (SMUL T) instruction provides correct (negative) weighting of the sign bitof a negative multiplier in signed multiplication. The instruction is identical to signed multiply iterate (SMUll)except that M(BN-J) is interpreted as - 1 if the sign bit of the multiplier is 1, and 0 if the sign bit of themultiplier is O.The unsigned multiply iterate (UMULI) performs an unsigned multiplication iteration. This instructioninterprets M(BN-J) as the BN-J bit of the multiplier. The shift is a double-precision right shift with the carryout from the P(J) + Multiplicand x M(BN-J) operation forced into bit BN of P(J + 1). This instructionis used in unsigned and mixed multiplication.signed multiplicationIIr(J)CCD

SN54AS888. SN74AS8888·BIT PROCESSOR SLICESUpon completion, the accumulator will contain the aN most sighificant bits and-the MQ contains the aNleast significant bits of the product.The status set by the unsigned multiply iteration is meaningless except on the final execution of theinstruction. The status set by the unsigned multiply iteration instruction is as follows:NOVRCn+aZResult MSB equal oneForced to zeroCarry out equal to oneDouble-precision result is zeromixed multiplicationMixed multiplication multiplies a signed multiplicand times an unsigned multiplier to produce a signed resultin 8N + 2 clocks. The steps are as follows:Zero register used for accumulatorLoad MQ with unsigned multi pierSMUll (8N times)SportR portF portAccumulatorMultiplicandIteration resultUpon completion, the accumulator will contain the aN most significant bits and the MQ will contain theaN least significant bits of the product.The following status is set by the last SMUll instruction:NOVRCn+aZResult MSB equal oneForced to zeroCarry out equal to oneDouble-precision result is zeroenQ)(.)oSQ)cen..Jdivide operationsThe divide uses a nonrestoring technique to perform both signed and unsigned division of a 16N bit integerdividend and an aN bit integer divisor (Figure 9). It produces an aN integer quotient and remainder.The remainder and quotient will be such that the following equation is satisfied:(Quotient) x (Divisor) + Remainder = DividendThe processor has the following divide instructions:1. UNSIGNED DIVIDE START (UDIVIS): 17-10 = B0162. UNSIGNED DIVIDE ITERATE (UDIVI): 17-10 = C0163. UNSIGNED DIVIDE TERMINATE (UDIVIT): 17-10 = F0164. SIGNED DIVIDE INITIALIZE (SDIVIN): 17-10 = a0165. SIGNED DIVIDE OVERFLOW TEST (SDIVO): 17-10 = AF166. SIGNED DIVIDE START (SDIVIS): 17-10 = 90167. SIGNED DIVIDE ITERATE (SDIVI): 17-10 = A016a. SIGNED DIVIDE TERMINATE (SDIVIT): 17-10 = E0169. DIVIDE REMAINDER FIX (DIVRF): 17-10 = 401610. SIGNED DIVIDE QUOTIENT FIX (SDIVQF): 17-10 = 5016TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-325

SN54AS888, SN74AS8888·BIT PROCESSOR SLICESQ.CI)..JQ.CI)..Jr-rnCCDC(I)Z·:;C(I)!:I->C(I)!:C/)20i=(!)u::Q.CI):;:Q.CI):;:2-326. TEXAS-II}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54AS888, SN74AS8888·BIT- PROCESSOR SLICESQ.en-I:;C::>en">C::>Q.I->C::>;:;CI):l·sC0~V)20i=Eoiwa::::J(!)u::::enQ)00>Q)-0CJ)...JTEXAS -I.!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-327

SN54AS888, SN74AS8888·BIT PROCESSOR SLICESThe unsigned divide iterate start (UDIVIS) instruction begins the iterate procedure while testing for overflow.Overflow is reported when the first subtraction of the divisor from the MSH of the dividend produces carryout. The test detects quotient overflow and divide by zero.The unsigned divide iterate terminate (UDIVIT) instruction completes the iterate procedure generating thelast quotient bit.The signed divide initialize (SDIVIN) instruction prepares for iteration by shifting the dividend and storingthe sign of the dividend for use in the following instructions and overflow ,tests.The signed divide overflow test (SDIVO) checks for overflow possibilities. This instruction may be deletedfrom the divide operation if the OVR pin is ignored. If it is removed some overflow conditions will goundetected. WE must be high (writing inhibited) when this instruction is used.The signed divide iterate start (SDIVIS) instruction calculates the difference between the divisor and MSHof the dividend. Partial detection of overflow is also done during this instruction. Operations with like signs(positive quotient) and division by zero will overflow during this instruction (including zero divisor). Operationswith unlike signs are tested for overflow during the signed divide quotient fix instruction (SDIVOF). Partialoverflow results are saved and will be used during SDIVOF when overflow is reported.IIrC/)cCD

SN54AS888, SN74AS8888·BIT PROCESSOR SLICESSDIVI (SN-2 times)SDIVITDIVRFSDIVQFSportR portF portSportR portF portSportR portF port.SportR portF portResult of SDIVIS (or SDIVI)DivisorIntermediate resultResult of last SDIVIDivisorIntermediate resultResult of SDIVITDivisorRemainderMQ registerDivisorQuotientThe status of all signed divide instructions except SDIVIN, DIVRF, and SDIVQF is as follows:NOVRCn+SZForced to zeroForced to zeroCarry out equal to oneIntermediate result is zeroThe status of the SDIVIN instruction is as follows:NOVRCn+SZForced to zeroForced to zeroForced to zeroDivisor is zeroThe status of the DIVRF instruction is as follows:NOVRCn+SZForced to zeroForced to zeroCarry out equal to oneRemainder is zeroU)Q)(.)"SQ)c(IJ..JThe status of the SDIVQF instruction is as follows:NOVRCn +8ZSign of quotientDivide overflowCarry out equal to oneQuotient is zeroThe quotient is stored in the MQ register and the remainder is stored in the register file location that originallyheld the most significant word of the dividend. If fractions are divided, the quotient must be shifted rightone bit and the remainder right three bits to obtain the correct fractional representations.TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-329

SN54AS888, SN74AS8888·BIT PROCESSOR SLICESThe signed division algorithm is summarized in Table 7.TABLE 7. SIGNED DIVISION ALGORITHMOP CLOCK INPUT INPUTMNEMONICCODECYCLES SPORT R PORTE4 LOADMQ 1 Dividend (LSH) -80 SDIVIN 1 Dividend (MSH) DivisorAF SDIVO. 1 Remainder (N) Divisor90 SDIVIS 1 Remainder (N) DivisorAO SDIVI aN -2t Remainder (N) DivisorEO SDIVIT 1 Remainder (N) Divisor40 DIVRF 1 Remainder (Unfixed) Divisor50 SDIVQF 1 MQ Register DivisorOUTPUTF PORTDividend (LSH)Remainder (N)Test ResultRemainder (N)Remainder (N)Remainder (Unfixed)RemainderQuotientt N = Number of cascaded packages.unsigned divide usageThe instructions necessary to perform an algebraically correct division of unsigned numbers are as follows:Load MQ with the least significant half of the dividendr-enCCD~.(")CDt/)UDIVIS Sport MSH of dividendR port DivisorF port Intermediate resultUDIVI (SN-1 times) Sport Result of UDIVIS (OR UDIVI)R port DivisorF port Intermediate resultUDIVIT Sport Result of last UDIVIR port DivisorF port Remainder (unfixed)DIVRF Sport Result of UDIVITR port DivisorF port RemainderThe status of all unsigned divide instructions except UDIVIS is as follows:NOVRCn+SZForced ~o zeroForced to zeroCarry out equal to oneIntermediate result is zeroThe status of the UDIVIS instruction is as follows:NOVRCn+SZForced to zeroDivide overflowCarry out equal to oneIntermediate result is zeroIf fractions are divided, the remainder must be shifted right two bits to obtain the correct fractionalrepresentation. The quotient is correct as is. The quotient is stored in the MQ register at the completionof the divide.The unsigned division algorithm is summarized in Table S.2-330 TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54AS888, SN74AS8888-BIT PROCESSOR SLICESTABLE 8. UNSIGNED DIVISION ALGORITHMOP CLOCK INPUT INPUT OUTPUTMNEMONICCODE CYCLES SPORT R PORT F PORTE4 LOADMQ 1 Dividend ILSH) - Dividend ILSH)BO UDIVIS 1 Dividend IMSH) Divisor Remainder IN)CO UDIVI 8N-1 t Remainder IN) Divisor Remainder IN)FO UDIVIT 1 Remainder IN) Divisor Remainder IUnfixed)40 DIVRF 1 Remainder IUnfixed) Divisor Remaindert N = Number of cascaded packages.group 5 instructionsHex code F of Groupsummarized in Table 9.instructions is used to access Group 5 instructions. Group 5 instructions areTABLE 9. GROUP 5 INSTRUCTIONSINSTRUCTION BITS (17-10)OP CODE IHEX)MNEMONICFUNCTIONOF CLR Clear1F CLR Clear2F CLR Clear3F CLR Clear4F CLR Clear5F CLR Clear6F CLR Clear7F BCDBIN BCD to Binary8F EX3BC Excess-3 Byte Correction9F EX3C Excess-3 Word CorrectionAF SDIVO Signed Divide Overflow CheckBF CLR ClearCF CLR ClearOF BINEX3 Binary to Excess-3EF CLR ClearFF NOP No OperationC/)Q)CJ'SQ)c(J)...Jclear instructions (CLR)There are 11 clear instructions listed in Table 9. The instructions force the ALU output to be zero andthe BCD flip-flops to be cleared. The status set by the clear instruction is as follows:NOVRCn +8ZNone (force to zero)None (force to zero)None (force to zero)Active (one)no operation instruction (NOP): 17-10 = FF16This instruction is identical to the clear instructions except that the BCD flip-flops retain their old value.TEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-331

SN54AS888, SN74AS8888-BIT PROCESSOR SLICESexcess-3 correction instructions (EX3BC, EX3C)Two excess-3 correction instructions are available:1. Excess-3 byte correction (EX3BC): 17-10 = 8F162. Excess-3 word correction (EX3C): 17-10 = 9F16One instruction supports the byte mode and the other supports the word mode. These instructions correctthe excess-3 additions (subtractions) in either the byte or word mode. For correct excess-3 arithmetic,this instruction must follow each add/subtract. The operand must be on the Sport.NOTE: The previous arithmetic overflow should be ignored.The status of the EX3C instruction is as follows:NOVRCn +8ZMSB of resultSigned overflowCarry out equal oneNone (force to one)The status of the EX3BC instruction is as follows:renCCD

SN54AS888, SN74AS8888·BIT PROCESSOR SLICESThe following code illustrates the BCD to binary conversion technique.Let ACC be an accumulator registerLet NUM be the register which contains the BCD numberLet MSK be a mask registerM1:M2:M3:M4:M5:M6:L1:L2:L3:L4:M7:M8:LOADMO NUMSUB ACC, ACC, SLCMOSUB, MSK, MSK, SLCMOSLCMOSLCMOADDI ACC, MSK, 1510AND MO, MSK, R1, SLCMOADD, ACC, R1, R1, SLCMOBCDBIN, R1, R1, ACCBCDBIN, ACC, R1, ACCAND MO, MSK, R1ACC+R1 ..... ACC; LOAD MO WITH BCD NUMBER; CLEAR ACC AND ALIGN MO; CLEAR MSK AND ALIGN MO; ALIGN; ALIGN; MSK = 1510; REPEAT L 1 THRU L4; N - 1 TIMES (N = number of; BCD digits); EXTRACT ONE DIGIT; ALIGN MO; ACC + DIGIT; IS STORED IN R 1; ALIGN MO; 4 x (ACC + DIGIT); IS STORED IN ACC; ALIGN MO; 10 x (ACC + DIGIT); IS STORED IN ACC; ALIGN MO; FETCH LAST DIGIT; ADD IN LAST DIGITThe previous code generates a binary number by executing the standard conversion formula for a BCDnumber (shown for 32 bits!.ABCD = [(A x 10 + B) x 10 + C] x 10 + DNotice that the conversion begins with the most significant BCD digit and that the addition is performedin raqix 2.enQ)(,)'S;Q)cen..Jbinary to excess·3 instructions (BINEX3): 17·10 = DF16This instruction (Figure 11 )allows the user to convert an N-bit binary number to an N/4-bit excess-3 numbE?rrepresentation in 2N + 3 clocks. The data on the Rand S ports are summed with the MSB of the MO register.The MO register is simultaneously shifted left circularly. The status set by the binary to excess-3 instructionis as follows:NOVRCn +8ZMSB of resultSigned arithmetic overflowCarry out equal oneResult equal zeroTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-333

SN54AS888, SN74AS8888·BIT PROCESSOR SLICESr-enCena:«2C50f- M0 XwUI:Q :2:ciwa::J(!)u:::mMenenw(.)>< w0f->~a:«2C5~wa::J(!)u:::2-334TEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54AS888, SN74AS8888·BIT PROCESSOR SLICESThe following illustrates the binary to excess·3 conversion technique.Let NUM be a register containing an unsigned binary numberLet ACC be an accumulatorM1:M2:M3:L 1:L2:LOADMQ NUMCLEAR ACCSET1 ACC H/33/BINEX3 ACC, ACC, ACCEX3C ACC, ACC;'LOAD MQ WITH BINARY; NUMBER; CLEAR ACC; ACC -+ HEX/3333 .; DOUBLE ACC AND ADD IN; MSB OF MQ; ALIGN MQ; EXCESS 3 CORRECT; REPEAT L 1 AND L2; N-1 TIMESThe previous code generates an excess-3 number by executing the standard conversion formula for a binarynumber.an2n+an-12n-1 +an_22n-2+ ". a020 = [(2an+ an-1)2+an-212 + '" aoNotice that the conversion begins with the most significant binary bit and that the addition is performedin radix-10 (excess-3).decimal arithmeticDecimal numbers are represented in excess-3 code. Excess-3 code numbers may be generated by addingthree to each digit of a Binary Coded Decimal (BCD) number. The hardware necessary to implement excess-3arithmetic is only slightly different from binary arithmetic. Carries from one digit to another during additionin BCD occur when the sum of the two digits plus the carry-in is greater than or equal to ten. If both numbersare excess-3, the sum will be excess-6, which will produce the proper carries. Therefore, every additionor subtraction operation may use the binary adder. To convert the result from excess-6 to excess-3, onemust consider two cases resulting from a BCD digit add: (1) where a carry-out is produced, and (2) wherea carry-out is not produced. If a carry-out is not produced, three must be subtracted from the resultingdigit. If a carry is produced, the digit is correct as a BCD number. For example, if BCD 5 is added to BCD 6,the excess-3 result would be 8 + 9 = 1 (with a carry). A carry rolls the number through the illegal BCDrepresentations into a correct BCD representation. Binary 3 must be added to digit positions that producea carry-out to correct the result to an excess-3 representation. Every addition and subtraction instructionstores the carry generated from each 4-bit digit location for use by the excess-3 correction functions. Thesecorrection instructions (word or byte) must be executed in the clock cycle immediately after the additionor subtraction operation.Signed numbers may be represented in ten's complement form by complementing the excess-3 number.As an example, add the decimal number - 423 to the decimal number 24, which will be represented by8AA and 357 in excess-3, respectively.8AA357C01011934-6CC-399SumCarryExcess-3 correctComplementExcess-3 to decimalComplements of excess-3 numbers may be generated by subtracting the excess-3 number from an excess-3zero followed by an excess-3 correct.ElltnQ)(..)"S;Q)cen....ITEXAS -1!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-335

SN54AS888, SN74AS8888-BIT PROCESSOR SLICESIrencCD

SN54AS888, SN74AS8888-BIT PROCESSOR SLICESabsolute maximum rating over operating free-air temperature range (unless otherwise noted)Supply voltage, Vee1 ........................................................ 7 VSupply voltage, Vee2 ........................................................ 3 VInput voltage .............................................................. 7 VHigh-level voltage applied to 3-state outputs .................................... "5.5 VOperating case temperature range: SN54AS888. . . . . . . . . . . . . . . . . . . . . . . . .. - 55'De to 125 DeOperating free-air temperature range: SN74AS888, SN74AS888-1 ............... 0 De to 70 DeStorage temperature range ......................................... - 65 De to 150 Derecommended operating conditionsSN54AS888SN74AS888SN74AS888-1MIN NOM MAX MIN NOM MAXVCCl 1/0 supply voltage 4.5 5 5.5 4.5 5 5.5 VVCC2 STL internal logic supply voltage 1.9 2 2.1 1.9 2 2.1 VVIH High-level input voltage 2 2 VVIL Low-level input voltage 0.8 0.8 V10H High-level output current -1 -2.6 mAI All output except G and ZERO 8 810L Low-level output current IG 16 16I ZERO 48 48mATC Operating case temperature -55 125TA Operating free-air temperature 0 70°celectrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)PARAMETERVIK VCClVOHAll outputsexcept ZEROTEST CONDITIONSSN54AS888MIN Typt MAXSN74AS888SN74AS888-1MIN Typt MAX~ 4.5 V, II ~ -18 mA -1.2 -1.2 VVCCl = 4.5 V to 5.5 V, 10H ~ -0.4 mA VCC- 2 VCC-2VCClVeCl~ 4.5 V, 10H ~ -1 mA 2.4 V~ 4.5 V, 10H ~ -2.6 mA 2.410H ZERO VCCl ~ 4.5 V, VOH ~ 5.5 V 0.1 0.1 mAAll outputsVCCl ~ 4.5 V, 10L ~ 8 mA 0.5 0.5except G and ZEROVOLVG VCCl ~ 4.5 V, 10L ~ 16 mA 0.5 0.5ZERO VCCl ~ 4.5 V, 10L ~ 48 mA 0.5 0.5II1/0 VCCl ~ 5.5 V, VI ~ 5.5 V 0.1 0.1All others VCCl ~ 5.5 V, VI ~ 7 V 0.1 0.1mAIIHt VCCl = 5.5 V, VI = 2.7 V 20 20 I'AIlL t VCCl = 5.5 V, VI = 0.5 V -0.4 -0.4 mAlOS VCCl = 5.5 V, Vo = 2.25 V -30 -112 -30 -112 mAICCl VCCl = 5.5 V 150 130 mAICC2 VCC2 = 2.1 V 410 390 mAt All typical values are at VCC = 5 V, T A = 25°C.tFor 1/0 ports, the parameters IIH and IlL include the off-state current.§The output conditions have been chosen to produce a current that closely approximates one-half the true short-circuit current, lOS.UNITUNITIItnQ)(J0>Q)o(J)...ITEXAS -1.11INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-337

SN54AS888, SN74AS8888-BIT PROCESSOR SLICESSN54AS888 maximum switching characteristics, Vee(see Note 1)4.5 V to 5.5 V, TeIt load resistor R 1 = 100 n.cPARAMETERtpdFROM(INPUT)A3-AOB3-BODA7-DAO,DB7-DBOCnEAEB17-10OEBOEYQIO (n)Shift·SIO (n)ShiftCKOEASSFtY Cn +8 G,P62 42 4847 28 2825 14 -54 32 3554 32 3558 32 32- - -14 - -15 - -15 - -68 60 56- - -- - -t For byte instructions only.NOTE 1: -load circuit and voltage waveforms are shown in Section 1.TO (OUTPUT) •zt N OVR DA DB69 62 60 18 1858 50 42 - -32 24 18 - -62 52 52 - -62 52 52 - -62 52 41 - -- - - - 14- - - - -24 - - - -24 22 - - -62 50 68 38 38- - - 14 -- - 14 - -~ SN74AS888 maximum switching characteristics, Vee 4.5 V to 5.5 V, TA(i' Note 1)CDenFROMTO (OUTPUT)PARAMETERtpdA3-AOB3-BO(INPUT)DA7-DAO,DB7-DBOCnEAEB17-10OEBOEYQIO (n)ShiftSIO (n)ShiftCKOEASSFtY Cn +854 3644 2625 849 2949 2955 30- -12 -15 -15 -58 55- -- -G, P zt N OVR42 60 52 5026 52 46 38- 32 24 1829 58 49 4729 58 49 4730 60 49 39- - - -- - - -- 24 - -- 24 19 -52 61 52 62- - - -- - - 12DADB18 18- -- -- -- -- -- 12- -- -- -35 3512 -- -UNITQIO 51065 6650 5032 3258 5858 5858 58- - ns- -- -- -70 70- -- -UNITQIO SIO58 5844 4431 3154 5454 5454 54- - ns- -- -- -60 60- -- -t load resistor R 1 = 100 n.t For byte instructions only_NOTE 1: load circuit and voltage waveforms are shown in Section 1.2-338 TEXAS -1.!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54ASBBB, SN74ASBBBB·BIT PROCESSOR SLICESSN74AS888-1 maximum switching characteristics, Vee = 4.5 V to 5.5 V, TA = 0 °e to 70 °e (seeNote 1)PARAMETERtpdFROM(INPUT)A3-AOB3-BODA7-DAO,DB7-DBOC nEAEB17-10DEBDEY010 (n)Shift510 (n)ShiftCKDEASSF~Y Cn +8 G, P44 30 3636 24 2422 8 -40 25 2540 25 2546 27 27- - -12 - -14 - -14 - -50 46 46- - -- - -t Load resistor R 1 = 100 fl.~ For byte instructions only.NOTE 1: Load circuit and voltage waveforms are shown in Section 1.register file write setup and hold timestsuthPARAMETERC3-CODB§17-1413-10OEYY7-YOWEOIO(n), SIO(n)SELYC3-CODB§17-1413-10OEYY7-YOWEOIO(n), SIO(n)SELYTO (OUTPUT)zt N OVR DA DB QIO SIO50 44 44 17 17 48 4846 41 32 - - 40 40UNIT27 21 16 - - 25 2549 41 41 - - 44 4449 41 41 - - 44 4450 42 35 - - 45 45- - - - 12 - - ns- - - - - - -20 - - - - - -20 18 - - - - -50 50 50 30 30 50 50- - - 12 - - -- - 12 -- - - -SN54AS888 SN74AS888 SN74AS888-1MIN MAX MIN MAX MIN MAXUNIT8 7 614 12 1116 14 1324 22 214 3 3 ns2 2 28 6 66 5 58 6 60 0 00 0 00 0 00 0 06 5 5 ns10 10 103 2 20 0 08 6 6•enQ)(.)"SQ)ctJ)..J§ DB (during select instruction) through Y port.TEXAS -I.!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-339

SN54AS888, SN74AS8888-BIT PROCESSOR SLICESspecial instruction switching characteristicsDuring various special instructions, the SSF pin is used to pass required information between the' AS888packages which make up a total system.For instance, during the multiplication process, the LSB of the multiplier determines whether an ADD/SHIFTor SHIFT operation is performed. During multiplication, the SSF pin of the least significant package (LSP)becomes an output pin while all other packages become input pins.Similarly, during normalization, the required operation depends on whether the two data MSBs are thesame or different. Therefore, during normalization the SSF pin of the most significant package (MSP)becomes an output pin while all other packages become input pins.Tables 10, 11, and 12 list the instructions which force the SSF pin during their execution. The propagationdelay from various inputs is also shown. The parameter which limits normal system performance is indicatedby a dagger.TABLE 10. SN54AS888 SSF PIN DELAYS AND SETUP TIMESIrencCD

SN54AS888, SN74AS8888·BIT PROCESSOR SLICESTABLE 11. SN74AS888 SSF PIN DELAYS AND SETUP TIMESMNEMONICHEX SSF SOURCE INPUT - SSF (ns)CODE LSP MSP Cn I(n) CKCRC 00 X - 26 52SNORM 20 X - 26 1 40DNORM 30 X - 26 52DIVRF 40 X - 26 T 40SDIVQF 50 X - 25 1 -SMUll 60 X - 25 1 40SDIVIN 80 X - 38 60SDIVIS 90 X 241 48 60SDIVI AO X 241 48 60UDIVIS 80 X 17 1 43 60UDIVI CO X 17 1 44 52UMULI DO X - 26 T 40SDIVIT EO X 25 T 46 52ABX 48 X - 32 60SMTC 58 X - 26 52BINEX3 DF X - 26 1 40LOADMQ (Arith) X 221 32 50LOADMQ (Log) X - 32 50BADD 88171 52 55BSUBS 98 i171 52 55SOURCEBSUBRA8 17 1 52 62ISBINCS B8 171 52 55MOSTBINCNS C8 17 1 52 62SIGNIFICANTBXOR D8 - 52 -BYTEBAND E8 - 52 -SELECTEDBORF8- 52 -EX3BC 8F - 45 45+t This ~arameter limits normal system performance.B(n)371-37 1---40152524537-41J3838 1-383814646464646---461SSF SETUPTIME (ns)17171717170000000017171700---------IIenCl)(J'S;Cl)CtJ)...JTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652·341

SN54AS888, SN74AS8888-BIT PROCESSOR SLICESTABLE 12. SN74AS888-1 SSF PIN DELAYS AND SETUP TIMESrencCD

SN54AS890, SN74AS890MICROSEOUENCERS02662. NOVEMBER 1982-REVISED APRIL 1985• 14 Bits Wide - Addresses up to 16.384Words of Microcode with One Chip• Selects Address from One of Eight Sources• STL-AS Technology• Independent Read Pointer for Aid inMicrocode Diagnostics• Supports Real-Time Interrupts• Two Independent Loop CountersoSupports 64 Powerful Instructions• Dependable Texas Instruments Quality andReliabilitydescriptionThe' AS890 is a powerful microsequencer thatis the result of the implementation of Tl'sAdvanced Schottky and Schottky TransistorLogic. Approximately 2400 Schottky gateequivalents are used to construct this highperformancesequencer. The 'AS890 cangenerate an address and provide register statusin only 29 ns while typically requiring only 1.8watts of power. All internal STL logic in thesedevices operates on a 2-volt power supply thatmust be supplied externally. The informationgenerated by the internal STL logic iscommunicated in the rest of the system via5-volt Advanced Schottky TTL-compatible 1/0ports.. The microsequencers select a 14-bitmicroaddress from one of eight sources toprovide the proper microinstruction sequence forbit-slice processor or other microcode basedsystems. These high-performance devices arecapable of addressing 16,384 control storememory locations either sequentially or viaconditional branching algorithms. This multiwaybranching capability, coupled with a nine-worddeep FILO (first in, last out) stack. allows themicroprogrammer to arrange his code in blocksso that microprograms may be structured in thesame fashion as such high-level languages asALGOL, Pascal, or Ada.Both polled and real-time interrupt routines aresupported by the' AS890 to enhance systemthroughput capability. Vectored interrupts mayoccur during any instruction, including PUSHesand POPs.NO.A2A·3A·4k5A6A7k8A·9A·1OB IB·2B3B4B·5B6B·7B·8SN74AS890 ... GB PACKAGE(TOP VIEW)INDEXSYM80 L1 2 3 4 5 6 7 8 9APINNAMEDRBIODRB9DRB8DRB7DRB6ORB5DRB4DRB3DRBIDRBI3iNTDRBI2DRBIIB3RBOEDRB2DRBO80OSElMUXOMUXIMUX2RCORC1RC2SO51S2ccVCC1VCC2CKZEROSTKWRN/RER• • .. • • • • • •8• @ • ·• • · • •C• •D· ·E• •F• •G•H• J• ·•K• @ • • • • • •l• • • ·• • •AS890tPINPINNO. NAME NO. NAMEB9 5TKWRN/RER F·IO VCCIZERO F-11 MUX2BII CK G·I Y5C-I YI3 G·2 YOEC2 YIO G 10 RCICIO cc G·II MUXIC·II 51 H·I Y40·1 YI2 H·2 Y60·2 Y9 H·IO BO010 52 MUXO50 JI Y3E·I Y11 J2 Y2E·2 YB J·IO RC2E·IO VCC2 J·II 05ELEll RCO K·I YIF·I Y7 K·2 YOF2 GND K 3 BI1011SN54AS890 ... FD PACKAGESN74AS890 ... FN PACKAGE(TOP VIEW)12131415161718192021222324·@10 11• •• •• •• •• •• •• •@•·9 8 765432 1 6867 666564636261•PINNO NAMEK·4 DRA13K·6 DRA8K 7 DRA7K 8 ORADK 9 ORAlKID DRA3K·II DRA2L·2 B2L3 INCDRAI2L5 DRAIOL6 DRA9L·7 RAciEL8 DRA6L·9 DRA5LIO DRA4252627 28 29 30 31 3232 34 35 36 37 38 394041 42 43a .- N M .q- LO co ILU r-... co 0'> 0 ...- N Mlf- C")rnrommmrornoromrn...-...-...-...-zro~~ocococ~ocroocococroromro-00000000::0000::0::0:0::000060~ 8259[ YO58~ Y157[ Y256[ Y355 Y454 Y553 Y652 YOE51 GND50 Y749 Y848 Y947 Y1046 Y1145 Y1244 Y13EllCJ)Cl)Co)0$Q)Cen...JPRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments~~~~~:~~i~ai~~1~7~ ~!~~~~tigt" !i;o~:~:~it:r~~s notTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1982. Texas Instruments Incorporated'2-343

SN54AS890, SN74AS890MICROSEOUENCERSfunctional block diagramRACE C>-----{YOSEL C>----.,renCCD

SN54AS890, SN74AS890MICROSEOUENCERSpin descriptionsPIN NAMEI/OPIN FUNCTIONRAOEDRA6-DRAOOSELMUX2-MUXORC2-RCOS2·S0CCVCC1VCC2CKZEROSTKWRN/RERDRB6-DRBORBOEDRB13·DRB7INTV13-V8GNDV7VOEV6-VOINCDRA13-DRA7B3-BOInIn/OutInInInInInInOutOutIn/OutInIn/OutInIn/OutIn/OutInIn/OutInIn/OutInEnables DRA output. active lowSeven LSBs of the A direct data I/O portMUX control for the source to DRA. Low selects RA.high selects stack.MUX control for V output bus (see Table 1)Register/counter controls (see Table 3)Stack control (see Table 2)Condition code5-volt supply for TTL compatible I/O2-volt supply for internal STLClockZero detect flag for register A and BStack overflow. underflow/read error flagSeven LSBs of the B direct data I/O port (0 = LSB)Enables DRB output. active lowSeven MSBs of the B direct data I/O portActive low selects INT RT register to stackSix MSBs of bidirectional V portGroundSeventh bit of bidirectional V portEnables V output bus. active lowSeven LSBs of bidirectional V port (0 = LSB)Incrementer controlSeven MSBs of direct B data I/O port1 6-way branch inputs onIIdescription (continued)Two 14-bit load able registers/counters may be used for temporary storage of data or utilized as downcounters for repetitive instructions such as multiplication and division or as loop counters when iterativeroutines are required.An additional feature is a 24-bit port that appends four user-definable bits to the ORA or ORB addressvalue for support of 16-way branches for the execution of relative branch addressing schemes.Y output multiplexerThe Y output multiplexer of the' AS890 is capable of selecting the next branch address from one of eightlocations. Addresses may be sourced from:1. The top of the 14-bit by 9-word address stack2. An external input on the ORA port, potentially a pipeline register3. An external input on the ORB port, potentially a pipeline register4. Internal register/counter. A5. Internal register/counter B6. An internal microprogram counter (MPC register)7. An external input onto the bidirectional Y output port8. A 16-way branch-4 bits appended to ORA, ORB, register/counter A or register/counter B.TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-345

SN54AS890, SN74AS890MICROSEOUENCERSThe source of the next address is dependent upon the previous state of the microsequencer, the MUXcontrols (MUX2-MUXO), the condition code (CC) input, and the state of an internal status flag (statusexternally available at the ZERO output) that indicates that one of the on-chip registers is being decrementedto zero.The entire instruction set may be made conditional by manipulation of the condition code (CC) input.Allowing the CC value to vary as a result of data or status provides for state-dependent or data-dependentbranching. Unconditional branches may be achieved by forcing CC high when selecting control storeaddresses. Holding this pin low will provide for conditional or unconditional branches as dictated by thestate of the zero-detect flag. The required control signals for selection of the Y output source are listedin Table 1. Note that the dependence of the' AS890 on two variables for conditional branches and jumpsallows a conditional branch or conditional jump to subroutine in any clock cycle. Also note that all multiplexerinputs are overridden when all of the stack control inputs are pulled low. This instruction resets the stackand read pointers to zero and places all lines of the Y output bus at the low level.TABLE 1. Y OUTPUT CONTROLIrencCD

SN54AS890, SN74AS890MICROSEUUENCERS14-bit by 9-word address stackThe positive-edge-triggered 14-bit address stack supplies on-board storage of nine control store addressesthat support up to nine nested levels of m~crosubroutine, looping, and real-time interrupt functions. Thestack pointer (SP), which operates as an up-down counter, is updated after the execution of each PUSHoperation and before each POP. In a PUSH operation, the address stored in the MPC register is loadedinto the stack location addressed by the stack pointer, and the stack pointer is incremented. This addressis available at the ORA port by enabling ORA (RAOE low and OSEL high).A POP operation causes the stack pointer to be decremented on the first rising clock edge following thearrival of the POP instruction at the S2-S0 pins. The value that was indexed by the stack pointer is effectivelyremoved from the top of the stack. All PUSH and POP instructions are conditionally dependent upon thestack control inputs (S2-S0)' the condition code (CC), the input value, and the zero-detect status. Thedesired option may be selected using the stack control inputs listed in Table 2.STACK CONTROLTABLE 2. STACK CONTROLSTACK OPERATION. CC = LS2 51 50 05EL ZERO = L ZERO = H CC = HL L L X RESET /CLEAR RESET/CLEAR RESET/CLEARL L H X CLEAR SP. RP HOLD HOLDL H L X HOLD POP POPL H H X POP HOLD HOLDH L L X HOLD PUSH PUSHH L H X PUSH HOLD HOLDH H L X PUSH HOLD PUSHH H H H READ READ READH H H L HOLD HOLD HOLDThe read pointer (RP) is a useful tool in debugging microcoded systems. A microprogrammer now has theability to perform a nondestructive, sequential read of the stack contents from the ORA port. This capabilityprovides the user with a method of backtracking through the address sequence to determine the causeof overflow without affecting program flow, the status of the stack-pointer or the internal data of the stack.Placing a high value on all of the stack inputs (S2-S0) and OSEL places the' AS890 into the. read mode.At each low-to-high clock transition, the value pointed to by the read pointer is available at the ORA portand the read pointer is decremented. Microcode diagnostics are simplified by the ability of the 'AS890to sequentially dump the contents of its stack. The bottom of the stack is detected by monitoring theSTKWRN/RER (stack warning/read error) pin. A high will appear when the stack contains one word anda READ instruction is applied to the S2-S0 pins. This signifies that the last address has been read. Thestack pointer and stack contents are uneffected by the READ operation. Under normal PUSH and POPoperations the read pointer is updated with the stack pointer and contains identical information.The STKWRN/RER pin alerts the system to a potential stack overflow or underflow condition. STKWRN/RERbecomes active under two additional conditions. If seven of the nine. stack locations (0-8) are full (thestack pointer is at 7) and a PUSH occurs, the STKWRN/RER pin will produce a high-level signal to warnthat the stack is approaching its capacity, and will be full after one more PUSH. Knowledge that overflowpotential exists allows bit-slice-based systems to continuously process real-time interrupt vectors. Thissignal will remain high, if HOLD, PUSH, or POP instructions occur, until the stack pointer is decrementedto 7.The user may be protected from attempting to POP an empty stack by monitoring STKWRN/RER beforePOP operations. A high level at this pin signifies that the last address has been removed from the stack(SP = 0). This condition remains until an address is pushed onto the stack and the stack pointer isincremented to one.Clearing the stack and read pointer is accomplished by placing low levels onto the stack control lines (S2-S0).This function overrides all of the Y output MUX controls and places the Y bus into a low state.fIenQ)CJ0>Q)cen..JTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-347

SN54AS890, SN74AS890MICROSEOUENCERSIIrOOCCD

SN54AS890, SN74AS890MICROSED.UENCERScontrol inputs3. At the following clock edge, the second microaddress is stored in the MPC and the interruptedaddress will be stored in the INT RT register which always contains the outgoing value on the Ybus. This edge also causes the processor to begin execution of the first instruction of the interruptroutine. This first instruction must PUSH the address stored in the INT RT register onto the stackso that the proper return linkage is maintained. This is accomplished by making INT low andperforming a PUSH. If this instruction were to be interrupted, the process would be repeated andthe proper return linkage preserved.A listing ot the response of internal elements to various control inputs is given in Table 4.TABLE 4. RESPONSE TO CONTROL INPUTSPIN NAMEHIGHLOGIC LEVELRAOE ORA output in high-Z state ORA output is activeRBOE ORB output in high-Z state ORB output is activeYOE Y output in high-Z state Y output is activeINT MPC to stack INT RT register to stack05EL Stack to ORA buffer input RA to ORA buffer inputINC Adds one to Y output and stores in MPC Passes Y output to MPC unalteredMUX2-MUXO Table 1 Table 1instruction set52-SO Table 2 Table 2RC2-RCO Table 3 Table 3Sixty-four microsequencing instructions enable the' AS890 to generate micro-addresses for up to 16.384locations. Any instruction can be made conditional depending upon the value of the externally appliedcondition code (CC) and the value stored in either of the internal register/counters.The required signals tor selection of the Y output source were listed in Table 1. Suggested methods forimplementing a few commonly used instructions are given in Table 5 and flowcharts showing executionexamples are illustrated in Figure 1.It should be noted that the term jump refers to a subroutine call that must be accompanied by a returninstruction. The term branch implies that a deviation from the program flow is accomplished but no returnis required.LOWenQ).~>Q)oen..JTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-349

SN54AS890, SN74AS890MICROSEOUENCERSTABLE 5. SUGGESTED CODING FOR REPRESENTATIVE INSTRUCTIONSrCJ)cCD

SN54AS890, SN74AS890MICROSEOUENCERS(a) CONTINUE(CC FORCED)(b) UNCONDITIONAL BRANCH(CC FORCED)CJ)Q)(.)oS;cQ)en...J(e) CONDITIONAL BRANCH(DEC DISABLED)(d) THREE·WAY BRANCH (DEC ENABLED)'NOTE 1: CC and ZERO are completed in the same clock cycle.FIGURE 1. INSTRUCTION SET FLOWCHARTSTEXAS -1!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-351

SN54AS890, SN74AS890MICROSEOUENCERSr--III IIIIIII LL ______.JIIf) REPEAT ICC FORCED. DEC DISABLED)1rrJ)cCD

SN54AS890, SN74AS890MICROSEOUENCERS(j) JUMP TO SUBROUTINEICC FORCED)iii TWO-WAY JUMP TO SUBROUTINEIDEC DISABLED)tJ)Q)ooSQ)cen..JIk) REPEAT UNTILIDEC DISABLED)(I) RETURN FROM SUBROUTINEICC FORCED, DEC DISABLED)FIGURE 1. INSTRUCTION SET FLOWCHARTS (continued)TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-353

SN54AS890, SN74AS890MICROSEOUENCERSrrncCD

SN54AS890, SN74AS890MICROSEOUENCERS(q) PUSH AND CONTINUE(CC FORCED)(r) POP AND CONTINUE(CC FORCED)III(J)Q)(.)"SQ)cen..J(t) RESET AND CLEAR(5) EXIT FROM LOOP(DEC ENABLED) 1NOTE 1: CC and ZERO are completed in the same clock cycle.FIGURE 1. INSTRUCTION SET FLOWCHARTS (continued)TEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-355

SN54AS890, SN74AS890MICROSEOUENCERSlEIrenoen

SN54ASB90, SN74ASB90MICROSEOUENCERSabsolute maximum ratings over operating temperature range (unless otherwise noted)Supply voltage, Vee1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VSupply voltage, Vee2 ...................................................... " 3 VInput voltage: All inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VI/O ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VOperating case temperature range, SN54AS890 ........................ " - 55°C to 125 °eOperating free-air temperature range, SN74AS890 ........................... ooe to 70 0 eStorage temperature range ......................................... - 65°C to 150 0 erecommended operating conditionsSN54AS890SN74AS890MIN NOM MAX MIN NOM MAXVCC1 I/O supply voltage 4.5 5 5.5 4.5 5 5.5 VVCC2 STL internal logic supplyvoltage 1.9 2 2.1 1.9 2 2.1 VVIH High-level input voltage 2 2 VVIL Low·level input voltge 0.8 0.8 V10H High·level output current -1 -2.6 mAI All outputs8 8IOL Low·level output current except Y13·YO mAI Y13·YO 12 12TC Operating case temperature - 55 125 °cTA Operating free air temperature 0 70 °celectrical characteristics over recommended operating temperature range (unless otherwise noted)PARAMETERTEST CONDITIONSSN54AS890SN74AS890MIN Typt MAX MIN Typt MAXVIK VCC1 = 4.5 V, II = -18 mA -1.2 -1.2 V·VCC1 = 4.5 V to 5.5 V. 10H = -0.4 mA VCC-2 VCC-2VOH VCC1 = 4.5 V. 10H = -1 mA 2.4 3.4 VVCC1 = 4.5 V, 10H = -2.6 mA 2.4VOLAll outputsexcept Y13·YOVCC1 = 4.5 V. 10L = 8 mA 0.5 0.5VY13·YO VCC1 = 4.5 V. 10L = 12 mA 0.5 0.5IIIIHInputs VCC1 -- 5.5 V. VI =7V 0.1 0.1I/O ports VCC1 = .5.5 V. VI = 5.5 V 0.1 0.1Inputs 20 20I/O ports i VCC1 = 5.5 V. VI = 2.7 V JlA40 40IlL i VCC1 = 5.5 V. VI = 0.4 V -0.4 -0.4 mAlOS VCC1 ~ 5.5 V. Vo = 2.25 V -30 -112 -30 -112 mAICC1 VCC1 = 5.5 V 185 178 mAICC2 VCC2 = 2.1 V 420 400 mAUNITUNITmAEll(J)Q)(.)oS;cQ)en..Jt All typical values are at VCC = 5 V. T A = 25°C.iFor 1/0 ports. the parameters IIH and IlL include output current 10ZL and 10ZL. respectively.§The output conditions have been chosen to produce a current that closely approximates one· half of the true short·circuit current. lOS.TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-357

SN54AS890MICROSEOUENCERSSN54AS890 maximum switching characteristics: VCC1TC = 55°C to 125°C (see Note 2)4.5 V to 5.5 V. VCC21.9Vt02.1 V.PARAMETERtpdFROMTO (OUTPUT)(INPUT) V ZERO DRA DRBCC 32CKDRA13-DRAO 16DRB13-DRBO 16MUX2-MUXO 36RC2-RCO 32 14S2-S0 32B2-BO 2232 30 3053 t 42tOSEL 24VOE 16ten RAOE 16RBOE 16iii t O""m,";o, R";"",C,"o',, A " B 'od "0,;0, , "'0YOE 16tdis RAOE 16RBOE 16r- NOTE 2: Load circuit and voltage waveforms are shown in Section 1enSN54AS890 setup and hold timesPARAMETERFROMTO (DESTINATION)MINCC Stack 10DRA13-DRAO RCA, INT RT 5DRB13-DRBO RCB, INT RT 5INC MPC 10INT Stack 10Stack 16tsu RC2-RCO RCA, RCB 10S2-S0INT RT 14Stack 10INT RT 10MUX2-MUXO INT RT 14B3-BO INT RT 14Y13-YO MPC 12th Any Input Any Destination 2SN54AS890 minimum clock requirements (see Note 3)PARAMETERtwL(CK) Pulse duration, clock low 10twH(CK) Pulse duration, clock high 20tc(CK)Clock cycle timeMIN55 t45STKWRN30MAXMAXUNITnsnsnsUNITnsUNITnstDecrementing Register/Counter A or B and sensing a zero.NOTE 3: The total clock period of clock high and clock low must not be less than clock cycle time. The minimum pulse durations specifiedare only for clock high or clock low, but not for both simultaneously.2-358 TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN74AS090MICROSEDUENCERSSN74AS890 maximum switching characteristics: VCC1TA = OOC to 70°C (see Note 2)4.5 V to 5.5 V, VCC2 1.9 V to 2.1 V,PARAMETERtpdFROMTO (OUTPUT)(INPUT) y ZERO ORA ORB STKWRNCC 29CKDRA13-DRAO 15DRB13-DRBO 15MUX2-MUXO 35RC2-RCO 30 1352-SO 28B2-BO 2029 29 29 2950 t 39 tOSEL 18YOE 15ten RAOE 15 nsRBOE 15YOE 16tdis RAOE 16 ns'i'i"B'ITi: 16t Decrementing Register/Counter A or B and sensing a zero.NOTE 2: Load circuit and voltage waveforms are shown in Section 1.SN74AS890 setup and hold timesUNITnsEllFROMPARAMETER TO (DESTINATION) MIN MAX UNITCC Stack 10DRA13-DRAO RCA. INT RT 5DRB13-DRBO RCB. INT RT 5INC MPC 10INT Stack 10Stack 14tsu RC2-RCO RCA. RCB 10INT RT 1252-SO Any Destination 10MUX2-MUXO INT RT 12B3-BO INT RT 14Y13-YO MPC 10th Any Input Any Destination 2SN74AS890 minimum clock requirements (see Note 3)PARAMETER MIN MAX UNITtwL(CK) Pulse duration. clock low 10twH(CK) Pulse duration. clock high 20tc(CKIClock cycle timens50 l nstDecrementing Register/Counter A or B and sensing a zero.NOTE 3: The total clock period of clock high and clock low must not be less than clock cycle time. The minimum pulse durations specifiedare only for clock high or clock low. but not for both simultaneously.36TEXAS "'J}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-359

SN74Asa90·1MICROSEOUENCERSSN74AS890-1 maximum switching characteristics: VCC1.TA = OOC to 70°C (see Note 2)4.5 V to 5.5 V, VCC21.9 V to 2. 1 V,lEIrCJ)CCD~.oCD(J)PARAMETERFROMTO (OUTPUT)(INPUT) Y ZERO ORA ORBCC 25CK25 25 2542t 34 tORA13-DRAO 14DRB13-DRBO 14MUX2-MUXO 31tpdRC2-RCO 26 1252-SO 25B2-BO 19OSEL 17VOE 15ten RAOE 15RBOE 15VOE 16tdis RAOE 16RBOE 16t Decrementing Register/Counter A or B and sensing a zero.NOTE 2: Load circuit and voltage waveforms are shown in Section 1.SN74AS890-1 setup and hold timesPARAMETERFROMTO (OESTINA TION)MINCC Stack 10DRA13-DRAO RCA, INT RT 5DRB13-DRBO RCB, INT RT 5INC MPC 10INT Stack 10Stack 14tsu RC2-RCO RCA, RCB 10INT RT 1252-SO Any Destination 10MUX2-MUXO INT RT 12B3-BO INT RT 14Y13-YO MPC 10th Any Input Any Destination 2SN74AS890-1 minimum clock requirements (see Note 3)PARAMETERMINtwL(CK) Pulse duration, clock low 10twH(CK) Pulse duration, clock high 2042ttc(CK) Clock· cycle time34STKWRN25MAXMAXUNITnsnsnsUNITnsUNITnstDecrementing Register/Counter A or B and sensing a ·zero.NOTE 3: The total clock period of clock high and clock low must not be less than clock cycle time. The minimum pulse durations specifiedare only for clock high or clock low, but not for both simultaneously.2-360 TEXAS -1!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN74AS095O·BIT MEMORY ADDRESS GENERATORSSN54AS095, STL-AS Technology• • •• •••Select FunctionsParallel 8-Bit ALU with Expansion Inputsand Outputs13 Arithmetic and Logic Functions8 Conditional Shifts (Single and DoubleLength)9 Instructions that Manipulate Bytes4 Instructions that Manipulate BitsAdd and Subtract Immediate InstructionsAbsolute Value InstructionSigned Magnitude to/from Two'sComplement ConversionSingle- and Double-Length Normalizeo Signed and Unsigned Divides with OverflowDetection; Input does not Need to bePrescaled• Signed, Mixed, and Unsigned Multiplies• Three-Operand, 16-Word Register File• Full Carry Look Ahead SupportdescriptionNOVEMBER 1985-REVISED APRIL 1986• Sign, Carry Out, Overflow, and Zero-DetectStatus Capabilities• Excess-3 BCD Arithmetic• MQ Register is Externally Available throughthe DB Port• Internal Shift Multiplexers that Eliminate theNeed for External Shift Control Parts• ALU' Bypass Path to Increase Speeds ofMultiply, Divide, and Normalize Instructionsand to Provide New Instructions such as BitSet, Bit Reset, Bit Test, Byte Subtract, ByteAdd, and Byte Logical• 3-0perand Register Files to Allow anOperation and a Move Instruction to beCombined• Byte Select Controlled by External 3-StateBuffers that may be Eliminated if Bit andByte Manipulation are not Needed• Bit and Byte Masks that are Shared withRegister Address Fields to Minimize ControlStore Word Widtho 3 Data Input/Output Paths to MaximizeData ThroughputThese 8-bit Advanced Schottky TTL integrated circuits are designed to implement high performance digitalcomputers or controllers. An architecture and instruction set has been chosen that'supports a fast systemclock, a narrow micro-code word width, and a high system throughput. The powerful instruction set allowshigh-speed system architecture to be implemented and also allows an existing system's performance tobe upgraded while protecting software investments. These processors are designed to be cascadable toany word width 16 bits or greater.The only difference between the' AS888 Bit-Slice Processor and the' AS895 Memory Address Generatorsis the function of the DB port. The 'AS888 DB port outputs the register file. The 'AS895 DB port canbe used to read the MQ register result during the same clock cycle that the ALU result is available at theY port.The SN54AS895 is characterized for operation over the full military temperature range of - 55°C to 125°C.The SN74AS895 and SN74AS895-1 are characterized for operation from O°C to 70°C.Package options include both plastic and ceramic chip carriers in addition to a 68-pin grid array ceramicpackage.enQ)UoS;Q)CCJ);...IPRODUCTION DATA documents contain information,current as of publication date. Products conform tospecifications per the terms of Texas Instrumentsstandard warranty. Production processing does notnecessarily include testing of an parameters.TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1985, Texas Instruments Incorporated2-361

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSIr-encCD

SN54AS095, SN74AS095O·BIT MEMORY ADDRESS GENERATORSPIN GRID CHIPNAMEARRAY CARRIERA-10 28 PPPB·7 29 SSFA·9 30 ZEROA-8 31 P/OVRA-7 32 GINA-6 33 Cn +8I/OII/O1/0000DESCRIPTIONPackage position pin. Tri·level input used to define package significance duringinstruction execution. Leave open for intermediate positions, tie to VCC for mostsignificant package, and tie to GND for least significant package.Special shift function. Used to transfer required information between packages duringspecial instruction execution.Device zero detection, open collector. Input during certain special instructions.ALU propagate/instruction overflow for most significant package, low active.ALU generate/negative result for most significant package, low active.ALU ripple carry output.B-6 34 5107A-5 35 0107A-4 36 0100A-3 37 5100A-2 38 C n1/0I/O1/01/0IBidirectional shift pin, low "ctive.ALU carry input.B-4 39 10B-3 40 11B-1 41 12B-2 42 13B-5 43 14C-1 44 15D-1 45 16E-1 46 17C-2 47 VCC2D-2 48 VCC1E-2 49 OEAF-1 50 EAF-2 51 GNDG-2 52 DAOH-2 53 DA1G-1 54 DA2H-1 55 DA3J-1 56 DA4J-2 57 DA5K-1 58 DA6K-2 59 DA7L-2 60 CKK-3 61 COL·3 62 C1KA 63 C2L-4 64 C3K-5 65 AOL-5 66 A1L·6 67 A2K·6 68 A3IIIIIIIIIII/OI/O1/0I/OI/O1/01/0I/OIIIIIIIIIInstruction input.Low voltage power supply (2 V).1/0 interface supply voltage (5 V).DA bus enable, low active.ALU input operand select. High state selects external DA bus and low state selectsregister file.Ground pin.A port data bus. Outputs register file data (EA = 0) or inputs external data (EA = 1).Clocks all synchronous registers on positive edge ..Register file write address select.Register file A port read address select.C/)Q)CJ'SQ)cCJ)..JTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-363

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSrencCD

SN54AS095, SN74AS095O·BIT MEMORY ADDRESS GENERATORSfunctional block diagram4C3-COA3-AO416X8REGISTER FILE4WECKB3-BOOEB8OA7-DAO ~~+--+-...... ---....,8DB7-DBOEBOEB1P/OVR

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSlEIrCACCD

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSMQ registerY busstatusThe multiplier-quotient (MO) register has specific functions in multiplication, division, and normalization.This register may also be used as a temporary storage register. The MO f€glster may be loaded if theinstruction code on pins 17-10 is E1-E7 or E9-EE (See Table 1).The Y bus contains the output of the ALU shifter if OEY is low and is a high impedance input if OEY ishigh. SEL Y must be low to pass the internal ALU shift bus and must be high to pass the external Y busto the register file.Four status pins are available on the most significant package, overflow (OVR), sign (N), carry out (C n + 8),and zero (ZERO). The Cn + 8 line signifies the ALU result while OVR, ZERO, and N refer the status afterthe ALU shift has occurred. Notice that the ZERO pin cannot be used to detect whether an input placedon a high impedance Y bus is zero. .divide BCD flip-flopsThe multiply-divide flip-flops contain the status of the previous multiply or divide instruction. They are ~affected by the following instructions: ~DIVIDE REMAINDER FIXSIGNED DIVIDE OUOTIENT FIXSIGNED MULTIPLYSIGNED MULTIPLY TERMINATESIGNED DIVIDE INITIALIZESIGNED DIVIDE STARTSIGNED DIVIDE ITERATEUNSIGNED DIVIDE STARTUNSIGNED DIVIDE ITERATEUNSIGNED MULTIPLYSIGNED DIVIDE TERMINATEUNSIGNED DIVIDE TERMINATEenThe excess-3 BCD flip-flops are affected by all instructions except NOP. The clear function clears these -Iflip-flops. They preserve the carry from each nibble (4-bits) in excess-3/BCD operations.package position pin (PPP)The position of the processor in the system is defined by the voltage level applied to the package positionpin (PPP). Intermediate positions are selected by leaving the pin open. Tying the pin to Vce makes theprocessor the most significant package and tying the pin to GND makes the processor the least significantpackage.special shift function (SSF) pinConditional shifting algorithms may be implemented via control of the SSF pin. The applied voltage to thispin may be set as a function of a potential overflow condition (the two most significant bits are not equal)or any other condition (see Group 1 instructions).instruction setThe' AS895 bit-slice processor uses bits 17-10 as instruction inputs. A combination of bits 13-10 (Group 1instructions) and bits 17-14 (Group 2-5 instructions) are used to develop the 8-bit op code for a specificinstruction. Group 1 and Group 2 instructions can be combined to perform arithmetic or logical functionsplus a shift function in one instruction cycle. A summary of the instruction set is given in Table 1.TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-367

SN54AS895, SN74AS8958-BIT MEMORY ADDRESS GENERATORSTABLE 1. INSTRUCTION SETIIIrCAC(1):$.(")(1)enINSTRUCTION BITS 113-101HEX CODEGROUP 1 INSTRUCTIONSMNEMONICFUNCTION0 Accesses Group 4 instructions1 ADD R +S+C n2 SUBR R+S+C n3 SUBS R+S+Cn4 INCS S+Cn5 INCNS S+Cn6 INCR R+Cn7 INCNR R+Cn8 Accesses Group 3 instructions9 XOR R XOR SA AND RAND SB OR R OR SC NAND R NAND SD NOR R NOR SE ANDNR RAND SFGROUP 2 INSTRUCTIONSAccesses Group 5 instructionsINSTRUCTION BITS 117-141HEX CODEMNEMONICFUNCTION0 SRA Arithmetic Right Single1 SRAD Arithmetic Right Double2 SRL Logical Right Single3 SRLD Logical Right Double4 SLA Arithmetic Left Single5 SLAD Arithmetic Left Double6 SLC Circular Left Single7 SLCD Circular Left Double8 SRC Circular Right Single9 SRCD Circular Right DoubleA MOSRA Pass (F .... yl and Atithmetic Right MOB MOSRL Pass (F .... y) and Logical Right MOC MOSLL Pass (F .... y) and Logical Left MOD MOSLC Pass (F .... y) and Circular Left MOE LOADMO Pass (F.... y) and Load MO (F=MO)F PASS Pass (F.... y)2-368 TEXAS ..INSTRUMENTSPOST OFFiCe BOX 225012 • DALLAS, TeXAS 75265

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSTABLE 1. INSTRUCTION SET (Continued)GROUP 3 INSTRUCTIONSINSTRUCTION BITS (17-10)HEX CODEMNEMONICFUNCTION08 SETl Set Bit18 SETO Reset Bit28 TB1 Test Bit (One)38 TBO Test Bit (Zero)48 ABS Absolute Value58 SMTC Sign Magnitude/Two's Complement68 ADDI Add Immediate78 SUBI Subtract Immediate88 BADD Byte Add R to S98 BSUBS Byte Subtract S from RA8 BSUBR Byte Subtract R from SB8 BINCS Byte Increment SC8 BINCNS Byte Increment Negative SD8 BXOR Byte XOR Rand SE8 BAND Byte AND Rand SF8 BOR Byte OR Rand SGROUP 4 INSTRUCTIONSINST~UCTION BITS (17-10)MNEMONICFUNCTIONHEX CODE00 Reserved10 SEL Select SIR20 SNORM Single Length Normalize30 DNORM Double Length Normalize40 DIVRF Divide Remainder Fix50 SDIVQF Signed Divide Quotient Fix60 SMUll Signed Multiply Iterate70 SMULT Signed Multiply Terminate80 SDIVIN Signed" Divide Initialize90 SDIVIS Signed Divide StartAO SDIVI Signed Divide IterateBO UDIVIS Unsigned Divide StartCO UDIVI UnSigned Divide IterateDO UMULI UnSigned Multiply IterateEO SDIVIT Signed Divide TerminateFO UDIVIT Unsigned Divide Terminatet/)Q)(.)"SQ)c(J)..oJTEXAS •INSTRUMENTSposf OFFICE BOI( 225012 • DAI.LAS, TEXAS 152652-369

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSTABLE 1. INSTRUCTION SET (Concluded)IrOOCCD~.("')CDengroup 1 instructionsINSTRUCTION BITS (17-10)HEX CODEGROUP 5 INSTRUCTIONSMNEMONICOF CLR ClearIF CLR Clear2F CLR Clear3F CLR Clear4F CLR Clear5F CLR Clear6F CLR Clear7F BCDBIN BCD to BinaryFUNCTION8F EX3BC Excess-3 Byte Correction9F EX3C Excess-3 Word CorrectionAF SDIVO Signed Divide Overflow CheckBF CLR ClearCF CLR ClearDF BINEX3 Binary to Excess-3EF CLR ClearFF NOP No OperationTABLE 2. GROUP 1 INSTRUCTIONSINSTRUCTION BITS (13-10)MNEMONICFUNCTIONHEX CODE0 Accesses Group 4 instructions1 ADD R+S +Cn2 SUBR R+S+Cn3 SUBS R+S+Cn4 INCS S+Cn5 INCNS S+Cn6 INCR R+Cn7 INCNR R+C n8 Accesses Group 3 instructions9 XOR R XOR SA AND RAND SB OR R OR SC NAND R NAND SD NOR R NOR SE ANDNR RAND SFAccesses Group 5 instructions2-370 TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54AS895, SN74AS8958-BIT MEMORY ADDRESS GENERATORSGroup 1 instructions (excluding hex codes 0, 8, and F), shown in Table 2, may be used in conjunctionwith Group 2 shift instructions to perform arithmetic or logical functions plus a shift function t in oneinstruction cycle (hex codes 0, 8, and F are used to access Group 4, 3, and 5 instructions, respectively).Each shift may be made into a conditional shift by forcing the special shift function (SSF) pin into the properstate. If the SSF pin is high or floating, the shifted ALU output will be sent to the output buffers. If theSSF pin is pulled low externally, the ALU result will be passed directly to the output buffers. Conditionalshifting is useful for scaling inputs in data arrays or in signal processing algorithms.These instructions set the BCD flip-flop for the excess-3 correct instruction. The status is set with thefollowing results (Cn + 8 is ALU carry out and is independent of shift operation; others are evaluated aftershift operation).tDouble-precision shifts involve both the ALU and MO register.Status is set with the following results:ArithmeticNOVRCn +8ZLogicNOVRCn +8Zgroup 2 instructionsMSB of resultSigned arithmetic overflowCarry out equal oneResult equal zeroMSB of resultNone (force to zero)None (force to zero)Result equal zeroTABLE 3. GROUP 2 INSTRUCTIONSINSTRUCTION BITS (17-141MNEMONICFUNCTIONHEX CODE0 SRA Arithmetic Right Single1 SRAD Arithmetic Right Double2 SRL Logical Right Single3 SRLD Logical Right Double4 SLA Arithmetic Left Single5 SLAD Arithmetic Left Double6 SLC Circular Left Single7 SLCD Circular Left Double8 SRC Circular Right Single9 SRCD Circular Right DoubleA MOSRA Pass (F-Y) and Arithmetic Right MOB MOSRL Pass (F-YI and Logical Right MOC MOSLL Pass (F-Y) and Logical Loft MOD MOSLC Pass (F-Y) and Circular Left MOE LOADMO Pass (F-Y) and Load MO (F = MO)F PASS Pass (F-Y)EllenQ)(.)'>Q)oen...JTEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-371

SN54AS895, SN74ASB~5B·BIT MEMORY ADDRESS GENERATORSThe processor's shift instructions are implemented by a combination of Group 2 instructions (Table 3)and certain wired connections on the packages used. The following external connections are required.On intermediate packages:S1U7 is connected to ST1J(J of the next most significant packageLmJ7 is connected to omo of the next most significant packageST1J(J is connected to S1U7 of the next least significant package

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSSERIAL I/O (9900 CRUIA'!.. 'LS446GAB--:---UDIR ---'-----1SI07SIOO t-------IBEllenQ)(.)oSQ)cen..J'AS895 'AS895 'AS8950100 t-------IFIGURE 1. SERIAL I/OTEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265. 2-373

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSThe shift instructions are summarized in Table 4 and illustrated in Figure 2. In Figure 2 and all succeedingfigures that illustrate instruction execution, the following definitions apply:OBT End fill for signed divide.MOF End fill for unsigned divide.SRF End fill for signed mUltiply and the arithmetic right shifts.TABLE 4. SHIFT INSTRUCTIONSlEIOP5107·5100 0107·0100SHIFT FUNCTION;CODEt WIRED VALUE WIRED VALUEON Arithmetic Right Single ALU-LSB Output -IN Arithmetic Right Double MQ-LSB Output ALU-LSB Output2N Logical Right Single Input to ALU-MSB ALU-LSB Output3N Logical Right Double Input to ALU-MSB ALU-LSB Output4N Arithmetic Left Single Input to ALU-LSB ALU-MSB Output5N Arithmetic Left Double Input to MO-LSB MQ-MSB Output6N Circular Left Single ALU-MSB Output -7N Circular Left Double ALU-MSB Output MQ-MSB Output8N Circular Right Single ALU-LSB Output -9N Circular Right Double MQ-LSB Output ALU-LSB OutputAN Arithmetic Right (MQ only) MO-LSB Output MQ-LSB OutputBN Logical Right (MQ only) MQ-LSB Output Input to MQ-MSBCN Logical Left (MO only) Input to MO-LSB MQ-MSB OutputDN Circular Left (MQ only) MQ-MSB Output MQ-MSB Outputtop Code N oF 0,8, or F; these select special instruction Groups 4,3, and 5 respectively.~Shift 1/0 pins are active low. Therefore, inputs and outputs must be inverted if truelogical values are required.Status is set with the following results:ArithmeticNOVRCn +8ZLogicNOVRCn +8ZResult MSB equal oneSigned arithmetic overflow tCarry out equal oneResult equal zeroResult MSB equal oneZeroZeroResult equal zerot For the SLA and SLAD instructions, OVR is set if signed arithmetic overflow or if the ALU result MSB XOR MSB-l equals one.2-374 TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54ASB95, SN74ASB95B·BIT MEMORY ADDRESS GENERATORSa..en..Ja..en..Jw..JC!:Jzenl-:t:C!:Ja:ui=w:2::t:I-a:«!:w..Jal:::>0cI- :t:~ex:ui=w:2::t:!:ex:«!:(/)20~u:::>a::I- (/)~l- LLJ:(/)Nwa:::::>(!)u:::II(J)Q)CJ'S;Q)een...JTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-375

SN54AS895. SN74AS8958·BIT MEMORY ADDRESS GENERATORS0.CI)..JII wr- t:JenC,CD

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORScw(Ja:eu.le2:!:!::ea:wNCI)...I...I~Il.(J)...Icw(Ja:eu.le2:!:!::ea:wN'CI)...I...I~W...Ie"zinl- Ll-W...Iui=w::2:J:I-ei:~~w...IOJ::l0cI- Ll-W...IUi=w::2:J:I-ei:~:cCIl::Ic:'';::;c:0~CI)2:ei=(J::J~a:l- CI)~I- !:!::::z:CI)Nwa:::J(!)u::fIIenQ)CJoSQ)een...JTEXAS lj}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-377

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORS0..CI)..J0..CI)-'I w..Jr- (!1CJ) Zu;l-Cu..CD w..J

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSQ.CI)..JQ.CI)..JW..JC,!)zCiil-:I:~a:a:«..J::lua:U~w..JIII::l0cI-:I:~a:a:«..J::lUa:U~:cCI):::lc:"';:;c:0~en2:0i=(.):Ja:l-en~I-~J:enNwa::J(!)u:FJIenQ)(.)'$Q)een..JQ.CI)~Q.CI)~TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-379

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSc.CI)..Jc.CI)..JII >=r- 0..JZen 0~C I-:I:CD !:?

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORS0wua:0u.I-02:!:!::0a:wNCI)...J...J~a.en...Ja.en...J>=...J20a~I-LLw...J...J=...J20a~I-~ u.W...Ja:ua:U~=cQ)"t:J:l(j!:0~CI)2:0f=u::)a:I- CI)~I-!:!::J:CI)Nwa:::)(!Ju:tilCJ)Q)(.)'S;Q)C00..JTEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-381

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSgroup 3 instructionsHex code 8 of Groupsummarized in Table 5.instructions is used to access Group 3 instructions. Group 3 instructions areTABLE 5. GROUP 3 INSTRUCTIONSIIrmcCD

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSset bit instruction (set1): 17-10 = 0816This instruction (Figure 3) is used to force selected bits of a desired byte(s) to one. The desired bits arespecified by an 8-bit mask (C3-CO):: (A3-AO) t consisting of register file address ports that are not requiredto support this instruction. All bits in the selected byte(s) that are in the same bit positions as ones inthe mask are forced to a logical one. The 83-80 address field is used for both source and destination ofthis instruction. The desired byte is specified by forcing SIOO to a low value. Nonselected packages passthe byte through unaltered. The S bus is the source word for this instruction. The status set by the setbit instruction is as follows:NOVRCn + 8ZNone (force to zero)None (force to zero)None (force to zero)Result equal zerot The symbol '::' is concatenation operatorBYTEINSTRUCTIONBYTE3I~';VCCPPpJBYTE2I~';PPP OPENZERO SSF - I- :--- ZERO SSF - I--:----- SI07 SIOO STi57 SiOor-- 01070100 0107 0100- Cn+8 - Cn+8-j> Cn - - p C n ---G-GBYTE1I~/PPP ŌPENr-- ZERO SSF -I-SI07 SIOO01070100- Cn+8- p Cn --0PPP- ZEROSI07 SIOOQ'i07 0100- Cn+8- Ii C n-G~~-------BYTEaI/ElltJ)Q)Co)'S;Q)cen..JCONDITIONALENABLE / \IFIGURE 3. SET BIT (OR RESET BIT)NOTES: 1. Force SIOO = low to select byte.2. Bit mast (C3-CO)::(A3-AO) will set desired bits to one.reset bit instruction (setO): 17-10 = 1816This instruction (Figure 3) is used to force selected bits of a desired byte(s) to zero. The desired bits arespecified by an 8-bit mask (C3-CO)::(A3-AO) consisting of register file address ports that are not requiredto support this instruction. All bits in the selected byte(s) that are in the same bit positions as ones inthe mask are reset. The 83-80 address field is used for both source and destination of this instruction.TEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-383

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSThe desired byte is specified by forcing SIOO to a low value. Nonselected packages pass lhe byte throughunaltered. The.S bus is the source word for this instruction. The status set by the reset bit instructionis as follows:NOVRCn +8ZNone (force to zero)None (force to zero)None (force to zero)Result equal zeroIrencCD

SN54Asa95, SN74ASa95a·BIT MEMORY ADDRESS GENERATORStest bit (zero) instruction (TBO): 17-10 .. 3816This instruction (Figure 4) is used to test selected bits of a desired byte(s). Bits to be tested are specifiedby an 8-bit mask (C3-CO)::(A3-AO) consisting of register file address ports that are not required to supportthis instruction. Write Enable (WE) is internally disabled during this instruction. The desired byte is specifiedby forcing SIOO to a low value. The test will pass if the selected byte has zeros at all bit locations specifiedby the ones of the mask (Figure 6). The S bus is the source word for this instruction. The status set bythe test bit (zero) instruction is as follows:NOVRCn +8ZNone (force to zero)None (force to zero)None (force to zero)PassMSSlssA3-AORsl1 11 11 11 I 0 I 0 I 0 I 0 IRsl1 111111 10 I 0 10 101B3-BO3-C0C3-C0c::AI11111 111101010101 ZERO c::AI11111111101010101TEST PASSES "1" ZERO CiiOO 0ii5'7MSSSiOo"0"SiOiA3-AORsl, 11 I 0 11 I 0 I 0 I 0 I 0 I B3-BO Rsl' 11 11 11 I 0 I 0 I 0 I 0 ILS5"1"A3-AOB3-BOEll(I)Q)o">Q)C-en-JC3-C0C3-C0TEST FAILS "0"ZEROC::AI'1111111101010 101 ZERO C::AI 1 1 1 1'1 1 11 0 1 010 101QiOo 01070107SIOO 5107SI07"0"FIGURE 5_ TEST BIT ONE EXAMPLES"1"TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-385

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSMSSRsl 0 I 0 I 0 I 0 11 I 0 11 I 0 ILSSA3-AO83-80 RS 11 11 11 11 I 011 I 0111C3-C0A3-AO83-80C3-COTEST PASSES "1" ZEROc::AI11111111101110111 ZERO c::AI1Iq11111011101110100 J..----I 0107SIOOSi"57IIrencCD

SN54AS895. SN74AS8958·BIT MEMORY ADDRESS GENERATORSadd immediate instruction (ADDI): 17-10 = 6816This instruction is used to add a specified constant value to the operand placed on the S bus. The constantwill be between the values of 0 and 1 5. The constant value is specified by the unused register file address(A port) not required to support this instruction. Forcing the carry input will add an additional one to theresult. The status set by the add immediate instruction is as follows:NOVRCn +8ZResult MSB equal oneArithmetic signed overflowCarry out equal oneResult equal zerosubtract immediate instruction (SUBI): 17-10 = 7816This instruction is used to subtract a specified constant value from the operand placed on the S bus. Theconstant value is specified by the unused register file address (A port) that is not required to support thisinstruction. The constant applied is the least significant four bits of a two's complement number. The devicesign extends the constant over the entire word length. The status set by the subtract immediate instructionis as follows:NOVRCn +8ZResult MSB equal oneArithmetic signed overflowCarry out equal oneResult equal zerobyte instructionsThere are eight byte instructions in Group 3. These instructions modify selected bytes of the operand onthe S bus. A byte is selected by forcing SIOO to a low value (same as SET1, SETO, TB 1, and TBOinstructions). Multiple bytes may be selected only if they are adjacent to one another.NOTE: At least one byte must be nonselected during these instructions.The nonselected bytes are passed through unaltered. Byte status is forced through the most significantpackage except for the sign of the result (N), which is forced to zero (low). The status set by the byteinstructions is as follows:NOVRCn +8Z(Most Significant Package)None (force to zero)Byte signed overflowByte carry out equal oneByte result equal to zero(f)Q)(.)os:Q)cen...J(Selected BYTES-other than MSP)GPCn +8ZNormal generateNormal propagateNormal carry outResult equal to zero(Nonselected BYTES-other than MSP)GPCn +8ZNo generate (force to one)Propagate (force to zero)C nNone (force to one)TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-387

SN54AS095, SN74AS095O·BIT MEMORY ADDRESS GENERATORSgroup 4 instructionsHex code 0 of Groupsummarized in Table 6.instructions is used to access Group 4 instructions. Group 4 instructions areselect SIR instruction (SEL): 17-10 os 1016TABLE 6. GROUP 4 INSTRUCTIONSINSTRUCTION BITS (17-10)OP CODE (HEX)MNEMONICFUNCTION00 Reserved10 SEL Select SIR20 SNORM Single Length Normalize30 DNORM Double Length Normalize40 DIVRF Divide Remainder Fix50 SDIVQF Signed Divide Quotient Fix60 SMUll Signed Multiply Iterate70 SMULT Signed Multiply Terminate80 SDIVIN Signed Divide Initialize90 SDIVIS Signed Divide StartAO SDIVI Signed Divide IterateBO UDIVIS Unsigned Divide StartCO UDIVI Unsigned Divide IterateDO UMULI Unsigned Multiply IterateEO SDIVIT Signed Divide TerminateFO UDIVIT Unsigned Divide TerminateThis instruction is used to pass either the S bus or the R bus to the output depending on the state of theSSF input pin. Normally, the preceding instruction would test the two operands and the resulting statusinformation would be used to force the SSF input pin. SSF = 0 will output the R bus and SSF = 1 willoutput the S bus. The status set by the select SIR instruction is as follows:NOVRCn +8ZResult MSB equal oneNone (force to zero)None (force to zero)Result equal zerosingle-length normalize instruction (SNORM): 17-10 = 2016This instruction will cause the contents of the MO register to shift toward the most significant bit. Zerosare shifted in via the 0100 input. The number of shifts performed can be counted and stored in one ofthe register files by forcing a high at the Cn input. When the two most significant bits are of oppositevalue, normalization is complete. This condition is indicated on the microcycle that completes thenormalization at the OVR output.The chip contains conditional logic that inhibits the shift function (and also inhibits the register file increment)if the number within the MO register is already normalized at the beginning of the instruction (Figure 7).The status set by the single-length normalize instruction is as follows:N 4 MSB of resultOVR MSB XOR 2nd MSBCn +8ZCarry out equal oneResult equal zero2-388 TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSQ.en...JQ.en....IwN:J«:i:0::0Z:r:I-t!'ZW...JW...Jt!'ziii!:wN:J«:i:0::0Z:r:l-t!'Zw...Jw...Jco::>0c!:WN::::i«~a:02::r:I-(!)2:w....IW....Ico:J0002:«W....I(!)2:Ci5....:wa::J(!)u:ElltJ)Q)CJ":;Q)Cen...JTEXAS -I!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-389

vSN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSdouble-length normalize instruction (DNORM): 17-10 .,. 3016This instruction will cause the contents of a double-length word (register file contains the most significanthalf and the MO register contains the least significant half) to shift toward the most significant bit. Zerosare shifted in via the 0100 input. When the two most significant bits are of opposite value, normalizationis complete. This condition is indicated on the microcycle that completes the normalization at the OVRo~p~.•The chip contains conditional logic which inhibits the shift function if the number is already normalizedat the beginning of the instruction (Figure 7). The most significant half of the operand must be placedon the S bus. The status set by the double-length normalize instruction is as follows:NOVRCn+SZmUltiply operationsMSB of resultMSB XOR 2nd MSBNone (force to zero)Result equal zeroThe ALU performs three unique types of N by N multiplies each of which produces a 2N-bit result (Figure S).All three types of multiplication proceed via the following recursion:renc(1)

SN54ASB95, SN74ASB95B·BIT MEMORY ADDRESS GENERATORS0..CI)..JCoen..Jl- ..J;:)::ECI):::::i:>::ECI)!:::J:>::E:>CoC/):2:e~cta:wa.e:2:e~ctC,,):Ja.j::...J;:)2ex)wa:;:)" u:::tJ)Q)(.)'SQ)Cen-oJ0..CI)::E0..CI)::ETEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-391

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSThe signed multiply iterate (SMUll) instruction performs a signed times signed iteration. This instructioninterprets M(BN-J) as the BN-J bit of the multiplier. The shift is a double-precision right shift one bit. Thisinstruction is repeated 15 times for a 16 x 16 signed mUltiply. This instruction will be used 16 consecutivetimes for a mixed multiplication.The signed multiply terminate (SMULT) instruction provides correct (negative) weighting of the sign bitof a negative multiplier in signed mUltiplication. The instruction is identical to signed multiply iterate (SMUll)except that M(BN-J) is interpreted as - 1 if the sign bit of the multiplier is 1, and 0 if the sign bit of themultiplier is O.The unsigned multiply iterate (UMULI) performs an unsigned multiplication iteration. This instructioninterprets M(BN-J) as the BN-J bit of the multiplier. The shift is a double-precision right shift with the carryout from the P(J) + Multiplicand x M(BN-J) operation forced into bit BN of P(J + 1). This instructionis used in unsigned and mixed multiplication.signed multiplicationSigned multiplication performs an BN + 2 clock two's complement mUltiply. The instructions necessaryto produce ~m algebraically correct result proceed in the following manner:lEIrC/)CCD

SN54AS895. SN74AS8958·81T MEMORY ADDRESS GENERATORSUpon completion, the accumulator will contain the BN most significant bits and the MQ contains the BNleast significant bits of the product.The status set by the unsigned multiply iteration is meaningless except on the final execution of theinstruction. The status set by the unsigned multiply iteration instruction is as follows:NOVRCn+BZResult MSB equal oneForced to zeroCarry out equal to oneDouble-precision result is zeromixed multiplicationMixed multiplication multiplies a signed multiplicand times an unsigned multiplier to produce a signed resultin BN + 2 clocks. The steps are as follows:Zero register used for accumulatorLoad MQ with unsigned multiplerSMUll (BN times)SportR portF portAccumulatorMultiplicandIteration resultUpon completion, the accumulator will contain the BN most significant bits and the MQ will contain theBN least significant bits of the product.The following status is set by the last SMUll instruction:NOVRCn +8ZResult MSB equal oneForced to zeroCarry out equal to oneDouble-precision result is zeroenQ)CJoSQ)cen..Jdivide operationsThe divide uses a nonrestoring technique to perform both signed and unsigned division of a 16N bit integerdividend and an BN bit integer divisor (Figure 9). It produces an BN integer quotient and remainder.The remainder and quotient will be such that the following equation is satisfied:(Quotient) X (Divisor) + Remainder = DividendThe processor has the following divide instructions:1. UNSIGNED DIVIDE START (UDIVIS): 17-10 = B0162. UNSIGNED DIVIDE ITERATE (UDIVI): 17-10 = C0163. UNSIGNED DIVIDE TERMINATE (UDIVIT): 17-10 = F0164. SIGNED DIVIDE INITIALIZE (SDIVIN): 17-10 = B0165. SIGNED DIVIDE OVERFLOW TEST (SDIVO): 17-10 = AF166. SIGNED DIVIDE START (SDIVIS): 17-10 = 90167. SIGNED DIVIDE ITERATE (SDIVI): 17-10 = A016B. SIGNED DIVIDE TERMINATE (SDIVITi: 17-10 == E0169. DIVIDE REMAINDER FIX (DIVRF): 17-10 = 401610. SIGNED OIVIDE QUOTIENT FIX (SDIVQF): 17-10 = 5016-~• .-IjTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265,2-393

SN54AS895, SN74AS8958·BITMEMORY ADDRESS GENERATORSc.(J)...Jc.(J)...JEIr-enC~C(J)z·:;c(J)c.t->c(J)~f/)z0i=a::«wc..0wc:;cenwa::::J(!)u:::c.(J):Ec.(J):E2-394 TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54ASB95, SN74ASB95B·BIT MEMORY ADDRESS GENERATORSQ.en....JQ.en....J:>is::len'>is::lQ.I->is::l~:cQ)::::J.=E0~(/)2:0i=isenw0::::l(!)u:::Ell(J)Q)"oSQ)Cen...JTEXAS -Ij}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-395

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSThe unsigned divide iterate start (UDIVIS) instruction begins the iterate procedure while testing for overflow.Overflow is reported when the first subtraction of the divisor from the MSH of the dividend produces carryout. The test detects quotient overflow and divide by zero.The unsigned divide iterate terminate (UDIVIT) instruction completes the iterate procedure generating thelast quotient bit.The signed divide initialize (SDIVIN) instruction prepares for iteration by shifting the dividend and storingthe sign of the dividend for use in the following instructions and overflow tests.The signed divide overflow test (SDIVO) checks for overflow possibilities. This instruction may be deletedfrom the divide operation if the OVR pin is ignored. If it is removed some overflow conditions will goundetected. WE must be high (writing inhibited) when this instruction is used.lEIrC/)cCD

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSSDIVI (SN-2 times)SDIVITDIVRFSDIVOFSportR portF portSportR portF portSportR portF portSportR portF portResult of SDIVIS (or SDIVI)DivisorIntermediate resultResult of last SDIVIDivisorIntermediate resultResult of SDIVITDivisorRemainderMO registerDivisorQuotientThe status of all signed divide instructions except SDIVIN, DIVRF, and SDIVOF is as follows:NOVRCn+SZForced to zeroForced to zeroCarry out equal to oneIntermediate result is zeroThe status of the SDIVIN instruction is as follows:NOVRCn +8ZForced to zeroForced to zeroForced to zeroDivisor is zeroThe status of the DIVRF instruction is as follows:NOVRCn +8ZForced to zeroForced to zeroCarry out equal to oneRemainder is zerotnQ)(,)"SQ)c(J)..JThe status of the SDIVOF instruction is as follows:NOVRCn+SZSign of quotientDivide overflowCarry out equal to oneOuotient is zeroThe quotient is stored in the MO register and the remainder is stored in the register file location that originallyheld the most significant word of the dividend. If fractions are divided, the quotient must be shifted rightone bit and the remainder right three bits to obtain the correct fractional representations.The signed division algorithm is summarized in Table 7.TEXAS -1.11INSTRUMENTSP(")ST OFFICE BOX 225012 • DALLAS, TEXAS 752652-397

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSTABLE 7. SIGNED DIVISION ALGORITHMOP CLOCK INPUT INPUT OUTPUTMNEMONICCODE CYCLES SPORT R PORT F PORTE4 LOADMQ 1 Dividend (LSH) - Dividend (LSH)BO SDIVIN 1 Dividend (MSH) Divisor Remainder (N)AF SDIVO 1 Remainder (N) Divisor Test Result90 SDIVIS 1 Remainder (N) Divisor , Remainder (N)AO SDIVI BN-2t Remainder (N) Divisor Remainder (N)EO SDIVIT 1 Remainder (N) Divisor Remainder (Unfixed)40 DIVRF 1 Remainder (Unfixed) Divisor Remainder50 SDIVQF 1 MQ Register Divisor QuotienttN = Number of cascaded packages.unsigned divide usageThe instructions necessary to perform an algebraically correct division of unsigned numbers are as follows:Load MQ with the least significant half of the dividend.-enC(1)

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSTABLE 8. UNSIGNED DIVISION ALGORITHMgroup 5 instructionsOP CLOCK INPUT INPUT OUTPUTMNEMONICCODE CYCLES SPORT R PORT F PORTE4 LOADMQ 1 Dividend (LSH) - Dividend (LSH)BO UDIVIS 1 Dividend (MSH) Divisor Remainder (N)CO UDIVI 8N-1 t Remainder (N) Divisor Remainder (N)FO UDIVIT 1 Remainder (N) Divisor Remainder (Unfixed)40 DIVRF 1 Remainder (Unfixed) Divisor Remaindert N = Number of cascaded packages.Hex code F of Groupsummarized in Table 9.instructions is used to access Group 5 instructions. Group 5 instructions areTABLE 9. GROUP 5 INSTRUCTIONSINSTRUCTION BITS (17-10)OP CODE (HEX)MNEMONICFUNCTIONOF CLR Clear1F CLR Clear2F CLR Clear3F CLR Clear4F CLR' Clear5F CLR Clear6F CLR Clear7F BCDBIN BCD to Binary8F EX3BC Excess-3 Byte Correction9F EX3C Excess-3 Word CorrectionAF SDIVO Signed Divide Overflow CheckBF CLR ClearCF CLR ClearDF BINEX3 Binary to Excess-3EF CLR ClearFF NOP No OperationIIItnQ)ICJ'S;Q)cen...Iclear instructions (ClR)There are 11 clear instructions listed in Table 9. The instructions force the AlU output to be zero andthe BCD flip-flops to be cleared. The status set by the clear instruction· is as follows:NOVRCn +8ZNone (force to zero)None (force to zero)None (force to zero)Active (one)no operation instruction (NOP): 17-10 = FF16This instruction is identical to the clear instructions except that the BCD flip-flops retain their old value.TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-399

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSexcess-3 correction instructions (EX3BC, EX3C)Two excess-3 correction instructions are available:1. Excess-3 byte correction (EX3BC): 17-10 = SF162. Excess-3 word correction (EX3C): 17-10 = 9F16One instruction supports the byte mode and the other supports the word mode. These instructions correctthe excess-3 additions (subtractions) in either the byte or word mode. For correct excess~3 arithmetic,this instruction must follow each add/subtract. The operand must be on the Sport.·NOTE: The previous arithmetic overflow should be ignored.The status of the EX3C instruction is as follows:NOVRCn+SZMSB of resultSigned overflowCarry out equal oneNone (force to one)IrenThe status of the EX3BC instruction is as follows:NOVRCn+SZNone (force to zero)Byte signed overflowCarry out equal oneNone (force to one)radix conversions:? Conversions between decimal and binary number representations are performed with the aid of two special< instructions: BINEX3 and BCDBIN. (Figure 10)(i'm BCD to binary instructions (BCDBIN): 17-10 - 7F16This instruction (Figure 11) allows the user to convert an N-digit BCD number to a 4N-bit binary numberin 4(N-1) plus S clocks. This function sums the R bus, the S bus, and the Cn bit, performs an arithmeticleft shift on the ALU result, and simultaneously circular shifts the MQ left. The status set by the BCD tobinary instruction is as follows:NOVRCn+SZMSB of resultSigned arithmetic overflow tCarry out equal oneResult equal zerot Overflow may be the result of an ALU operation or the arithmetic left shift operation.2-400TEXAS "'-'INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSThe following code illustrates the BCD to binary conversion technique.Let ACC be an accumulator registerLet NUM be the register which contains the BCD numberLet MSK be a mask registerM1:M2:M3:M4:M5:M6:Li:, L2:L3:L4:M7:M8:LOADMO NUMSUB ACC, ACC, SLCMOSUB, MSK, MSK, SLCMOSLCMOSLCMOADDIACC, MSK, 1510AND MO, MSK, R1, SLCMOADD, ACC, R1, Fn, SLCMOBCDBIN, R1, R1, ACCBCDBIN, ACC, R1, ACCAND MO, MSK, R1ACC + R1 -+ ACC; LOAD MO WITH BCD NUMBER; CLEAR ACC AND ALIGN MO; CLEAR MSK AND ALIGN MO; ALIGN; ALIGN; MSK = 1510; REPEAT L 1 THRU L4; N - 1 TIMES (N = number of; BCD digits); EXTRACT ONE DIGIT; ALIGN MQ; ACC, + DIGIT; IS STORED IN R1; ALIGN MO; 4 X (ACC + DIGIT); IS STORED IN ACC; ALIGN MO; 10 x (ACC + DIGIT); IS STORED IN ACC; ALIGN MO; FETCH LAST DIGIT; ADD IN LAST DIGITThe previous code generates a binary number by executing the standard conversion formula for a BCDnumber (shown for 32 bits).ABCD = [(A X 10 + B) X 10 + C) X 10 + DNotice that the conversion begins with the most significant BCD digit and that the addition is performedin radix 2.II(f)Q)(.)oS;Q)Cen --..Jbinary to excess-3 instructioris (BINEX3): 17-10 = DF16This instruction (Figure 12) allows the user to convert an N-bit binary number to an N/4-bit excess-3 numberrepresentation in 2N + 3 clocks. The data on the Rand S ports are summed with the MSB of the MO register.The MO register is simultaneously shifted left circularly. The status set by the binary to excess-3 instructionis as follows:NOVRCn +8ZMSB of resultSigned arithmetic overflowCarry out equal oneResult equal zeroTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-401

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSQ.en-JQ.en-JlEIr-CJ)Ze 10CD cu< coo·CDt/)!:> a:«:2D50l-M0 x(.) wa:Iciwa::::>(!)u:::zD5!:Menenw(.)xw0I-> a:«:2D5...:wa:,:::>(!)u:::2-402TEXAS -I/}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSThe following illustrates the binary to excess-3 conversion technique.Let NUM be a register containing an unsigned binary numberLet ACC be an accumulatorM1:M2:M3:L 1:L2:LOADMQ NUMCLEAR ACCSET1 ACC H/33/BINEX3 ACC, ACC, ACCEX3C ACC, ACC; LOAD MQ WITH BINARY; NUMBER; CLEAR ACC; ACC -+ HEX/3333 ..; DOUBLE ACC AND ADD IN; MSB OF MQ; ALIGN MQ; EXCESS 3 CORRECT; REPEAT L 1 AND L2; N-1 TIMESThe previous code generates an excess-3 number by executing the standard conversion formula for a binary·number.an2n+an_12n-1 +an-22n-2+ ... a020 = [(2an.+an-1)2+an-212 + ... aoNotice that the conversion begins with the most significant binary bit and that the addition is performedin radix-10 (excess-3).decimal arithmeticDecimal numbers are represented in excess-3 code. Excess-3 code numbers may be generated by addingthree to each digit of a Binary Coded Decimal (BCD) number. The hardware necessary to implement excess-3arithmetic is only slightly different from binary arithmetic. Carries from one digit to another during additionin BCD occur when the sum of the two digits plus the carry-in is greater than or equal to ten. If both numbersare excess-3, the sum will be excess-6, which will produce the proper carries. Therefore, every additionor subtraction operation may use the binary adder. To convert the result from excess-6 to excess-3, onemust consider two cases resulting from a BCD digit add: (1) where a carry-out is produced, and (2) wherea carry-out is not produced. If a carry-out is not produced, three must be subtracted from the resultingdigit. If a carry is produced, the digit is correct as a BCD number. For example, if BCD 5 is added to BCD 6,the excess-3 result would be 8 + 9 = 1 (with a carry). A carry rolls the number through the illegal BCDrepresentations into a correct BCD representation. Binary 3 must be added to digit positions that producea carry-out to correct the result to an excess-3 representation. Every addition and subtraction instructionstores the carry generated from each 4-bit digit location for use by the excess-3 correction functions. Thesecorrection instructions (word or byte) must be executed in the clock cycle immediately after the additionor subtraction operation.Signed numbers may be represented in ten's complement form by complementing the excess-3 number.As an example, add the decimal number - 423 to the decimal number 24, which will be represented by8AA and 357 in excess-3, respectively.8AA357C01011934-6CC-399SumCarryExcess-3 correctComplementExcess-3 to decimalComplements of excess-3 numbers may be generated by subtracting the excess-3 number from an excess-3zero followed by an excess-3 correct.•fJ)Q)CJoSQ)cen-ITEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-403

SN54AS895, SN74AS8958-BIT MEMORY ADDRESS GENERATORSlEIrCJ)CCD

SN54AS895, SN74AS8958-BIT MEMORY ADDRESS GENERATORSabsolute maximum rating over operating free-air temperature range (unless otherwise noted)Supply voltage, Vee1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VSupply voltage, Vee2 ........................................................ 3 VInput voltage .............................................................. 7 VHigh-level voltage applied to 3-state outputs .................................... " 5.5 VOperating case temperature range: SN54AS895. . . . . . . . . . . . . . . . . . . . . . . . .. - 55 °e to 125 °eOperating free-air temperature range: SN74AS895, SN74AS895-1 ............... ooe to 70 0 eStorage temperature range ......................................... - 65 °e to 150 °erecommended operating conditionsSN54AS895SN74AS895SN74AS895-1MIN NOM MAX MIN NOM MAXVCC1 I/O supply voltage 4.5 5 5.5 4.5 5 5.5 VVCC2 STL internal logic supply voltage 1.9 2 2.1 1.9 2 2.1 VVIH High·level input voltage 2 2 VVIL Low-level input voltage 0.8 0.8 V10H High·level output current -1 -2.6 mAI All output except G and ZERO 8 810L Low-level output current IG 16 16 mAI ZERO 48 '48TC Operating case temperature -55 125TA Operating free-air temperatureUNITII°c0 70 enQ)(,)electrical characteristics over recommended operating free-air temperature range (unless otherwisenoted) Q)PARAMETERITEST CONDITIONSVIK VCCl = 4.5 V, 11= -18 mAVCC1 = 4.5 V to 5.5 V, IOH = -0.4 mAAll outputsVOH VCC1 = 4.5 V, IOH = -1 mAexcept ZEROVCC1 = 4.5 V, 10H = -2.6 mA10H ZERO VCCl = 4.5 V, VOH = 5.5 VAll outputsexcept IT and ZEROVCCl = 4.5 V, IOL = 8 mAVOLG VCCl = 4.5 V, 10L = 16 mAIIZERO VCCl = 4.5 V, IOL = 48 mAI/O VCCl = 5.5 V, VI = 5.5 VAll others VCCl = 5.5 V, VI = 7 VIIH i VCCl = 5.5 V, VI = 2.7 VIlL i VCCl = 5.5 V, VI = 0.5 V10§ VCCl = 5.5 V, Va = 2.25 VICClICC2VCCl = 5.5 VVCC2=2.1VSN54AS895MIN Typt MAX MIN Typt MAX-1.2-1.2VCC- 2VCC-22.42.40.10.1tAli typical values are at VCC = 5 V, TA = 25°C.iFor I/O ports, the parameters IIH and IlL include the off-state current.§The output conditions have been chosen to produce a current that closely approximates one-half the true short-circuit current, lOS.0.50.50.50.10.120-0.4-30 -112150410SN74AS895SN74AS895-10.50.50.50.10.120-0.4-30 -112130390UNITVVmAVmAp.AmAmAmAmAoS;Cen..JTEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-405

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSSN54AS895 maximum switching characteristics, Vee = 4.5 V to 5.5 V, Te(see Note 1)IrCJ)cPARAMETERtpd. FROM(INPUT)A3-AOB3-BODA7-DAO.DB7-DBOCnEAEB)7-10OEBOEYGIO (n)ShiftSIO (n)ShiftCKOEASSFit Load resistor R 1 = 100 n.V Cn +8 G.P62 42 4847 28 2825 14 -54 32 3554 32 3558 32 32- - -14 - -15 - -15 - -68 60 56- - -- - -i For byte instructions only.NOTE 1: Load circuit and voltage waveforms are shown in Section 1.TO (OUTPUT)zt N OVR DA DB69 62 60 18 -58 50 42 - -32 24 18 - -62 52 52 - -62 52 52 - -62 52 41 - -- - - - 14- - - - -24 - - - -24 22 - - -62 50 68 38 30- - - 14 -- - 14 - -CD< SN74AS895 maximum switching characteristics, Vee 4.5 V to 5.5 V, TAc;' Note 1)CDrnFROMTO (OUTPUT)PARAMETER(INPUT) V Cn +8 G.P zt N OVR DA DBA3-AO54 36 42 60 52 50 - -83-80tpdDA7-DAO.DB7-DBOCnEAEB17-10OEBOEYGIO (n)ShiftSIO (n)ShiftCKOEASSFi44 2625 949 2949 2955 30- -12 -15 -15 -58 55- -- -t Load resistor R1 = 100 n.i For byte instructions only.NOTE 1: Load circuit and voltage waveforms are shown in Section 1 .26 52 46 38- 32 24 1829 58 49 4729 58 49 . 4730 60 49 39- - - -- - - -- 24 - -- 24 19 -52 61 52 62- - - -- - - 12- -- -- -- -- -- 12- -- -- -35 2512 -- -QIOSIO65 6650 50UNIT32 3258 5858 5858 58- - ns- -- -- -70 70-0-- -o °e to 70 0 e (seeGIOSIO58 5844 44UNIT31 3154 5454 5454 54- - ns- -- -- -60 60- -- -2-406 . TEXAS"INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSSN74AS895-1 maximum switching characteristics, Vee = 4.5 V to 5.5 V, TA = 0 °e to 70 °e (seeNote 1)PARAMETERtpdFROM(INPUT)A3-AOB3-BODA7-DAO,DB7-DBOCnEAEB17-10OEBOEY010 (n)ShiftSIO (n)ShiftCKOEASSF:I=y Cn +8 G, P44 30 3636 24 2422 8 -40 25 2540 25 2546 27 27- - -12 - -14 - -14 - -50 46 46- - -- - -ztTO (OUTPUT)N OVR50 4446 4127 2149 4149 4150 42- -- -20 -20 1850 50- -- -443216414135----50-12UNITDA DB 010 SIO17 - 48 48- - 40 40- - 25 25- - 44 44- - 44 44- - 45 45- 12 - - ns- - - -- - - -- - - -30 22 50 5012 - - -- - - -t Load resistor R 1 = 100 n.:1= For byte instructions only.NOTE 1: Load circuit and voltage waveforms are shown in Section 1.register file write setup and hold timestsuthPARAMETERC3-CODB§17-1413-10OEYY7-YOWEOIO(n), SIO(n)SELYC3-CODB§17-1413-10OEYY7-YOWEOIO(n), SIO(n)SELYSN54AS895MIN MAX8141624428680000610308SN74AS895 SN74AS895-1MIN MAX MIN MAXUNIT7 612 1114 1322 213 3 ns2 26 65 56 60 00 00 00 05 5 ns10 102 20 06 6§DB (during select instruction) through Y port.TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-407

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSspecial instruction switching characteristicsDuring various special instructions, the SSF pin is used to pass required information between the' AS888packages which make up a total system.For instance, during the multiplication process, the LSB of the multiplier determines whether an ADD/SHIFTor SHIFT operation is performed. During multiplication, the SSF pin of the least significant package (LSP)becomes an output pin while all other packages become input pins.Similarly, during normalization, the required operation depends on whether the two data MSBs are thesame or different. Therefore, during normalization the SSF pin of the most significant package (MSP)becomes an output pin while all other packages become input pins.Tables 10, 11, and 12 list the instructions which force the SSF pin during their execution. The propagationdelay from various inputs is also shown. The parameter which limits normal system performance is indicatedby a dagger.TABLE 10. SN54AS895 SSF PIN DELAYS AND SETUP TIMESrCJ)cCD

SN54AS895, SN74AS8958·BIT MEMORY ADDRESS GENERATORSTABLE 11. SN74AS895 SSF PIN DELAYS AND SETUP TIMESMNEMONICSNORMDNORMDIVRFSDIVQFSMUllSDIVINSDIVISSDIVIUDIVISUDIVIUMULISDIVITABSSMTCBINEX3LOADMQ (Arith)LOADMQ (Log)BADDBSUBSBSUBRBINCSBINCNSBXORBANDBOREX3BCHEX SSF SOURCE INPUT -+ SSF (ns) SSF SETUPCODE LSP MSP Cn I(n) _ CK B(n) TIME (ns)20 X - 26T 40 - 1730 X - 26 52 37 t 1740 X - 26 t 40 - 1750 X - 25 t - - 1760 X - 25 t 40 - 080 X - 38 60 40t 090 X 24t 48 60 52 0AO X 24t 48 60 52 0BO X 17t 43 60 45 0CO X 17t 44 52 37 0DO X - 26 t 40 - 0EO X 25 t 46 52 49 048 X - 32 60 38 1758 X - 26 52 38 t 17DF X - 26 t 40 - 17X 22t 32 50 38 0tThis parameter limits normal system performance .X - 32 50 38 t 08817t 52 55 46 -98 i17t 52 55 46 -SOURCEA8 17t 52 62 46 -ISB8 17t 52 55 46 -MOSTC8 17t 52 62 46 -SIGNIFICANTD8 - 52 - - -BYTEE8 - 52 - - -SELECTEDF8- 52 - - -8F - 45 45 46 t -~tilenQ)UoSQ)oen..J. TEXAS"INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-409

SN54AS095, SN74AS095O·BIT MEMORY ADDRESS GENERATORSTABLE 12. SN74AS895-1 SSF PIN DELAYS AND SETUP TIMESlEIrCJ)cCD

SN54AS897A, SN74AS897A16·BIT PARALLEL/SERIAL BARREL SHIFTERSD2885. OCTOBER 1985-REVISED MARCH 1986• High-Speed "Flash" Shift Operations• Expandable to 32 BitsSN54AS897A.SN74AS897AG8 PIN-GRID ARRAY PACKAGE(TOP VIEW)• Hexadecimal and' Binary Normalization withLeading Zero Detection• Bit Reversal• Merge Capabilities• Texas Instruments Quality and ReliabilitydescriptionThe SN54AS897A and SN74AS897A a~multipurpose 16-bit barrel shifters in a 68-pin'ceramic pin-grid-array package. The devices arecapable of several different types of shiftoperations, as well as other more specializedfunctions such as hexadecimal and binarynormalization, bit replacement, and leading-zerodetection.The unique .feature of all barrel shifters is howthe shift function is implemented. Inconventional shift registers, shift operations arecontrolled by the number of input clock pulsesapplied. With barrel shifters, the desired numberof positions to be shifted is determined by aninput decoder. This form of implementation doesnot require an input clock and results in a shiftoperation that is restricted only by internalpropagation delays. This delay is the sameregardless of the number of positions to beshifted. The result is a high-speed "flash" typeof shift.The' AS897 A offers the system designer a muchbroader range of capabilities than previousconventional shift registers. Normalization ofdata in floating-point computations, bit-reversalwhen generating Fast Fourier Transform (FFT)addresses, and insertion of stop/start bits inasynchronous data communications are just afew of the applications that are possible with thisdevice.The' AS897 A can be operated as an ' AS897 byconnecting the HEX/BIN pin (J1) to ground.ACDGH3 ,4 5 7 8 9 10 11• • • • • • • • • •• 0· • • • • • • 0·• • • •• • • •• • • •• • • •• • • •• • • •• • • •• 0· • • • • • 0·• • • • • • • •PIN ASSIGNMENT TA8LEPIN PIN PIN PINNO. NAME NO. NAMEA2 ZNl FlO GNDA3 ZN2 Fll Y9A4 ZN3 Gl D4A5 GND G2 GNDA6 i'JORM Gl0 YllA7 ZL GIl Y8A8 GND HI NCA9 16B/32B H2 D5Al0 OP Hl0 GNDBl D14 Hll Y7B2 D13 Jl HEX/BINB3 D15 J2 D3B4 ZNO Jl0 GND. B5 VCC2 Jll GNDB6 ZN4 Kl D2B7 IP K2 DlB8 VCCI K3 VCCIB9 GND K4 MlBl0 S K5 GNDBll Y15 K6 CLKCl D12 K7 GNDC2 D9 K8 VCC2Cl0 Y13 K9 Y6Cll Y12 Kl0 Y4D} Dll Kll Y5D2 . D8 L2 DODl0 NC L3 M2Dll GND L4 MOEl Dl0 L5 TPE2 D7 L6 DEYEl0 Y14 L7 YOEll Yl0 L8 YlFl GND L9 Y2F2 D6 L10 Y3EllU)Q)(.)">Q)C(J)..JNC-No internal connectionChip Carrier information available from factory upon request.PRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments~~~~~:~~i~ai~:1~1i ~!~:i~~ti:; :1~o::~:~:t:~~S not. TEXAS.INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265Copyright © 1985. Texas Instruments Incorporated2-411

SN54AS897A, SN74AS897A16·BIT PARALLEL/SERIAL BARREL SHIFTERSlogic symbol t16·BIT PARAllEL/SERIAL BARREL SHIFTER'ASS97AMOMlM2Il41IK41Il31MO MO Ml M2 SHIFT OPERATIONMl l l l SHIFT RIGHT. S FillM2l l H SHIFT lEFT. S Filll H SHIFT RIGHT. CIRCULARl H SHIFT lEFT. CIRCULARl l SHIFT RIGHT. S Fill.MERGEl l H SHIFT lEFT. S Fill.MERGEl H l SET BIT N TO Sl H H NORMALIZE. S FilllEIDO01020304050607DB09010011012013014015Il21IK21IKllIJ21IGllIH21IF21IE21IB3115I OOAT~ ~v15IL71YOIlSIYlIl91Y2Ill01Y3IK101Y4IKlllY5IK91Y6IHlllY7IGlllYBIFlllY9IElllYl0IG101YllIClllY12IC101Y13IE101Y14IBlllY15tThis symbol is in accordance with ANSI/IEEE Std 91-1984.2-412 TEXAS ..INSTRUMENTSPOST OFFICE.BOX 225012 • DALLAS. TEXAS 75265

~~SN54AS897A, SN74AS897A16·BIT PARAllEL/SERIAL BARREL SHIFTERSfunctional block diagram (positive logic)MOM1M2HEX/BiN16B/326IPOP01HEX 2BINARY 3416 BIT 5MC}cLc- L32 BITIP67BITS16OP 161616r---S3232r-C NORM 3232CONTROLOPERATIONShift right (-+nl, S fillShift left (+-nl, S fillShift right (-+nl, circularShift left (+-nl, circularShift right (-+nl, S fill, mergeShift left (+-nl, S fill, mergeSet bit n to SNormalize (+-nl, S fillIP OP OPERATION0 X Without bit reversal1 X With bit reversalX 0 015-00 shiftedX 1 Register data shifted0 X 015-00 least sig_ input1 X 015-00 most sig_ inputX 0 Y15-YO least sig. outputX 1 Y15-YO most sig_ outputnZlt--to-~EN4XI> Qk~AZN3-ZNO},1~ lEAOING015-00 -,-- ZEROOETECTORClKL16 &r-:::= 1I r-161~,REGISTER/COUNTERCTR164CTR4ClI+n {;'.QI'I-r-, ~16OATASELECTMUX4*=....::::BITREVERSAL16MERGESHIFT+-n/-+np: ~~6,16F Mr-SOR ZFill,'- EN I>(J)Q)Q~~ ZN4 CJoS;Q)C..... Zlen..J...~16XI>Q~ Y15-YO, 16TEXAS -I/}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-413

SN54AS897A, SN74AS897A16·BIT PARALLEL/SERIAL BARREL SHIFTERSrU)CCD

SN54AS897A, SN74AS897A16·BIT PARALLEL/SERIAL BARREL SHIFTERSPINI/ONAME NO.OEY L6 IOP Al0 IS Bl0 ITP L5 IVCCl B8VCCl K3VCC2 B5VCC2 K8YO L7 I/OYl L8 I/OY2 L9 I/OY3 L 10 I/OY4 Kl0 I/OY5 Kll I/OY6 K9 I/OY7 Hll I/OY8 Gll I/OY9 Fll I/OYl0 Ell I/OYll Gl0 I/OY12 Cll I/OY13 Cl0 I/OY14 El0 I/OY15 Bll I/OZL A7 I/OZNO B4 I/OZNl A2 I/OZN2 A3 I/OZN3 A4 I/OZN4 B6 I/ODESCRIPTIONControl input for the Y15-YO I/O ports. When OEY is low, the Y outputs are enabled.In the 16·bit mode, controls the source of input data. A logic high on this input selects data from theregister/counter. A low selects data on the 015-00 inputs.In the 32-bit mode, defines the package output positions. When OP is high, Y15-YO are in the most significantoutput position. When OP is low, Y15-YO are in the least significant output position.Specifies the logic level that will fill the bit position or positions vacated during all shift operations except16-bit circular. In the 16-bit circular mode, when S is high, the data latch operates as a 16-bit binary counter.When S is low, the register functions as a data latch.Functional testing input. When low, transforms the 16-bit counter into four 4-bit counters. During normaloperation, 'fP must be maintained at a high logic level.5-volt supply for TTL-compatible I/O2-volt supply for internal Schottky Transistor Logic (STL)Input/output bits 0-15. As an input, they load the data register. A an output, they present the shifted data.An input/open-collector output used primarily in 32-bit applications. When the input at 015-00 is zero,the ZL output is high. The ZL outputs of cascaded packages are connected in a wired-ANO configurationto detect if all inputs are zero. A recommended pull-up resistor of 200 to 680 (l must be provided externallyfor proper operation in the 32-bit mode.A four-bit code that performs the following functions in the 16-bit mode:1. As an input in shift instructions, specifies how many bit positions are to be shifted.2. As an input in replace instructions, specifies position of the bit to be replaced.3. As an input to the normalize instruction, specifies the number of left shifts to be performed.4. As an output from the normalize instruction, when NORM = L, specifies the number of leading zerosin the data on 015-00.ZN4 is concatenated with ZN3-ZNO for use in 32-bit shift operations as described above. In 16-bitnormalization operations, ZN4 indicates when the input to the shifter is zero. In 16-bit left and right shiftsand in shift and merge operations, a high on ZN4 causes all 16-bits to be filled with the logic level onthe S input.•(J)Q)(.)'SQ)cen...JTEXAS ..INSTRUMENlSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-415

SN54AS897A. SN74AS897A16·BIT PARALLEL/SERIAL BARREL SHIFTERSdescription (continued)control blockThe control block decodes the'M2-MO instruction inputs, 168/328 configuration select, IP and OP dataselect/bit reversal options, and other control inputs and transmits the resulting control signals to the restof the internal logic.instruction setThe' AS897 A can operate in any of the eight user-programmable shift modes shown in Table 1. Selectionof these instructions is controlled by pins M2-MO.'TABLE 1. INSTRUCTION SETIIrCJ)CCD

SN54AS897A, SN74AS897A16·81T PARALLEL/SERIAL BARREL SHIFTERS16031·016 ".16" ....015·00ZLZN3·ZNOZN4,..r;T1 TT1 T- T 1I TI IliT 1 1 1M2·MOCLKSNORM'AS897AOP=HIP = H16B/32B3 -•11' :: 1~iY31·Y16'AS897AOP =HIP =' L16B/32B~11 111 1'AS897AOP = LIP= H16B/32B~16~16FIGURE 1. 32·BIT BARREL St-iIFTER-Y15·YO'AS897AOP = LIP = L16B/328I II*data input/outputData can be input to the chip from two ports: 015-00, which passes data to the zero detector and tothe shifter via the data select and bit-reversal multiplexers, and Y15-YO, which passes data to theregister/counter." Y15-YO is also used to output the shift result from the chip.Data input and output positions in the 32-bit mode are defined by IP and OP (see Table 2). When IP ishigh, the 015-00 port is the most significant input position; when IP is low, the 015-00 input port is theleast significant. If OP is high, the Y15-YO port is the most significant output position; if OP is low, theY15-YO port is the least significant position.U)Q)(,)'>Q)CCJ)...JTABLE 2. IP AND OP CONTROLS16·BIT OPERATION32-BIT OPERATIONSIGNAL(16B/326 - HI (16B/326 - LIIP = L Bit-reversal option off 015-00 is least significant input positionIP = H Bit-reversal option on 015-00 is most significant input positionOP = L 015-00 is shifted Y15-YO is least significant output positionRegister/counter dataOP = His shiftedY15-YO is most significant output positionzero detectorThe zero detector detects the number of leading zeros at the 015-00 input port. If HEX/BIN is high. thezero detector counts only those binary zeros that are part of a leading hexadecimal zero group. For example.given the binary number 0000 0000 0001 0001. the leading.zero co"unt will be decimal 11 if HEX/BINis low and decimal 8 if HEX/BIN is high.If a" zeros are detected at the 0 port, the ZL output transistor will be turned off. If the ZL output pin ispulled up through the recommended pull-up resistor (see pin description tablel. the resulting signal willbe high. If anything other than a zero is detected on the 015-00 inputs. the output transistor will be turnedon; this will pull the ZL signal low.TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75:652-417

SN54AS897A, SN74AS897A16·BIT PARALLEL/SERIAL BARREL SHIFTERSDuring data normalization (M2 = H. M 1 = H. MO = HI. the zero-detector outputs the leading zero countto the ZN4-ZNO I/O ports. provided NORM is low. When NORM is high. ZN4-ZNO act only as inputs inthis mode. For operations other than normalization, the state of NORM is irrelevant.In the data-normalization mode. a high logic level will be output on the ZN4 pin when the 015-00 buscontains all lows and NORM is low (see Table 3).TABLE 3. ZN4 1/0 PORTSIGNAL 1/0IZN4016-BIT CONFIGURATION(16B/328 - HIIn shift-left. shift-right. andshift-and-merge modes. ahigh fills all bits with thelogic level on the S input.Inactive in other modes.In the normalization mode.when NORM = L.indicates when the inputto the shifter is zero32-BIT CONFIGURATION(168/32B - LIWith ZN3-ZNO indicates number of bits to be shifted in shiftoperations and position of bit to be replaced in replace-bit mode.In the normalization mode. when NORM = L. ZN4-ZNO indicatesnumber of leading zeros detected in 015-00 and number of placesto be shifted for normalization.• data selector multiplexerrencCD

SN54Asa97A, SN74Asa97A16·BIT PARALLEL/SERIAL BARREL SHIFTERSmergeDuring the shift and merge instruction (M2 = H, M1 = L, MO = Xl, the merge block DRs the shift resultwith data from the register/counter.S or Z fillDuring bit replacement (M2 = H, M 1 = H, MO = Ll in the 16-bit mode, this block sets the bit specifiedon the ZN3-ZNO inputs with the logic level on the S input. This option works identically in the 32-bit mode,except that the bit to be replaced is specified on the Z4-Z0 inputs. During all other instructions exceptcircular shifts, the S input specifies the logic level that will fill the bit position or positions vacated duringthe shift.Z fill is used in the 32-bit mode to selectively put the device outputs in a high-impedance state. This featureis necessary to properly select the correct bit locations that will combine to form the shifted output. Anexample of a 32-bit circular shift four positions to the right, which illustrates the Z-fill technique, is shownin Figure 2.ZN3-ZNOZN4M2-MOelKSNORM·..·........---- ...·.... 4T31 I1 -MOST SIGNIFICANT HALF LEAST SIGNIFICANT HALF100000000111111111 0000000011111010 I31A16 151T 1 I015·00 015-00 015·00 015-00168/328*168/328*168/328'*IP= H IP = L IP= H IP = LOP=H OP=H OP = L OP = L0168/328V15·VO V15-VO V15-VO V15-VOZZZZOOOOOOO011111 I 1 I1 - 1T-1010ZZZZZZZZZZZZI1111 ZZZZZZZZZZZZI I101000000000111 1111000000001111FIGURE 2. 32-BIT Z-FILL TECHNIQUETRZZZZ000000001111IEllU)Q)o'S;Q)cen-ITEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-419

SN54AS897A, SN74AS897A16·BIT PARALLEL/SERIAL BARREL SHIFTERSSHIFT OPERATION EXAMPLESExamples of ' AS897 A shift instructions are provided in the following paragraphs. Unless otherwise specified,the examples assume a 16-bit configuration.shift left or right (M2 = L, M1 = L, MO = X)ExampleWhen in the shift-right (MO = L) or shift-left (MO = H) modes, ZN3-ZNO define the number of bit positionsto be shifted. If, for example, ZN3-ZNO is equal to a decimal 10, the data selected by OP will be shifted10 bit positions. The positions vacated during the shift operation are filled with the logic level being appliedto the S input. NORM is inactive in all shift modes except normalization and is therefore shown as a don'tcare. If IP is high, the data selected by OP will be bit-reversed before it is passed to the shifter.Shift a 16-bit word on the data bus ten positions to the left and fill the least significant bits with highs.CONTROL SIGNALSSHIFT NUMBER OF BITS BIT DATA BITNORMALIZEINSTRUCTION TO SHIFT REVERSAL SOURCE FILLCON FIGURATIONM2-MO NORM ZN4-ZNO IP OP S 16B/32B001 X 01010 0 0 1 1r- Assume 015-00 contains hex AF50:enCCD

SN54AS897A, SN74AS897A16·BIT PARALLEL/SERIAL BARREL SHIFTERScircular shift left or right (M2 = l, M 1 = H, MO = X)ExampleIn this mode, data selected by OP is circular shifted left (MO = H) or right (MO = l) the number of bitpositions specified by ZN3·ZNO. If, for example, the device is in the circular-shift-right mo~e (MO = l)and ZN3-ZNO contains a decimal five, the data selected by OP will be shifted right five positions.In all shift modes except 16-bit circular, the S input contains the bit used for end fill or bit replacement.In the 16-bit circular-shift mode, the S input controls whether the register/counter will operate as a 16-bitcounter or as a data register. When S is high, the register/counter operates as a 16-bit binary counter;when S is low, the register/counter operates as a 16-bit data latch. Both functions are controlled on thepositive edge of the ClK input. Data on Y15-YO will be latched into the register/counter on the rising edgeof the clock when S is low.Circular shift a 16-bit word in the register/counter five positions to the right.CONTROL SIGNALSSHIFT NUMBER OF BITS BIT DATANORMALIZEINSTRUCTION TO SHIFT REVERSAL SOURCEM2-MO NORM ZN4-ZNO IP OP010 X X0101 0 1LATCH ORCOUNTERS0CONFIGURATION16B/32B1Assume the register/counter contains hex A016:Register/CounterInput Data 11010 00000001 01101Y15-YOResult 110110101000000001CJ)Q)(,)oS;Q)cen...Jshift and merge (M2 = H, M 1 = l, MO X)ExampleIn the shift-and-merge mode, data selected by OP is shifted by OP is shifted left (MO = H) or right (MO = l)the number of positions specified by ZN3-ZNO, bit positions vacated by the shift are filled by the logiclevel on S, and the result is ORed with data in the register/counter.Shift data on the data bus six positions to the left, and fill vacated positions with zeros. Merge the shifteddata with data from the data register.CONTROL SIGNALSSHIFT NUMBER OF BITS BIT DATA ENDNORMALIZEINSTRUCTION TO SHIFT REVERSAL SOURCE FILLCONFIGURA liONM2-MO NORM ZN4-ZNO IP OP S 16B/32B100 X 00110 0 0 0 1TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-421

SN54AS897A, SN74AS897A16·BIT PARALLEL/SERIAL BARREL SHIFTERSAssume 015-00 contains hex 6174 and register/counter contains hex 320B:015-00Input Data1 a 11 a 000 1 a 111 0100 1Shift ResultIntermediateResult1 a 1 01 11 01 0000 0000 1Register/CounterInput Data 10011 0010 0000 10111Y15-YOResult 10111 1111 0000 10111bit replacement (M2 = H, M 1 = H, MO L)rtf)In the bit-replacement mode, data in the bit position specified by ZN3-ZNO is replaced by the logic levelon the S input. If, for example, ZN3-ZNO contains a decimal seven and S contains a logic high, bit 7 ofthe data selected by OP will be set high regardless of its original state. In the following example, OP hasbeen set high to select data from the register/counter. Because IP has been set high, the data will be. bitreversedbefore it enters the shifter ..CCD~.oCDt/)ExampleBit-reverse the data in the register/counter and set bit 7 of the result to zero.CONTROL SIGNALSSHIFTPOSITION OF BIT BIT DATA INSERTNORMALIZEINSTRUCTIONTO BE INSERTED REVERSAL SOURCE BITM2-MONORMZN4-ZNO IP OP S110 XX0111 1 1 0Register/CounterInput Data 1 a 11 a 000 1 00 11 0100 1CONFIGURATION16B/32B1Result after Bit-ReversalIntermediate 10010 1100 1000 01101Result· .Y15-YOResult 1 00 10 11 00 0000 a 11 012-422TEXAS -I/}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54ASB97A, SN74ASB97A16·BI1 PARALLEL/SERIAL BARREL SHIFTERSdata normalization (M2 = H, M 1 = H, MO = L)ExampleThe data-normalization mode shifts data on 015-00 to the left until a high logic level appears in the mostsignificant-bitposition of output Y15-YO if HEX/BIN is low. If HEX/BIN is high, only 4-digit groups containingleading zeros are shifted left. The number of positions shifted to accomplish this is determined by the leadingzerodetector. This count will be output on ZN3-ZNO when the NORM input is low.Since the leading-zero detector counts leading zeros in the 01 5-00 input, the normalization is designedto operate on data from the data bus rather than the register/counter. Therefore OP is set low in the followingexample. The S input is programmed low so that all bit positions vacated during the shift will be filledwith zeros.Perform a hex normalization on a 16-bit data word from the data bus.CONTROL SIGNALSSHIFT NUMBER OF BITS LEADING-ZERO BIT DATANORMALIZEINSTRUCTION TO BE SHIFTED MODE REVERSAL SOURCEM2-MO NORM ZN4-ZNO HEX/BIN IP OP111 0Outputs leadingzero count1 0 0INSERTCONFIGURATIONBITS16B/32B0 1ExampleAssume 015-00 contains hex 002B:Input DataLeading-ZeroCountResult015-0010000 0000 001 0 101 1 1ZN3-ZNO1000Y15-YO11010 1011 0000 00001tnQ)o'>Q)cen..JPerform a binary normalization on a 32-bit word from the data bus.CONTROL SIGNALSSHIFT NUMBER OF BITS LEADING-ZERONORMALIZEBIT .1 DATAINSTRUCTION TO SHIFT MODE REVERSAL SOURCEM2-MO NORM ZN4-ZNO HEX/BIN IP I OPOutputs leading111 00 See Figure 1zero countBITCONFIGURATIONFILLS16B/32B0 0TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-423

SN54AS897A, SN74AS897A16·BIT PARALLELJSERIAL BARREL SHIFTERSAssume 031-00 contains hex 0000 3061:031-016 015-00Input Oata 10000 0000 0000 0000 I 10911 1101 0110 00011Leading-ZeroCountResultZN4-ZNO10010 IY31-Y16·Y15-YO11111 0101 1000 0100 I 10000 0000 0000 00001IEEE floating-point normalizationFloating-point normalization is used to preserve number resolution after subtraction or Some other floatingpointalgorithm that results in orders of magnitude reduction. Three' AS897 A devices can be configuredto convert a 32-bit data word into the IEEE floating-point format shown in Figure 3 .rencCDC;.

SN54AS897A, SN74AS897A16·BIT PARALLEL/SERIAL BARREL SHIFTERSFigure 4 shows the three-device configuration. The limitation of this application is that only 23 bits ofthe 32 bits are used in the significand, and the sign bit must be set from hardware. As an alternate tothe IEEE floating-point format, the same hardware configuration can be used to normalize a ~2-bit dataword resulting in a 32-bit significand and a five-bit exponent .MANTISSA(MSBs)MANTISSA(LSBs)-4:-,16,~ZN4·ZNO516Vs'AS897Ao OP = H YIP = HZN ZL...po16,.... .. .... ....... po .... ....••16,........tS'AS897A15 Y30·Y160 Y ,OP=HIP = L .. ZN ZL .... ..IS'AS897A'8o OP = L Y ,IP = L.. ..ZN ZL.... ....1 .... ...~Y15·Y8'ZLU)Q)o"S;Q)cen...JPREVIOUSEXPONENTSIGNBIT8..., r...rQPp.QtU-.U8 • 23I 1 I8 23FIGURE 4. THREE-DEVICE CONFIGURATION FOR IEEE flOATING-POINT FORMATY30·Y8ITEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-425

SN54AS897A, SN74AS897A16-BIT PARALLEL/SERIAL BARREL SHIFTERSExampleInput data in IEEE floating point formatSign PreviousBit Exponent Mantissa1 I 0010 10011000 1001 0001 0001 0001 00011Input mantissa concatenated with: 0 0000 0000 to D31-DO of the' AS897 AsD31-D16D15-DO100010010 0010 001010010 0010 0000 00001Normalize mantissa and output the leading zero count on ZN4-ZNO.D31-D16 D15-DO ZN4-ZNO11001 0001 0001 000110001 0000 0000 000011000111IPack result in IEEE floating point formatNote: Exponent = old exponent - ZN4-ZNOSignBit Exponent MantissaI 0010 0110 I 001 0001 0001 0001 0001 0000.1absolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, Vee1 ............... , . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. 7 VSupply voltage, Vee2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3 VInput voltage: I/O ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VAll other inputs .......................:........................ 7 VOperating case temperature range: SN54AS897 A . . . . . . . . . . . . . . . . . . . . .. - 55 DC to 125 DCOperating free-air temperature range: SN7 4AS897 A . . . . . . . . . . . . . . . . . . . . . . . . .. 0 DC to 70 DCStorage temperature range ......................................... - 65 DC to 150 DC2-426 TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54AS897A, SN74AS897A16-BIT PARAllEL/SERIAL BARREL SHIFTERSrecommended operating conditionsVCClVCC2VIHVilSupply voltageSupply voltageHigh-level input voltagelow-level input voltageVOH High-level output voltage ZlIOHIOLtwtsuthTATCHigh-level output currentlow-level output currentPulse durationSetup time before ClKiHold time after ClKiOperating free-air temperatureOperating case temperatureZN4-ZNOY15-YOZN4-ZNOZl, Y15-YOClK lowClK highY15-YOstMO, Ml, :vI2t16B/32B~Y15-YO~stMO, Ml, M2t16B/32B~SN54AS897ASN74AS897AMIN NOM MAX MIN NOM MAXUNIT4.5 5 5.5 4.5 5 5.5 V1.9 2 2.1 1.9 2 2.1 V2 2 V10 10;0 1010 1015 1415 1420 180.8 0.8 V5.5 5.5 V-0.4 -0.42 20 00 0-1 .- 2.64 812 24mAmA8 8- 55 0 70 DCnsnsns125 DCt These parameters only apply in the circular mode and with 16B/32B high.t These parameters only apply in the circular mode. Q)electrical characteristics over recommended operating temperature range (unless otherwise noted)PARAMETERTEST CONDITIONSSN54AS897A SN74AS897AMIN Typt MAX MIN Typt MAXVIK VCC = 4.5 V, II = 18 mA -1.5 -1.5 V10H Zl VCC = 4.5 V, VOH = 5.5 V 0.1 0.1 mAAll outputs VCC = 4.5 V to 5.5 V, 10H = -0.4 mA VCC-2 VCC-2 VVOH VCC = 4.5 V, 10H = -1 mA 2.4 3.2Y15-YOVCC = 4.5 V, 10H =, - 2.6 mA 2.4 3.2VOLIIZN4-ZNOZl, Y15-YOVCC = 4.5 V, 10l = 4 mA 0.25 0.4 0.25 0.4VCC = 4.5 V, 10l = 8 mA 0.35 0.5VCC = 4.5 V, IOl=12mA 0.25 0.4 0.25 0.4VCC = 4.5 V, 10l = 24 mA 0.35 0.5I/O ports~ VCC = 5.5 V, VI = 5.5 V 0.1 0.1All others VCC = 5.5 V, VI = 7 V 0.1 0.1I/O ports~ 40 40IIH VCC = 5.5 V, VI = 2.7 V I'mAAll others 20 20III All inputs VCC = 5.5 V, VI = 0.4 V' -0.4 -0.4 mA10§ VCC = 5.5 V, Vo = 2.25 V -30 -112 -30 -112 mAICCl VCC = 5.5 V, See Note 1 100 90 mAICC2 VCC = 2.1 V, See Note 1 180 170 mAt All typical values are at VCC = 5 V, T A = 25 DC.~ For I/O ports, the parameters IIH and III include the offstate output current.§ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.NOTE 1: Supply currents ICCl and ICC2 are measured with MO, Ml, M2, IP, OP, S, ZN3-ZNO, 015-00, and OEY low; 168/32B, NORM,and ClK high; and Y15-YO, Zl, and ZN4 open.UNITVVmAtilQ)(.)'>Cen...JTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-427

SN54AS897A, SN74AS897A16·BIT PARALLEL/SERIAL BARREL SHIFTERSswitching characteristics over recommended operating temperature rangeIIrencm

PRODUCTPREVIEWSN54ALS963, SN54ALS964, SN74ALS963, SN74ALS964DUAL-RANK 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUTS• Serial-to-Parallel and Parallel-to-SerialConversions• Parallel 1/0 Registers• Data Exchangeable Between 1/0 Registerand Shift Register• Choice of Synchronous and/orAsynchronous Clear• Independent or Dual Register Clocking• Functionally Similar to NationalSemiconductor DM74LS962• Dependable Texas Instruments Quality andReliabilitydescriptionThe' ALS963 and' ALS964 each contain an 8-bitshift register in parallel with an 8-bit I/O register.In addition to serial-to-parallel and parallel-toserialconversions, these devices are capable ofexchanging data between the shift and I/Oregisters. Control lines determine the mode ofoperation as shown in the function table.The 'ALS963 features individual shift and I/Oregister clock inputs whereas the 'ALS964features simultaneous register clocking througha single clock input. Clocking in both cases isachieved by positive transitions at the clockinputs.The clear function for the 'ALS963 issynchronous (active high). The 'ALS964features active-high synchronous andasynchronous clearing.The SN54ALS963 and SN54ALS964 arecharacterized for operation over the full militaryof - 55°C to 125°C. The SN74ALS963 andSN74ALS964 are characterized for operationfrom O°C to 70°C.SN54AlS963 ... JT PACKAGESN74AlS963 ... OW OR NT PACKAGE(TOP VIEW)DE vccSERINA/OAGINS/OsG2-TC/OCSClR 0100G'I=2E/OEGSHF/OFSEROUTG/OGH/OHGNDClK1SN54AlS963 ... FK PACKAGESN74AlS963 ... FN PACKAGE(TOP VIEW)2

SN54ALS963, SN74ALS963DUAL·RANK 8·BIT SHIFT REGISTERS WITH 3·STATE OUTPUTS. AlS963 logic symboltCLK2 ~"'---C>Gl-2GSHSERINrOOCCDEN..a/~ ..SE ROUT2-430TEXAS l!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

· SN54ALS963, SN74ALS963DUAL·RANK 8·BIT SHIFT REGISTERS WITH 3·STATE OUTPUTS, ALS963 gate·level logic diagram (positive logic)OE~(l_)------------------------r-_-_-q~~~ __________________________ ~GIN (3)-G2-_1~(4~)--------------~)-______ ~~SE R I N ..;..(2_) ------i-+-+--i-t----i....-../B/OA, I C/OC", 5 SECTIONS (16) 0/°0, NOT SHOWN (15) E/OEi(14) F/OF(13) G/OGItn(1)0'S;(1)Cen..JH/OHSEROUTTEXAS -I.!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652·431

SN54ALS963, SN74ALS963DUAL·RANK 8·BIT SHIFT REGISTERS WITH 3·STATE OUTPUTS'ALS963FUNCTION TABLEr(J)cCD

...SN54ALS964, SN74ALS964DUAL·RANK 8·BIT SHIFT REGISTERS WITH 3·STATE OUTPUTSI ALS964 logic symbol ttThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12., ALS964 register·level logic diagram(f)Q)(,)'>Q)oen-lCLK GSH Gl-2 SCLR ACLROEREG 2 REG 1 BUFFERSSRG8 t>R. R -~ 8."--- 3R 2.3RENr-...M1 L1:::::. M1-----.1'--.. M2"" M2 -C3fT,2-C38/ ~SERIN 1,2,30, 1,30r 1,30 - 2,30r .8/, ~I~8/,·8/;'SE ROUT- TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-433

SN54ALS964, SN74ALS964DUAL-RANK 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUTS, ALS964 gate-level logic diagram (positive logic)OE ~(~11 __________________________ ~GIN (3) r--~L_j----:------------------------,(4)G2·1 --------------~~~----~~ClKSE R I N ...;.:;.'-------t-t-HH----L-~rC/)CCD

SN54ALS964, SN74ALS964DUAL-RANK 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUTS'ALS964FUNCTION TABLEINPUTSOE GIN G2-1 Gl-2 GSHH H H H HL H H H HX L H H H.H H L H HL H L H HX L L H HH H H L XL H H L XX L H L XH H L L XL H L L XX L L L XH H H H LL H H H LX L H H LH H L H LL H L H LX L L H LX H X X XX X X X XX L X X XCLKXXiiiiiiiiiiiiiiiiiXiACLRLLLLLLLLLLLLLLLLLLLHLSCLRLLLLLLLLLLLLLLLLLLHXHA/QATHROUGHH/QHHI-ZOUTPUTINPUTHI-ZOUTPUTINPUTHI-ZOUTPUTINPUTHI-ZOUTPUTINPUTHI-ZOUTPUTINPUTHI-ZOUTPUTINPUTINPUTOPERATION OR FUNCTIONAll data stableAll data stableEnter data from 1/0 into Reg 1Copy data from Reg 2 to Reg 1Copy data from Reg 2 to Reg 1Reg 1 ORs data from Reg 2 and 1/0Copy data from Reg 1 to Reg 2Copy data from Reg 1 to Reg 2Copy data from Reg 1 to Reg 2,enter new data from I/O into Reg 1Exchange data between registersExchange data between registersCopy data from Reg 1 to Reg 2,Reg 1 ORs data from Reg 2 and 1/0Shift data in Reg 2Shift data in Reg 2Shift data in Reg 2, enter new datafrom I/O into Reg 1Copy data from Reg 2 to Reg 1,shift data in Reg 2Copy data from Reg 2 to Reg 1,shift data in Reg 2Reg 1 ORs data from Reg 2 and 1/0,shift data in Reg 2Synchronously clear Reg 1 and Reg 2Asynchronously clear Reg 1 and Reg 2Enter data from 1/0 into Reg 1 andsynchronously clear Reg 2•(f)Q)CJ'SQ)c(J)...JTEXAS l!}INSTRUMENTSPOST OFFICE BOx 225012 • DALLAS, TExAS 752652-435

SN54ALS963, SN74ALS963DUAL·RANK 8·BIT SHIFT REGISTERS WITH 3·STATE OUTPUTS, ALS963 typical sequenceIllustrated below is the following sequence:1. Clear both registers to zero.2. Input 0011 0011 in Reg 1.3. Transfer 0011 0011 from Reg 1 to Reg 2.4. Input 0111 0111 into Reg 1.5. Shift contents of Reg 2, SERIN = 06. Shift contents of Reg 2, SERIN = 17. Exchange contents of Reg 1 with Reg 2.OE-------~GINIIrrncCDS.oCDtJ)GSH~ ~------------------------------------------------IILJLJG2·1LJCLKl----~CLK2----~SERIN ________ ~--------------~--~--~----------~r----l~--------ISEROUT~IA/OA·H/OH ~ 00000000 H 00110011 1011101111 1011101111 11001101I. .I'--'I~ INPJT ----!---.I..-- HI'Z--'I+-OUTPUT~II OUTPUT HI·Z I I ICONTENTS ~ I I 1OF REG 1 ~ 00000000 I 00110011 1 01110111 I 11001101I I I II I I ICONTENTS OF REG 2 ~ ~~~~~ ____ ~~~~ 00000000 __ jl~~I[J~I~~:r~~~~][~~~I:~~~~:::I 00110011 01110111iCLEAR REG 1LOAD LOADAND REG 2 REG 1 REG 2iSERIN = 0iSHIFTREG 2SERIN ~ 12-436TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54ALS964, SN74ALS964DUAL·RANK 8·BIT SHIFT REGISTERS WITH 3·STATE OUTPUTS'ALS964 typical sequenceIllustrated below is the following sequence:1. Asynchronously clear Reg 1 and Reg 2 to zero, operate, then synchronously clear.2. Input 0011 0011 into Reg 1.3. Transfer 0011 0011 from Reg 1 to Reg 2 and input 0111 0111 into Reg 1.4. Shift contents of Reg 2, SERIN = 05. Shift contents of Reg 2, SERIN = 16. Exchange contents of Reg 1 with Reg 2.OE _______..JISCLR ~~ ____________________________________________ __ACLR ~~~ _________________________________________ __CLK --~JSERIN ~ ___________________ r-1,-_____ __(/)Q)(,)0$Q)cen..JSEROUT ~ ~A/OA·H/oH mmooo 0000~~0~0~1~10~0~1~1 [I =~0~1~11~0~1I11~=:Ir--------{I=I11~0~O I11~0~1 =:I+-OUTPUt-4 1·4---INPUT----··I*---HI.Z---.·I*-OUTPUT--+jIICONTENTS ~ ~OFREG1 ~ ~00000000 100110011 I 01110111 1100 1101I ICONTENTS m m 00000000 I 00110011 101100110 111001101 1 0111 0111OF REG 2 "+f---J~~f--"""::':~:="""'!""t--~t..;.;:;.:..:...:.;..;.;~t...::.:.:..:~;...t~;.;;...:..;.;~t----ASYN SYN LOAD LOAD REG 1 SHIFT SHIFT EXCHANGECLEAR CLEAR REG 1 AND REG 2 REG 2 REG 2SERIN = 0 SERIN=1TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • OALLAS, TEXAS 752652-437

SN54ALS963, SN54ALS964, SN74ALS963, SN74ALS964DUAL·RANK 8·BIT SHIFT REGISTERS WITH 3·STATE OUTPUTSabsolute maximum ratings over operating free·air temperature range (unless otherwise noted)Supply voltage. Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VInput voltage: All inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VI/O ports ..................................................... 5.5 VOperating free-air temperature range: SN54ALS963. SN54ALS964 . . . . . . . . . .. - 55°C to 125°CSN74ALS963. SN74ALS964 ............... ooe to 70°CStorage temperature range ......................................... - 65°C to 150 °e'ALS963 recommended operating conditionsrCJ)CCD

SN54ALS963, SN54ALS964, SN74ALS963, SN74ALS964DUAL·RANK 8·BIT SHIFT REGISTERS WITH 3·STATE OUTPUTSelectrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)SN54ALS963SN74ALS963PARAMETER TEST CONDITIONS SN54ALS964 SN74ALS964 UNITMIN Typt MAX MIN Typt MAXVIK Vee = 4.5 V, II = -18 mA - 1.5 -1.5 VVee = 4.5 V to 5.5 V, IOH = -0.4 mA Vee- 2 Vee- 2VOH Vee = 4.5 V, 10H = -1 mA 2.4 3.3 VVOLIISEROUTQA thru QHVee = 4.5 V, 10H = -2.6 mA 2.4 3.2Vee = 4.5 V, 10L = 8 mA 0.25 0.4 0.25 0.4Vee = 4.5 V, 10L = 16 mA 0.35 0.5Vee - 4.5 V, 10L = 12 mA 0.25 0.4 0.25 0.4Vee = 4.5 V, IOL = 24 mA 0.35 0.5A thru H Vee = 5.5 V, VI = 5.5 V 0.1 0.1Any other Vee = 5.5 V, VI = 7 V 0.1 0.1IIHl Vee = 5.5 V, VI = 2.7 V 20 20 p.AIlL l Vee = 5.5 V, VI = 0.4 V -0.1 -0.1 mAlo§ Vee = 5.5 V, Vo = 2.25 V -3q -112 -30 -112 mAleeOutP!Jts high'ALS963 Vee = 5.5 V Outputs low mAOutputs disabledOutputs high'ALS964 Vee = 5.5 V Outputs low mAOutputs disabledVmAEJIt/)Q)CJ"S;t All typical values are at Vee = 5 V, T A = 25 ce. Q)lFor 110 ports (QA throuh QH). the parameters IIH and IlL include the off-state output current.C, §The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.en...JTEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-439

SN54ALS963, SN54ALS964, SN74ALS963, SN74ALS964DUAL·RANK 8·BIT SHIFT REGISTERS WITH 3·STATE OUTPUTSIIrCJ'JCCD

SN74ALS990, SN74ALS9918·BIT D·TVPE TRANSPARENT READ·BACK LATCHESD2835, APRIL 1984-REVISED JANUARY 1986• 3-State I/O-Type Read-Back Inputs• Bus-Structured Pinout• Choice of True or Inverting Logic'ALS990 ... True Outputs'ALS991 ... Inverting Outputs• Package Options Include Both Plastic andCeramic Chip Carriers in Addition to Plasticand Ceramic DIPs• Dependable Texas Instruments Quality andReliabilitydescriptionThese 8-bit latches are designed specifically forstoring the contents of the input data bus plusproviding the capability of reading-back thestored data onto the input data bus.The eight latches of the I ALS990 and I ALS991are transparent Ootype. While the enable (C) ishigh, the Q outputs of the I ALS990 will followthe data (0) inputs. For the 'ALS991, the Qoutputs will provide the complement of what isapplied to its data (0) inputs.Read-back is provided through the read-backcontrol input (OERB). When the control is takenlow, the data present at the output of the datalatches will be allowed to pass back onto theinput data bus. When it is taken high, the outputof the data latches will be isolated from the data(0) inputs. The read-back control does not affectthe internal operation of the latches; however,precautions should be taken not to create a busconflictsituation.The SN74ALS990 and SN74ALS991 arecharacterized for operation from boc to 70 o C.SN74ALS990 ... OW OR N PACKAGE(TOP VIEW)VeeOERB10 1020 2030 3040 4050 5060 6070 7080 80GNO eSN74ALS990 ... FN PACKAGE(TOP VIEW)00 Uo 0 ~ UON~O>~ 13 2 1 20 1930 18 2040 17 3050 16 4060 15 5070 14 609 1011 12 13OOUOOOOZ 001"-(:JSN74ALS991 ... OW OR N PACKAGE(TOP VIEW)veeOERB10 1620 2030 3040 4050 5660 6070 7080 80GNO eSN74ALS991 ... FN PACKAGE(TOP VIEW)C/)Q)CJ'SQ)c(J)...J30405000CI: U00 w UION""O>~ 13 2 1 20 199 1011 12 1300 UIOIOOOZ 001"-(:J18 2Q17 3616 4015 5014 60PRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments~~~~~:~~ii;a{~~I~~'; ~!~~~~ti~; ~Io~:~:~:t~:s~s notTEXAS -1.!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265Copyright © 1984, Texas Instruments Incorporated2-441

SN74ALS990, SN74ALS9918·BIT D·TVPE TRANSPARENT READ·BACK LATCHESlogic symbols t'ALS990'ALS991J tTh;,10203D4050607080(1)(11)NEN2~1(2)10 (19)'V2(3) 4-(18)(4) =(171p(5) .(16)(6) ..(15)(7)-(14)(8)(13)(9)(12)J'-.J EN2OERB(1)(11)CL{110(2)1010l.- 'V 2 ..20 20(3) ....(4) - :30 3D(5) ....40 40(6)50 50 ..60 60171(8)70 70(9)80 80"mbol ;,;, ",,,d,,,, w;,h ANSI/IEEE Std 91-t984 "d lEe MU,,,'oo 617-12r-..;. (19ir--.... (18)c--.... (171(16)r-.. (15)r-.. (14)r-.. (13)r---., (12)rencCD

SN74ALS990, SN74ALS9918·BIT D·TVPE TRANSPARENT READ·BACK LATCHESlogic diagrams (positive logic)'ALS990'ALS991c10-~-_+~~10204030403Q4QEllU)Q)(,)0$Q)CCJ)...Jsososososo70----+-.,7070--.:.:::.:..----+-~so -~-_+____ ~soso ~~-_+____ ~soTEXAS -1!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-443

SN74ALS990, SN74ALS9918·BIT D·TVPE TRANSPARENT READ·BACK LATCHEStiming diagramDATA BUS------II~------~------~~~~------------~~~cOERBI I I I~~ ~~a ______ ~X--------------------------------~x:==t This setup time ensures the read back circuit will not create a conflict on the input data bus.absolute maximum ratings over operating free·air temperature range (unless otherwise noted)Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. 7 VInput voltage, (OERS and e inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VVoltage applied to D inputs ............................................. . . . .. 5.5 VOperating free-air temperature range SN74ALS990, SN74ALS991 ................ ooe to 70 0 eStorage temperature range ......................................... - 65°C to 150 °eEI recommended operating conditionsrenCen

SN74ALS990, SN74ALS991,8·BIT D·TYPE TRANSPARENT READ·BACK LATCHESelectrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)PARAMETER TEST CONDITIONS MIN Typt MAX UNITVIK Vee = 4.5 V, II = -18 mA -1.2 VAll outputs Vee = 4.5 V to 5.5 V, IOH = -0.4 mA Vee- 2VOHVOLIIIIHIlLa or a Vee = 4.5 V, IOH = -2.6 mA 2.4 3.2DaorOYee = 4.5 V, IOL = 4 mA 0.25 0.4Vee = 4.5 V, IOL = 8 mA 0.35 0.5Vee = 4.5 V, IOL = 12 mA 0.25 0.4Vee = 4.5 V, IOL = 24 mA 0.35 0.5OERB, e Vee = 5.5 V, VI = 7 V 0.1D inputs Vee = 5.5 V, VI = 5.5 V 0.1OERB, eVee = 5.5 V, VI = 2.7 V20{LAD inputs t 20OERB, eVee = 5.5 V, VI = 0.4 V-0.1mAD inputs t -0.1lo§ Vee = 5.5 V, Vo = 2.25 V -30 -112 mAlec'ALS990'ALS991Vee = 5.5 V, OERB higha outputs high 27 50a outputs low 40 70a outputs high 25 45a outputs low 45 75t All typical values are at Vee = 5 V, T A = 25 ae.tFor 1/0 ports, the parameters IIH and IlL include the off-state output current.§The output conditions have been chosen to produce a current that closely approximates one half the true short-circuit output current, lOS.VVmAmAII(/)Q)ooSQ)cen..JTEXAS -I!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-445

SN74ALS990, SN74ALS9918-BIT D-TVPE TRANSPARENT READ-BACK LATCHES'ALS990 switching characteristicsPARAMETERtpLHtpHLtpLHtpHLtentdisFROM(INPUT)DCOERBTO(OUTPUT)QQDVee - 5 V,eL - 50 pF,TA = 25°e,See Figures 1 and 2MIN TYP MAX8 1411 2213 2216 2312 1810 18Vee = 4.5 V to 5.5 V,eL -50 pF,TA - ooe to 70 o e, UNITSee Figures 1 and 2MINMAX4 175 246 268 264 214 19nsnsnsten = tpZL or tpZHtdis = tPLZ or tpHZ'ALS991 switching characteristicsEIrC/)CCDc:::n'CDenPARAMETERtpLHtpHLtpLHtpHLtentdisten = tpZL or tpZHtdis = tpLZ or tpHZFROM(INPUT)DCOERBTO(OUTPUT)Q5DVee = 5 V,CL - 50 pF,TA = 25°e,See Figures 1 and 2MIN TYP MAX12 159 1217 2114 1812 178 12Vee = 4.5 V to 5.5 V,CL = 50 pF,TA = ooe to 70 o e,See Figures 1 and 2MINMAX4 204 159 287 234 224 17UNITnsnsns2-446 TEXAS l!IINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN74ALS990, SN74ALS9918-BIT D-TVPE TRANSPARENT READ-BACK LATCHESPARAMETER MEASUREMENT INFORMATIONFROM OUTPUT;q: TESTUNDER TESTPOINT(See Note A)CL 5000.,..LOAD CIRCUIT FORQ OR IT OUTPUTSFiGURE 1NOTE A: CL includes probe and jig capacitance.7V~S1FROM OUTPUT -41---4-.....-UNDER TESTCL(See Note A)1 kOLOAD CIRCUIT FOR 0 OUTPUTSFIGURE 2TESTPOINTTIMINGINPUTDATAINPUT./. 3.5 V/,1.3 V___...J :- - - - - - -- 0.3 V"'tsu""'th~~'-'l--:/- 3.5V~1.3V ~0.3VVOLTAGE WAVEFORMSSETUP AND HOLD TIMESINPUT ~-1.;V- - - 3.5V~I • .:IV ~0.3VtpLH~ ~tpHLIN.PHASE ~I! : -!- - VOHOUTPUT I . 1.3 V : 1.3 V. : VOLtPHL-l4----+i ~tpLHIIOUT -OF·PHASE ~ 1 ., \I Jr VOH~~.~vOUTPUT(See Note D) - - - VOLVOLTAGE WAVEFORMSPROPAGATION DELAY TIMES~~~~~LEVEL ~ 3.5VIf.-- tw ---.:0.3 V~~~~~EVEL~~ tw_~y---- 3.5V~ __ _VOLTAGE WAVEFORMSPULSE WIDTHSOUTPUTCONTROL 1.3 V 1.3 V0.3V3.5 V(low-level I -:-------- 0.3Venabling) tpZL ~ ---' If- tPLZI I III I I : '" 3.5 VWAVEFORM1~1.3Vi :~3VS1. CLOSED i ~-=-------:.I=-~ VOL(See Note B) tpZH ~ -..: !f-tPHZ T------L_ VWAVEFORM 2 I -----f- OHS10PEN1.3 V(See Note B) . . 0.3 V "'0 VVOLTAGE WAVEFORMSENABLE AND DISABLE TIMES, THREE-STATE OUTPUTSEll(J)Q)CJos:Q)C(J)...JNOTES:B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.C. All input pulses have the following characteristics: PRR ~ 1 MHz, tr ~ tf = 2 ns, duty cycle ~ 50%.D. When measuring propagation delay times of 3-state outputs, switch S 1 is open.TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-447

2-448

SN74ALS992, SN74ALS9939-BIT D-TVPE TRANSPARENT READ-BACK LATCHESWITH 3-STATE OUTPUTS02836, APRIL 1984~REVISED JANUARY 1986• 3-State I/O-Type Read-Back Inputs• Bus-Structured Pinout• Choice of True or Inverting Logic'ALS992 . . . True Outputs'ALS993 ' ... Inverting Outputs• Designed with 9 Bits for Parity Applications• Package Options Include Both Plastic andCeramic Chip Carriers in Addition to Plasticand Ceramic DIPs• Dependable Texas Instruments Quality andReliabilitydescriptionThese 9-bit latches are designed specifically forstoring the contents of the input data bus plusproviding the capability of reading-back thestored data onto the input data bus. In addition,they provide a 3-state buffer-type output and areeasily implemented in parity applications.The nine latches of the' ALS992 and' ALS993are transparent D-type. While the enable (C) ishigh, the 0 outputs of the' ALS992 will followthe data (0) inputs. For the 'ALS993, the Qoutputs will provide the complement of what isapplied to its data (0) inputs. On both devices,the 0 ~r 5. outputs will be in the 3-state conditionwhen output enable OEO is high.Read-back is provided through the read-backcontrol input (OERS)' When the control is takenlow, the data present at the output of the datalatches will be allowed to pass back onto theinput data bus. When it is taken high, the outputof the data latches will be isolated from the data(D) inputs. The read-back control does not affectthe internal operation of the latches; however,precautions should be taken not to create a busconflictsituation.The SN74ALS992 and SN74ALS993 arecharacterized for operation from 0 °C to 70°C.SN74AlS992 ... ow OR NT PACKAGE(TOP VIEW)OERBVee1Q2Q3D3Q40 4Q5Q6Q70 7Q80 8Q90 10 15 9QeLR 11 14 OEQGNO 12 13 eSN74AlS992 ... FN PACKAGE(TOP VIEW)4 3 2 1 28 27 26121314151617 18SN74AlS993 ... ow OR NT PACKAGE(TOP VIEW)OERBvee10203D 3040 4050 5060 6070 7080 8090 10 15 90eLR 11 14 OEQGNO 12 13 eSN74AlS993 ... FN PACKAGE(TOP VIEW)ICDa: UCl Cl UJ U UloloN-OZ>_N4 3 2 1 2827 26U)Q)CJ"S;Q)cen..J12131415 161718PRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments~t~~~:~~i~ar~:1~1e ~!:~~~ti~f ~Io::~:~:t::s~s notTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265NC-No internal connectionCopyright © 1984: Texas Instruments Incorporated2-449

SN74ALS992, SN74ALS9939·BIT D·TVPE TRANSPARENT READ·BACK LATCHESWITH 3·STATE OUTPUTSlogic symbols t10203D4050(14)(1)(11) .......(13)(2)1.-(3) ... .(4)(5)(6)(7) ..60(8)70(9)80(10) ...90'" EN3.......EN2R..,C11029'ALS992r-39IIr tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.(J) Pin numbers are for OW and NT packages.oCD

SN74ALS992, SN74ALS9939·BIT D·TYPE TRANSPARENT READ·BACK LATCHESWITH 3·STATE OUTPUTSlogic diagrams (positive logic)'ALS992'ALS993OEOOERBelR ....:...:..~-

SN74ALS992, SN74ALS9939·BIT D·TYPE TRANSPARENT READ·BACK LATCHESWITH 3·STATE OUTPUTStiming diagramDATA BUS ___-I¥ INPUT DATA ~ READ BACK }---{\.__I_N_PU_T_D_A_T_A __I+--tsu---'I"--th---'IC I LI.tpd./I+tpd.la------------~--*~ ____________________________________________eLR = H, om =L"This setup time ensures the read back circuit will not create a conflict on the input data bus.' ___ ~IrOOCCD

SN74ALS992, SN74ALS9939-BIT D-TYPE TRANSPARENT READ-BACK LATCHESWITH 3-STATE OUTPUTSelectrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)PARAMETER TEST CONDITIONS MIN TYPt MAX UNITVIK Vee = 4.5 V, II = -18 mA -1.2 VAll outputs Vee = 4.5 V to 5.5 V, 10H = -0.4 mA Vcc- 2VOHVQ or Q Vee = 4.5 V, IOH = -2.6 mA 2.4 3.2VOLDQ or ITVee = 4.5 V, 10l = 4 mA 0.25 0.4Vee = 4.5 V, 10l = 8 mA 0.35 0.5Vee = 4.5 V, IOl=12mA 0.25 0.4Vee = 4.5 V, IOl = 24 mA 0.35 0.5Vee = 5.5 V, Vo = 2.7 V 20~ Q or ITIOZl Vee = 5.5 V, Vo = 0.4 V -20p.AIID inputs Vee = 5.5 V, VI = 5.5 V 0.1All other~Vee = 5.5 V, VI = 7 V 0.1mAIIHo inputs t 20Vee = 5.5 V, VI = 2.7VAll other20p.AIIIo inputs t -0.1Vee = 5.5 V, VI = 0.4 VAll other -0.1mAlo§ Vee = 5.5 V, Vo = 2.25 V -30 -112 mAleeQ outputs high 30 50'AlS992 Vee = 5.5 V, OERB high Q outputs low 50 80 mAQ outputs disabled 35 55IT outputs high 30 50'AlS993 Vee = 5.5 V, OERB high Q outputs low 52 82 mAQoutputs disabled 40 60t All typical values are at Vee = 5 V, T A = 25°e.t For I/O ports, the parameters IIH and III include the off-state output current.§ The output conditions have been chosen to produce a current that closely approximates one half the true short-circuit output current, lOS.VenCD(.)'S;Q)cen...JTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-453

SN74ALS992, SN74ALS9939·BIT D·TVPE TRANSPARENT READ·BACK LATCHESWITH 3·STATE OUTPUTSI ALS992 switching characteristics (see Figure 1)Vee - 5 V.Vee - 4.5 V to 5.5 V.PARAMETERFROM(INPUT)TO(OUTPUT)eL - 50 pF.TA -25 D eeL - 50 pF.TA = oDe to 70 D eUNITMINTYPMAXMINMAXtpLHtpHLtpLHtpHLtpHLtpHLtentdistentdisDCCLROERBOEQQQQDDQ7 109 1312 1515 1912 1615 2211 176 1111 166 103 144 166 208 256 208 264 212 144 181 14nsnsnsnsns'ALS993 switching characteristics (see Figure 1)EIPARAMETERFROM(INPUT)TO(OUTPUT)MINVee - 5 v.CL - 50 pF.TA - 25 D CTYP MAXVee = 4.5 V to 5.5 V.eL = 50 pF.TA = oDe to 70 D eMINMAXUNITtpLHtpHLtpLHtpHLtPLHtpLH,tentdistentdisD 0:C 0:QCLRDOERBDOEQ 0:11 148 1116 2013 1610 1315 2211 176 1111 166 106 204 159 287 225 178 264 212 144 201 12nsnsnsnsnsten = tpZH or tpZLtdis = tpHZ or tPLZ2-454 TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN74ALS992, SN74ALS9939·BIT D·TYPE TRANSPARENT READ·BACK LATCHESWITH 3·STATE OUTPUTSPARAMETER MEASUREMENT INFORMATION7V~Sl7V~SlFROM OUTPUTTESTUNDER TEST -1~-4~-1~- POINTCL500 n(See Note A)1 k!lFROM OUTPUT --4_~""'__- TESTUNDER TESTPOINTCL(See Note A)1 k!lLOAD CIRCUIT FORQ OR IT OUTPUTSLOAD CIRCUIT FOR 0 OUTPUTSTIMINGINPUTDATAINPUT./ 3.5V/." 1.3 V___ -J : - - - - - - - - 0.3 V:+-tsu~th~-,----3.5V1.3V 1.3V0.3V~.VOLTAGE WAVEFORMS. SETUP AND HOLD TIMESINPUT ~-1.;V- - - 3.5V..../f1.~V ~ 0.3VtPLH~ ~tpHLIN-PHASE ~I! : -!- - VOHOUTPUT I 1.3 V : 1.~ V. I VOLtPHL-44--+t ~tPLHIIOUT-OF-PHASE ~ '"'' v.:-: VOHOUTPUT ~~.~V(See Note D). . ~ - - VOLVOLTAGE WAVEFORMSPROPAGATION DELAY TIMES~~~~~LEVEL ~ 3.5V14---- tw -.; 0.3 V~tw~ 3.5VLOW·LEVEL I 1.3 V 1.3 V ___ _PULSE0.3 VOUTPUTVOL TAGE WAVEFORMSPULSE WIDTHSCONTROL· 1.3 V 1.3 V3.5 V/low-level I -i-------- 0.3Venabling) tpZL~ ..... If--tPLZ. I I I II I I : .. 3.5 VWAVEFORM 1 ~1.3V ! :~3VSl CLOSEDi ~------:.::.~== VOL(See Note B) tPZH~ -..: rf-tPHz T_____ t_ VWAVEFORM 2 I ~ -----f- OHS10PEN(See Note B)1.3 V0.3 V "0 VVOLTAGE WAVEFORMSENABLE AND DISABLE TIMES. THREE·STATE OUTPUTStJ)Q)CJ":;Q)CCJ)..JNOTES: A. CL includes probe and jig capacitance.B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.C. All input pulses have the following characteristics: PRR :5 1 MHz, tr = tf = 2 ns, duty cycle = 50%.D. When measuring propagation delay times of 3-state outputs, switch S 1 is open.FIGURE 1TEXAS -1.!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-455

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SN74ALS994, SN74ALS9951 U·BIT D·TVPE TRANSPARENT READ·BACK LATCHESD2856. OCTOBER 1984-REVISED JANUARY 1986• 3-State I/O-Type Read-Back Inputs• Bus-Structured Pinout• Choice of True or Inverting Logic'ALS994 ... True Outputs'ALS995 ... Inverting Outputs• Package Options Include Both Plastic andCeramic Chip Carriers in Addition to Plasticand Ceramic DIPs• Dependable Texas Instruments Quality andReliabilitydescriptionThese 1 O-bit latches are designed specifically forstoring the contents of the input data bus plusproviding the capability of reading-back thestored data onto the input data bus.The ten latches of the' ALS994 and' ALS995 aretransparent Ootype. While the enable (C) is high,the Q outputs of the 'ALS994 will follow thedata (0) inputs. For the' ALS995, the Q outputswill provide the inverse of what is applied to itsdata (0) inputs.Read-back is provided through the read-backcontrol input (OERB). When the control is takenlow, the data present at the output of the datalatches will be allowed to pass back onto theinput data bus. When it is taken high, the outputof the data latches will be isolated from the data(0) inputs. The read-back control does not affectthe internal operation of the latches; however,precautions should be taken not to create a busconflictsituation.The SN74ALS994 and SN74ALS995 arecharacterized for operation from 0 °C to 70°C.SN74ALS994 ... OW OR NT PACKAGE5DNe6D7D8D(TOP VIEW)VeeOERB1D 1020 203D 304D 405D 506D 607D 708D 809D 9010D 100GND eSN74ALS994 ... FN PACKAGE(TOP VIEW)I cc UClClffi. UUddN ..... QZ> ..... N4 3 7 1 28272625 3024 407891011232221201950NC60708012 131415161718ClClClUuddcn ozz 00')..... (,9NC-No internal connection.(/)Q)(.)os:Q)oen..JPRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments~~~~~:~~i~a{~:I~~'; ~!:~~~ti:r ~~o~:::~:t::s~s not"'i2. Copyright © 1984. Texas Instruments IncorporatedTEXAS V .INSTRUMENTS 2-457POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN74ALS994, SN74ALS99510·BIT D·TVPE TRANSPARENT READ·BACK LATCHESSN74ALS995 ... ow OR NT PACKAGEOERB102030(TOP VIEW)Vcc10203040506570 7080 8590 95100 100GNO"-10...__........CNC-No internal connectionSN74ALS995 ... FN PACKAGE30 540 650 7NC 860 970 1080 11(TOP VIEW)l co U00 ffi U UIOION..-OZ>..-N4 3 2 1 28272612 131415161718o 0 0 U UIO 10mozz Om"-(.9 ...25 3024 4523 5022 NC21 6620 7019 80IIrencCD

SN74ALS994, SN74ALS99510·BIT D·TVPE TRANSPARENT READ·BACK LATCHESlogic diagrams (positive logic)'ALS994'ALS995OERBcc10 --.:.:(2:.:.) ___ -4-...... ~10 --.:.:(2:..:) ___ -+ ...... -120--:(3~) ___-+...... ~20 --:(.=.;3):.....-__ -4-...... ~30--:(4~)----+ ...... ~30--:(~4) ___ -+~~4050(5)(6)404050 50(5)(6)4050enQ)(J'>Q)Cen..J60(7)60 60(7)60(8)70--....:....:.....----+-.....70 70--:(.=.;8)~---4-...... ~80~(~9) ___ _4~~80~(~9)~ __ _+~~ 8090 _(1_0..;,.) ___ -+-~90~(~10~)---~~ 90100 -...:..(1:....:1.:...) ___ +-~100 ~(..;,.11;.:.) ___........ ~ 100Pin numbers shown are for DW and NT packages.TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-459

SN74ALS994, SN74ALS99510·BI1 D·TYPE TRANSPARENT READ·BACK LATCHEStiming diagramDATA BUS ___... ¥ INPUT DATA AAffi READ BACK >----

SN74ALS994, SN74ALS99510·BI1 D·TVPE TRANSPARENT READ·BACK LATCHESelectrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)PARAMETER TEST CONDITIONS MIN Typt MAX UNITVIK Vee '" 4.5 V, II = -18 mA -1.2 VAll outputs Vee'" 4.5 V to 5 5 V, 10H '" -0.4 mA VCc- 2VOHVo or 0 Vee == 4.5 V, 10H == -2.6 mA 2.4 3.2VOLIIDo or 0:Vee == 4.5 V, 10L == 4 mA 0.25 0.4Vee == 4.5 V, 10L == 8 mA 0.35 0.5Vee == 4.5 V, 10L == 12 mA 9. 2 5 0.4Vee == 4.5 V, 10L == 24 mA 0.35 0.5OERB, e Vee == 5.5 V, VI == 7 V 0.1D inputs Vee == 5.5 V, VI == 5.5 V 0.1IIHOERB, eVee == 5.5 V, VI == 2.7 V20p.AD inputs l 20IlLOERB, eVee == 5.5 V, VI == 0.4 V-0.1mAD inputs l -0.1lo§ Vee == 5.5 V, Va == 2.25 V -30 -112 mAo outputs high 30 50'ALS994Vee == 5.5 V, o outputs low 52 82leemAOERB high o outputs high 30 50'ALS995o outputs low 55 85t All typical values are at Vee == 5 V, T A == 25°e.l For 1/0 ports, the parameters IIH and IlL include the off-state output current.§ The output conditions have been chosen to produce a current that closely approximates one-half the true short-circuit output current, lOS.VmAtnQ)(,)oSQ)cen..JTEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-461

SN74ALS994, SN74ALS99510·BIT D·TYPE TRANSPARENT READ·BACK LATCHES, ALS994 switching characteristics (see Figure 1)Vee - 5 V.FROM TO eL - 50 pF.PARAMETER(INPUT) (OUTPUT) TA a 25 D eMIN TYP MAXtpLH7 10DQtPHL 11 15tPLH12 16CQtpHL 16 21ten11 17OERBDtdis 9 13, ALS995 switching characteristics (see Figure 1)Vee - 4.5 V to 5.5 V.eL - 50 pF.TA - oDe to 70 D eMINMAX3 144 186 218 274 212 16UNITnsnsnslEIrenCCDc::O·CD(J)PARAMETERtpLHtPHLtPLHtpHLtentdisten = tpZH or tpZLtdis = tPHZ or tpLZFROM(INPUT)DCOERBVee a 5 V. Vee - 4.5 V to 5.5 V.TO eL - 50 pF. eL - 50 pF.(OUTPUT) TA - 25 D e TA - oDe to 70 D eMIN TYP MAX MINMAX12 16 6 200:9 12 4 1517 23 9 280:14 19 7 22D12 18 4 218 12 2 15UNITnsnsns2-462TEXAS ..INSTRUMENlSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN74ALS994, SN74ALS99510·BIT D·TVPE TRANSPARENT READ·BACK LATCHESPARAMETER MEASUREMENT INFORMATIONq:FROM OUTPUTTESTUNDER TEST POINTCL 500 f!(See Note A)7V~Sl1 kf!FROM OUTPUTTESTUNDER TEST ~~-4~~~- POINTCL(See Note A)1 kf!LOAD CIRCUIT FORQ OR Q OUTPUTSLOAD CIRCUIT FOR 0 OUTPUTSTIMINGINPUTDATAINPUT,..----- 3.5V~3V---~ 1- - - - - - - - 0.3 V+tsu.....-th~~ I -:----3.5V1.3V 1.3V0.3VVOLTAGE WAVEFORMSSETUP AND HOLD TIMESINPUT ~-l.~V- - - 3.5V.-/f1 .3V ~ 0.3VtpLH~ I4----M-tPHL~II· I 1 -I--VIN.PHASE I' 1 OHOUTPUT I 1.3 V : . 1.3 VIVOLtpHL ~ I4----..-tPLHI . IOUT -OF·PHASE ~ 1 ., \I ~ VOHOUTPUT ~~.~v(See Note D) - - - VOLVOL TAGE WAVEFORMSPROPAGATION DELAY TIMES~~~~~LEVEL ~ 3.5VLOW·LEVELPULSE:.-- tw -.: 0.3 V--....1,">\/ tw.~~ 3.5V~ __ _VOL TAGE WAVEFORMSPULSE WIDTHS0.3 VOUTPUT ~, .,\/ ~ 3.5VCONTROL ~_~~~ ___ _(low.jevel I -:- - - - - -- - 0.3 Venabling) tPZL............ ~ !f-tPLZ1 I III I I : "" 3.5 VWAVEFORM1~1.3V i :~3VSl CLOSEO i ~.:------=.:='= VOL(See Note B) tPZH~ I TWAVEFORM 2S10PEN(See Note B)~. I' ..... r!-~~H!_ t:_- ----f- VOH1.3 V0.3 V ""0 VVOL TAGE WAVEFORMSENABLE AND DISABLE TIMES, THREE·STATE OUTPUTSElltnQ)CJ">Q)cen-JNOTES: A. CL includes probe and jig capacitance.B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.C. All input pulses have the following characteristics: PRR ,,; 1 MHz, tr = tf = 2 ns, duty cycle = 50%.D. When measuring propagation delay times of 3·state outputs, switch S 1 is open.FIGURE 1TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-463

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ADVANCEINFORMATIONSN74ALS9968·BIT D·TYPE EDGE·TRIGGERED READ·BACK LATCHESD2854, OCTOBER 1984-REVISED JANUARY 1986• 3-St~te 1/0-Type Read-Back Inputs• Bus-Structured Pinout• Tic Determines True or ComplementaryData at Q Outputs• Package Options Include Both Plastic andCeramic Chip .Carriers in Addition to Plasticand Ceramic DIPs• Dependable Texas Instruments Quality andReliabilitydescriptionThese 8-bit registers are designed specifically forstoring the contents of the input data bus plusproviding the capability of reading-back thestored data onto that bus. The Q outputs aredesigned with bus-driving capability.The edge-triggered flip-flops enter the data onthe low-to-high transition of the clock (ClK)when enable (EN) is low. Data can be read-backonto the data inputs by taking the read input (RD)low, in addition to having EN low. Whenever ENis high, both the read-back and write modes aredisabled. Transitions on EN should only be madewith ClK high in order to prevent false clocking.The polarity of the Q outputs can be controliedby the polarity input TIC. When TIC is high, Qwill be the same as is stored in the flip-flops.When TIC is low, the output data will beinverted. The Q outputs can be placed in a highimpedancestate by taking the output control (G)high. The output control IT does not affect theinternal operations of the register. Old data canbe retained or new data can be entered while theoutputs are off.405060NC7080ENOW OR NT PACKAGE!TOP VIEW)10 VCC20 1030 2040 3050 4060 5070 6080 70EN 80ROGClKTICGNOClRFN PACKAGE(TOP VIEW)U0 00 U UO 0C") N .... Z> .... N4 3 2 1 2827265 256 247 238 229 2110 2011 1912 1314151617 18NC-No internal connection.A low level at the clear input (ClR) resets the internal registers low. The clear function is asynchronousand overrides all other register functions.The -1 version of the SN74AlS996 is identical to the standard version except that the recommendedmaximum IOl is increased to 48 milliamperes.The SN74AlS996 is characterized for operation from 0 DC to 70 DC.304050NC607080CI)Q)(,)">Q)cen...JADVANCE INFORMATION documents· contain Copyright © 1984, Texas Instruments Incorporated~~~c::r:3~~~rO::h~: 0~r3:v~~~~~~n~ec~:~~!~~rst~~data and other specifications are subject to changewithout notice.TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-465

SN74ALS9968·BIT D·TVPE EDGE·TRIGGERED READ·BACK LATCHESlogic symboltlogic diagram (positive logic)G (15)Tic (14)ern (13)(10)RO(9)EN(11)ClK10 (1)(23)1QmROENClK10J!~-20 (2)30 (3)40 (4)50 (5)60 (6)70 (7)80 (8)(22)(21)(20)(19)(18)(171(16)2Q3Q4Q5Q6Q7Q8Q20 (2)30 (3)40 (4itThis symbol is in accordance with ANSI/IEEE Std 91-1984 andlEe Publication 617-12.Pin numbers shown are for DW and NT packages.2-466. TEXAS -1!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN74ALS996B·BIT D·TVPE EDGE·TRIGGERED READ·BACK LATCHEStiming diagramIT/e = HID~~~~C=~~~~~===:~~==~~~~~~~==~~~~~----~:" ____ J2~~------~I4--tsU~th-+l I I__________ ~~tw~~----~I--------------------------~----_+'----~I--~~----~1 _ClK LJ : II I I II4-ten+lI I I tdis~ I~~~ I I I IEi\j---..... I : : ~ I I~-----+1------~1--------------------------~1~----41--~ .I4--th~tdis________________ ~ I4-ten+l~I~----~IIRo :1...._______---' IQASYNCCLEARl+-tp-+II'~I ~~~----~IIIIIIWRITE READ-BACK'This hold time ensures the readback circuit will not create a conflict on the input data bus,!'---------------------------------IIITEXAS -I.!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652·467

SN74ALS996H·BIT D·TYPE EDGE·TRIGGERED READ·BACK LATCHESabsolute maximum ratings over operating free· air temperature range (unless otherwise noted)Supply voltage, Vee ......................................................... 7 VInput voltage (G, RD, EN, eLK, eLR, and TiC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VVoltage applied to D inputs and to disabled 3-state outputs .......................... 5.5 VOperating free-air temperature range. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .. ooe to 70 0 eStorage temperature range ......................................... - 65 °e to 150 0 erecommended operating conditionsIIIrencCD

SN74ALS9968·BIT D·TVPE EDGE·TRIGGERED READ·BACK LATCHESelectrica1 characteristics over recommended operating free-air temperature range (unless otherwisenoted)PARAMETER TEST CONDITIONS MIN Typt MAX UNITVIK Vee = 4.5 V, II = -18 mA -1.2 VVOHAll outputs Vee = 4.5 V to 5.5 V, 10H = -0.4 mA Vcc- 2Q Vee = 4.5 V, 10H = -2.6 mA 2.4 3.2DVee = 4.5 V, 10l = 4 mA 0.25 0.4Vee = 4.5 V, 10l = 8 mA 0.35 0.5VOL Vee = 4.5 V, 10l = 12 mA 0.25 0.4 VQ Vee = 4.5 V, 10l = 24 mA(IOl = 48 mA for -1 versions)0.35 0.5Vee~= 5.5 V, VI = 2.7 V 20Q10Zl Vee = 5.5 V, VI = 0.4 V -20D inputs Vee = 5.5 V, VI = 5.5 V 0.1IIIIHAll others Vee = 5.5 V, VI = 7 V 0.1D inputs t 20Vee = 5.5 V,VI = 2.7 VAll others20D inputs t -0.1IlL Vee = 5.5 V, VI = 0.4 V mAAll others -0.1lo§ Vee = 5.5 V, Vo = 2.25 V -30 -112 mAI Q outputs high 35 55Vee = 5.5 V,leeI Q outputs low 55 85 mAOERB highI Q outputs disabled 42 65t All typical values are at Vee = 5 V, T A = 25 De.t For 1/0 ports, the parameters IIH and III include the off-state output current.§ The output conditions have been chosen to produce current that closely approximates one half of the true short-circuit output current, lOS.switching characteristics (see Figure 1)PARAMETERf maxtplHtpHltplHtpHltplHtpHltpHltentdistentdistentdisFROM(INPUT)elK(TIC = H or l)elR (TIC = l)elR (TIe = H)TICelRRDENGTO(OUTPUT)QQQDDDQVee - 5 V, Vce = 4.5 V to 5.5 V,el - 50 pF, CL - 50 pF,TA = 25°e TA - ooe to 70 0 eMIN TYP MAX MIN MAXVp.AmAp.AUNIT40 35 MHz16 24 5 2816 24 5 2815 23 7 2713 19 7 2313 20 5 2313 20 5 2319 25 8 30 ns9 15 3 1610 16 3 199 14 3 1610 16 3 198 13 4 154 8 1 10nsnsnsnsnsns(/)Q)(.)oSQ)cen-Jten = tpZH or tpZltdis = tpHZ or tpLZTEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-469

SN74ALS996H·BIT D·TVPE EDGE·TRIGGERED READ·BACK LATCHESPARAMETER MEASUREMENT INFORMATION7V~S17V~S1500 nFROM OUTPUTTESTUNDER TEST -4~~~-4~- POINTCL;:,500 n(See Note A)FROM OUTPUTTESTUNDER TEST -4~-4~-4~- POINTCL1 kf!(See Note A)LOAD CIRCUIT FORQ OUTPUTSLOAD CIRCUIT FOR 0 OUTPUTSIrenc(I)

SN54ASl181, SN74ASl181ARITHMETIC LOGIC UNITS/FUNCTION GENERATORSD1915, MAY 1985• Package Options Include Compact 300-milor Standard 600-mil DIPs and Both Plasticand Ceramic Chip Carriers• Full Look-Ahead for High-Speed Operationson Long Words• Arithmetic Operating Modes:AdditionSubtractionShift Operand A One PositionMagnitude ComparisonPlus Twelve Other Arithmetic Operations• Logic Function ModesExclusive-ORComparatorAND. NAND. OR. NOR• Dependable Texas Instruments Quality andReliabilitylogic symbol tso (6)Sl (5)S2 (4)S3 (3)(8)M(7)c nAOJ*CIALU(1)(2)(4)SN54AS1181 .. : JT OR JW PACKAGESN74AS1181 ... OW, NT, OR NW PACKAGE(TOP VIEW)80 VCCAOA1S3 81S2 /\2S1 82SOA3C n 83MGFOF1Cn +4pF2A=BGNDF3SN54AS1181 ... FK PACKAGESN74AS1181 ... FN PACKAGES251SO 7NC 8(TOP VIEW)UC'"lOOUU~~CIlI1

SN54AS 1181, SN74ASl181ARITHMETIC LOGIC UNITS/FUNCTION GENERATORSdescriptionThe' A5 1181 arithmetic logic units (ALU)/function generators have a complexity of 75 equivalent gateson a monolithic chip. These circuits perform 16 binary arithmetic operations on two 4-bit words as shownin Tables 1 and 2. These operations are selected by the four function-select lines (50, 51, 52, 53) andinclude addition, subtraction, decrement, and straight transfer. When performing arithmetic manipulations,the internal carries must be enabled by applying a low-level voltage to the mode control input (M). A fullcarry look-ahead scheme is made available in these devices for fast, simultaneous carry generation bymeans of two cascade-outputs (pins 15 and 17) for the four bits in the package. When used in conjunctionwith the 5N54A5882 or 5N74A5882 full carry look-ahead circuits, high-speed arithmetic operations canbe performed. The typical addition times shown previously illustrate the little additional time required foraddition of longer words when full carry look-ahead is employed. The method of cascading' A5882 circuitswith these ALUs to provide multilevel full carry look-ahead is illustrated under signal designations.If high speed is not of importance, a ripple-carry input (en) and a ripple-carry output (en + 4) are available.However, the ripple-carry delay has also been minimized so that arithmetic ma'nipulations for small wordlengths can be performed without external circuitry.IIrC/)cCD

SN54ASl181, SN74ASl181ARITHMETIC LOGIC UNITS/FUNCTION GENERATORSsignal designationsIn both Figures 1 and 2, the polarity indicators ( 1::::::..) indicate that the associated input or output is activelowwith respect to the function shown inside the symbol and the symbols are the same in both figures.The signal designations in Figure 1 agree with the indicated internal functions based on active-low data,and are for use with the logic functions and arithmetic operations shown in Table 1. The signal designationshave been changed in Figure 2 to accommodate the logic functions and arithmetic operations for the activehighdata given in Table 2. The 'A51181 together with 'A5882 and '5182 can be used with the signaldesignation of either Figure 1 or Figure 2.'AS1181'AS1181so (6)S1 (5)S2 (4)S3 (3)(i!)MCn (7)}f.(0CIALU••. 15) CP(0 ..• 15) CG6(P=O)~(0 •.. 15) co(15) p(11) G(14)A=B(16) C +4 nso (6)Sl (5)S2 (4)S3 (3)M (8)C nALU(0 •.. 15) Cpf-(:...:.1S:::.)_X_--,(0 ... 15) CG 1--:...:.(1.;..:.7)_Y---,6(P=O) ~ (14) A=BAOAOBOEllenQ)(.)as;Q)CtJ)..J'AS882'AS882,---+--+--=C ṉ -,-,(l.;..) _-I CIL...;...;Po:.,..;;;( 3;...) --1::"4 CPOCPGCn (1)XO (3)CICPGXlCOl(6) Cn+8YlX2COl(6)Cn+8C03(11)Cn+16CP3CG3C03(11)Cn+16Cn+24CP4COS(17)Cn+24Cn+32CG4C07(22)

SN54AS1181, SN74AS1181ARITHMETIC LOGIC UNITS/FUNCTION GENERATORSTABLE 1Irf/)CCD

SN54ASl181, SN74ASl181ARITHMETIC LOGIC UNITS/FUNCTION GENERATORSlogic diagram (positive logic)'AS1181(3183 (41~~ (51SO~133 ~~(191~~~~~iF!= ====r-'\.I~ r===t---'~_./(171(161(151W'(131F3~~(211~~(231~~I~~I~~,}) (111./:~ (141L-F2A=BIIenCl)(,)"S;Cl)Cen....I80 l!!.. ~~11 ./:~(10)AO (2)M (8)(7)I~(9)FO~~Pin numbers shown are for DW" JT, JW, NT, and NW packages.TEXAS -I.!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-475

SN54ASl181, SN74ASl181ARITHMETIC LOGIC UNITS/FUNCTION GENERATORSIrenc(1)

SN54AS1181. SN74AS1181ARITHMETIC LOGIC UNITS/FUNCTION GENERATORSelectrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)PARAMETERTEST CONDITIONSSN54ASl181 SN74ASl181MIN Typt MAX MIN Typt MAXVIK Vee = 4.5 V, II = -18 mA -1.2 -1.2 VAny outputVOH except A = BVee = 4.5 V to 5.5 V, IOH = -2 mA VCC- 2 VCC- 2 VG Vee = 4.5 V, IOH = -3 mA 2.4 3 2.4 3 V10H A = B Vee = 4.5 V, VOH = 5.5 V 0.1 0.1 mAAny outputVOL except ITVee = 4.5 V, IOL = 20 mA 0.3 0.5 0.3 0.5 VG Vee = 4.5 V, IOL = 48 mA 0.4 0.5 0.4 0.5 VM input 0.1 0.1Any A or B input 0.3 0.3II Vee = 5.5 V, VI = 7 V mAAny 5 input 0.4 0.4IIHearry input 0.6 0.6M input 20 20Any A or B input 60 60Vee = 5.5 V,VI = 2.7 VAny 5 input80 80earry input 120 120M input -0.5 -0.5Any A or B input -1.5 -1.5IlL Vee = 5.5 V, VI = 0.4 V mAAny 5 input -2 -2earry input -3 -3All outputs except-30 -112 -30 -112lOt A=B and G Vee = 5.5 V, Vo = 2.25 V mAG -30 -125 -30 -125lee Vee = 5.5 V 74 117 74 117 mAt All typical values are at Vee = 5 V, T A = 25°e.tThe output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, 105.UNITp.AEll(J)Q)(.)0>Q)cen...ITEXAS -I.!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-477

SN54ASl181, SN74ASl181ARITHMETIC LOGIC UNITS/FUNCTION GENERATORSswitching characteristics (see Note 1)Vcc - 4.5 V to 5.5 V,IrencCD

SN54ASl181, SN74ASl181ARITHMETIC LOGIC UNITS/FUNCTION GENERATORSPARAMETER MEASUREMENT INFORMATIONSUM MODE TEST TABLEFUNCTION INPUTS: SO-S3=4.5 V, S1-S2-M-0 VPARAMETERtpLHtpHLtpLHtpHLtpLHtpHLtpLHtpHLtpLHtpHLtpLHtpHLtpLHtpHLtpLHtpHLtpLHtpHLtpLHtpHLtpLHtpHLINPUTUNDERTESTAiBiAiBiAiSiC nAiSiAnyAAnyBOTHER INPUTSAME BITAPPLY APPLY APPLY APPLY4.5 V GND 4.5 V GNDBiAiNoneNoneOTHER DATA INPUTS OUTPUT OUTPUTRemainingA and SRemainingA and SBi None NoneUNDERWAVEFORMTEST (SEE NOTE 1)C n Fi In-PhaseC n Fi In-PhaseRemainingp In-PhaseA and S, C nRemainingAi None Nonep In-PhaseA and S, C nRemaining RemainingNone BiITIn-PhaseBA, C nRemaining RemainingNone AiITIn-PhaseBA, C nNone None In-PhaseAll All Any FA- S or Cn +4NoneNoneNoneNoneBiAiBiAiRemainingSRemainingA, C nCn +4Remaining RemainingSA, C nCn +4Remaining Remaining AnyS, A3 A, C n FRemaining Remaining AnyA, B3 S, C n FOut-af-PhaseOut-af-PhaseIn-PhaseIn-PhaseC/)(J)(,)'S(J)cCJ)-INOTE 1: Load circuit and voltage waveforms are shown in Section 1.TEXAS -1!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-479

SN54AS1181, SN74AS1181ARITHMETIC LOGIC UNITS/FUNCTION GENERATORSPARAMETER MEASUREMENT INFORMATIONiliFF MODE TEST TABLEFUNCTION INPUTS: S1-S2-4.5 V. SO-S3-M-O VrenCCD

SN54AS1181. SN74AS1181ARITHMETIC LOGIC UNITS/FUNCTION GENERATORSPARAMETER MEASUREMENT INFORMATIONLOGIC MODE TEST TABLEFU!'ICTION INPUTS: S1-S2-M-4.5 V. SO-S3-0 VPARAMETERtPLHtpHLtpLHtpHLINPUTUNDERTESTAiBiOTHER INPUTOTHER DATA INPUTSSAME BITAPPLY APPLY APPLY APPLY4.5 V GND 4.5 V GNDB None NoneRemainingAi None NoneA and B. CnRemainingA andB. CnOUTPUT OUTPUTUNDER WAVEFORMTEST (SEE NOTE 1)Fi Out-ot-PhaseFi Out-ot-PhaseINPUT BITS EQUAL/NOT EQUAL TEST TABLEFUNCTION INPUTS: SO=S3=M=4.5 V. 51 =52=0 VPARAMETERtpLHtpHLtpLHtpHLtPLHtpHLtPLHtpHLtpLHtpHLtPLHtpHLtpLHtpHLtpLHtPHLINPUTUNDERTESTAiBiAiBiAiBiAiBiOTHER INPUTSAME BITOTHER DATA INPUTSAPPLY APPLY APPLY APPLY4.5 V GND 4.5 V GNDBiNoneRemainingA and B. CnNoneAiNoneRemainingA and B. Cnr-.JoneNoneBiRemainingA and B. CnNone. None AiRemainingA and B. CnNoneBiNoneRemainingNoneAiNoneNoneNoneBiAiA and B. CnRemainingA and B. CnRemainingA and B. CnRemainingA and B. CnNoneNoneNoneOUTPUT OUTPUTUNDER WAVEFORMTEST (SEE NOTE 1)PPPPCn +4Cn +4Cn +4Cn +4Out-ol-PhaseOut-ol-PhaseIn-PhaseIn-PhaseIn-PhaseIn-PhaseOut-ol-PhaseOut-ol-PhaseenQ)t)'SQ)cen...JINPUT PAIRS HIGH/NOT HIGH TEST TABLEFUNCTION INPUTS: S2=;,M=4.5 V. SO=S1 =53= OVINPUTPARAMETER UNDERTESTtpLHAitpHLtpLHBitpHLtpLHAitPHLtpLHBitpHLOTHER INPUTSAME BITOTHER DATA INPUTSAPPLY APPLY APPLY APPLY4.5 V GND 4.5V GNDBiNoneRemaining RemainingA.CnBAiNoneRemaining RemainingB.CnABiNoneRemaining RemainingA.CnBAiNoneRemaining RemainingNOTE 1: Load circuit and voltage waveforms are shown in Section 1.B. Cn AOUTPUT OUTPUTUNDER WAVEFORMTEST (SEE NOTE 1)f5In-PhasepCn +4Cn +4In-PhaseOut-ol-PhaseOut-of-PhaseTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • OALLAS. TEXAS 752652-481

SN54AS1181, SN74AS1181ARITHMETIC LOGIC UNITS/FUNCTION GENERATORSPARAMETER MEASUREMENT INFORMATIONSELECT INPUT/LOGIC MODE TEST TABLEFUNCTION INPUTS: M - 4.5 VPARAMETERtpLHtpHLtPLHtpHLINPUTUNDERTESTAnySAnySOTHER INPUTSAME BITOTHER DATA INPUTSAPPLY APPLY APPLY APPLY4.5 V GND 4.5 V GND- -RemainingB- - 8,A2A, 80, C nRemainingA, C nOUTPUT OUTPUTUNDER WAVEFORMTEST ISEE NOTE 1)Cn +4 Out-of-Phasep- In-PhaseSELECT INPUT/ARITH MODE TEST TABLEFUNCTION INPUTS: M - 0 VIrencCD

PRODUCTPREVIEWSN54ALS2967, SN74ALS2967, SN54ALS2968, SN74ALS2968DYNAMIC MEMORY CONTROLLERS02900, JANUARY 1986• Provides Control for 16K, 64K, and 256KDynamic RAMs• Highest-Order Two-Address Bits Select Oneof Four Banks of RAMs• Supports Scrubbing Operations and NibbleMode Access• Separate Output Enable for Multi-ChannelAccess to Memory• 48-Pin Dual-In-Line Package• 'ALS2968 is Designed to beInterchangeable with AMD AM2968descriptionThe' ALS2967 and' ALS2968 dynamic memorycontrollers (DMCs) are designed for use intoday's high-performance memory systems. TheDMC acts as the address controller between anyprocessor and dynamic memory array.Two versions are provided that help simplifyinterfacing to the system dynamic timingcontroller. The 'ALS2967 offers active-low RowAddress Strobe Input (RASI) and ColumnAddress Strobe Input (CASI), while the'ALS2968 offers active-high Row AddressStrobe Input (RASI) and Column Address StrobeInput (CASI) inputs.Using two 9-bit address latches, the DMC willhold the row and column addresses for anyDRAM up to 256K. These latches and the tworow/column refresh address counters feed intoa 9-bit, 4-input MUX for output to the dynamicRAM address lines. A 2-bit bank select latch isprovided to select one of the four RAS and CASoutputs. The two bits are normally obtained fromthe two highest-order address bits.SN54AlS2967, SN54AlS2968 ... JD PACKAGESN74AlS2967, SN74ALS2968 ... JD OR N PACKAGE(TOP VIEW)CSCASI or CASI tMSELRASOAOCASOA9RASlAlCASlAl0 00A2 01All 02A3 03A12 04A4GNDA13OEGNDVCCLE 05A5 06A14 07A6 08A15RAS2A7CAS2A16RAS3A8CAS3A17RASI or RASI tSELOMCOSEL 1MClt 'AlS2967 has active-low inputs CASI and RASI; 'ALS2968 hasactive-high inputs CASI and RASI.The' ALS2967 and' ALS2968 have two basic modes of operation, read/write and refresh. During normalread/write operations, the row and column addresses are multiplexed to the dynamic RAM, with thecorresponding RAS and CAS signals activated to strobe the addresses into the RAM. In the refresh mode,the two counters cycle through the refresh addresses. If memory scrubbing is not being implemented,only the row counter is used. When memory scrubbing is being performed, both the row and column countersare used to perform read-modify-write cycles. In this mode all RAS outputs will be active (low) while onlyone CAS output is active at a time.The SN54ALS2967 and SN54ALS2968 are characterized for operation over the full military temperaturerange of - 55°C to 125°C. The SN74ALS2967 and SN74ALS2968 are characterized for operation fromOOC to 70°C.CJ)Q)o'SQ)cen...IPRODUCT PREVIEW documents contain informationCopyright © 1986, Texas Instruments Incorporatedon products in the formative or design phase ofdevelopment. Characteristic data an~ otherspecifications are design goals. Texas Instruments2-483reserves the right to change or discontinue these iNSTRUMENTSproducts without notice.POST OFFICE BOX 225012 • DALLAS. TEXAS 75265TEXAS -I.!}

SN54ALS2967, SN74ALS2967, SN54ALS2968, SN74ALS2968DYNAMIC MEMORY CONTROLLERSlogic symbols t'ALS2967'ALS296ar-rJ)CCD ~~6'R4115)147)115) > ~~6'RA55RASOA55117)145)117)A66RAS1A66(19)131)119)RASA77 RAsnf~ ;RAS2A77121)129)121)Aaa.-RAS3Aaa 3 ....(4)14)A9O'A9O·(6)16)A101A101la)(a)A112A112110)110)A123A123112)112) COLA134 >~g~RA134116)f146)> ADDR(16)A145CASOA14511a)A156 1 ....144)11a)CAS 1A156120)A167 CAS ~ ....(30)(20)CAS2A167122)12a)122)A17 a.CAS3A17a123)123)SELOSELO(24)SEL1~ }SEL(24)SEL 1~ }SELCAS{~CAS I(4a),. CASI CAS I14a)CAS)(43)142)(41)140)(39)135)134)133)132)147)145)131)129)146)144)130)(2a)0001020304050607oatThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.2-484 TEXAS ~INSTRUMENlS-POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54ALS2967, SN74ALS2967, SN54ALS2968, SN74ALS2968DYNAMIC MEMORY CONTROLLERSlogic diagram (positive logic)DEMCOMClMSELcsJ~!"' ___RASI'ALS296S ONLY(14)LEAOAlA2A3A4ASA6A7ASA9Al0AllA12A13A14A15A16A17SELOSELlCAS I(371(261(251(21(11{~JLCOUNTERCTR20O~1~(ROW(~~:~lCT-O 6~7~S~9 ----./CT c 10~:~ ----./13~14(COL(~~~-:-C P. +/Cl 17 ----./J~)---4SCOlS(BANK)'ALS2967 ONLY19~-ffi----.-(51(71(9)(111~IClL;(151 lD(171(191(211~LATCHES9X(ROW)~ 9X(S)(COLUMN)(101(12)~(161 lD(lB)(20)~(231(241(BANK(lDlD(4SI 'ALS2967 ONLY ---------------- -T...!~___ ....:~S~6~O~~ ________.J9999,- --MUXENO} 01 G"3G4G5, r9X0/1,41.42,4,52.4,5'\7~RAS DECODEDMUXEN~10 V41 V423 V4f--O} 101 G 13 10.4,5 '\7G5CAS DECODEDMUXEN~0 V411 G52 G623 V4f--0} 5Z lQ1 1311.4.5'\712,4,5 '\713.4,5 '\70}6G~1 (10/20.417 '\7G7(11/21.417'\7(12/22.417 '\7(13/23.417 '\7(431(421~ (401~ (351~ (331~(47)(451(311(291(46)(44)(301(2SI0001020304050607OSIIICJ)Q)CJ"S;Q)cen..JTEXAS -I/}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-485

SN54ALS2967, SN74ALS2967, SN54ALS2968, SN74ALS2968DYNAMIC MEMORY CONTROLLERSTABLE 1. PIN FUNCTIONIrencCDc:;.

SN54ALS2967, SN74ALS2967, SN54ALS2968, SN74ALS2968DYNAMIC MEMORY CONTROLLERSMC1LLHHMCOLHLHTABLE 2. MODE-CONTROL FUNCTION TABLEOPERATING MODERefresh Mode without Scrubbing. Refresh cycles are performed with only the row counter being used to generatethe addresses. In this mode, all four RAS outputs are active while the four CAS outputs remain high.Refresh with Scrubbing/Initialize. During this mode, refresh cycles are done with both the row and column countersgenerating the addresses. MSEL is used to select either the row or the column counter. All four RAS outputs go lowin response to RASI (' ALS2967) or RASI (' ALS2968)' while only one CASn output goes low in response to CASI(' ALS2967) or CASI (' ALS2968). The bank counter keeps track of which CAS output goes active. This mode canalso be used during system power-up so that the memory can be written with a known data pattern.Read/Write. This mode is used to perform read/write cycles. Both the Rowand Column addresses are multiplexedto the address output lines using MSEL. SELO and SELl are decoded to determine which RASn and CASnoutputs will be active.Clear Refresh Counters. This mode clears the three refresh counters (row, column, and bank) on the inactive transitionof RASI (' ALS2967) or RASI (' ALS2968)' putting them at start of the refresh sequence (see timing diagrams for moredetail). In this mode, all four RAS outputs are driven low afterthe active edge of RASI (' ALS2967) or RASI (' ALS2968)so that DRAM wake-up cycles may also be performed.IIIU)Q)CJ'S;Q)C(J)..oJTEXAS -I!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-487

SN54ALS2967, SN74ALS2967, SN54ALS2968, SN74ALS2968DYNAMIC MEMORY CONTROLLERSMODETABLE 3. ADDRESS OUTPUT FUNCTIONSMC1INPUTSMCO MSEL CSOUTPUTS OO-OSRefresh without scrubbing L L X X Row counter addressRefresh with scrubbingLHL X Row counter addressH X Column counter addressL L Row address tRead/write H L H L Column address tX H All LClear refresh counter i H H X X All L'ALS2967 'ALS296SRASIRASITABLE 4. RAS OUTPUT FUNCTIONSMC1INPUTSMCOOUTPUTSSEL1 t SELOt CS RASO RAs1 RAS2 RAS3L H L L X X X L L L LL H L H X X X L L L LL L L L H H HL H L H L H HL H t-i L H L L H H L HH H L H H H LX X H H H H HL H H H X X X L L L LH L X X X X X H H H HTABLE 5. CAS OUTPUT FUNCTIONSINPUTS'ALS2967 'ALS296SINTERNALMC1 MCO SEL 1 t SELOtCAS I CASI SC1 BCOOUTPUTSCs CASO CAS1 CAS2L H L L X X X X X H H HL H L H X XL L X L H HL H X H L HH L X H H LH H X H H HL L X X L L H HL H X X L H L HL H H L H L X X L H H LH H X X L H H HX X X X H H H HL H H H X X X X X 1-1 H HH L X X X X X X X H H HCAS3HHHHLHHHLHHHt If LE is low, outputs will be the levels entered when LE was last high. If LE is high, outputs will follow address inputs as selected by MSEL.i For' ALS2967, clearing occurs on the low-to-high transition of'RASi; for' ALS296S, clearing occurs on the high-to-Iow transition of RASI.2-488 TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54ALS2967, SN74ALS2967, SN54ALS2968, SN74ALS2968DYNAMIC MEMORY CONTROLLERSread/write' operation detailsDuring normal read/write operations, the row and column addresses are multiplexed to the dynamic RAMcontrolled by the MSEL input. The corresponding RASn and CASn output signals strobe the addressesinto memory. The block diagram in Figure 1 shows a typical system interface for a one-megaword dynamicmemory. The DMC is used to control the four banks of 256K memory.For systems where addresses and data are multiplexed onto a single bus, the DMC uses latches, (row,column, and bank) to hold the address information. Figure 5 shows a typical timing diagram using theinput latches. The twenty input latches are transparent when latch enable (LE) is high, and latch the inputdata whenever LE is taken low. For systems in which the processor has separate address and data buses,LE may be permanently high (see timing diagram in Figure 4).-) DATA BUS DATA BUS>FIGURE 1. 1-MEGAWORD X 16-BIT DYNAMIC MEMORY111TEXAS "!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-489

SN54ALS2967, SN74ALS2967, SN54ALS2968, SN74ALS2968DYNAMIC MEMORY CONTROLLERSread/write operations (continued)The DMC is designed with heavy-duty outputs that are capable of driving four banks of 16-bit words,including six checkbits used for error detection and correction.In addition to heavy-duty output drivers, the outputs are designed with balanced output impedances (25 nboth high and low). This feature optimizes the drive low characteristics, based on safe undershoot, whileproviding symmetrical drive high characteristics. It also eliminates the external resistors required to pullthe outputs up to the MOS VOH level (VCC - 1.5 V).'ALS29671'ALS2968DYNAMICMEMORYCONTROLLER256K X 16·BITCHECK-BITSSELO,1IIrC/)CCD

SN54ALS2967, SN74ALS2967, SN54ALS2968, SN74ALS2968DYNAMIC MEMORY CONTROLLERSmemory expansionWith a 9-bit address path, the DMC can control up to one megaword when using 256K dynamic RAMs.If a larger memory size is desired, the DMC's chip select (CS) makes it easy to expand the memory sizeby using additional DMCs. A four-megaword memory system is shown in Figure 3.To maintain maximum performance in 32-bit applications, it is recommended that individual bus driversbe used for each bank.L\ADDRESS I2;~CHIP -SELECTDECODERf--r--r---.. DMC9, ../ ADDR~ MC1 RAS ONE-MEGAWORDrMEMORY ARRAYesoCAS4 BANKS (256K)T T T_a. DMC9 ../ ADDR~ MC1 to.RASONE-MEGAWORDMEMORY ARRAY~.. CS1 CAS 4 BANKS (256K)..iiiiiiDMC 9/ ADDR~ MC1 r RAS ONE-MEGAWORDMEMORY ARRAY4 BANKS (256K)Cs2CASiii·T i iDMC 9 r/ ADDRI~ MC1:.RAS ONE-MEGAWORDMEMORY ARRAYr Cs3_ CAS4 BANKS (256K)CAS~ iiiRAS~MsELVi•~MEMORYCONTROL.. IVi•)I MEMORY TIMING CONTROLLERFIGURE 3. 4-MEGAWORD X 16-BIT DYNAMIC MEMORYITEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-491

SN54ALS2967, SN74ALS2967, SN54ALS2968, SN74ALS2968DYNAMIC MEMORY CONTROLLERSrefresh operationsThe two 9-bit counters in the' ALS2967 and' ALS2968 support 128-, 256-, and 512-line refresh operations.Transparent, burst, synchronous, or asynchronous refresh modes are all possible. The refresh countersare advanced on the low-to-high transition of RASI on the' ALS2967, and on the high-to-Iow transitionof RASI on the' ALS2968. The refresh counters are reset to zero on the low-to-high transition of RASIon the' ALS2967, and on the high-to-Iow transition of RASI on the' ALS2968, if Me 1 and Mea are ata low logic level. See Figure 8 for additional timing details.When performing refresh cycles without memory scrubbing (Me1 and Mea both low), all four RAS outputsgo low, while all CAS outputs are driven high. Typical timing for this mode of operation is shown in Figure 6.IIrOOCCD

SN54ALS2967. iSN74ALS2967. SN54ALS2968. SN74ALS2968DYNAMIC MEMORY CONTROLLERSabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VInput voltage .............................................................. 7 VVoltage applied to disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VOperating free-air temperature range: SN54ALS2967, SN54ALS2968 . . . . . . . .. - 55°C to 125°CSN74ALS2967, SN74ALS2968 ............ , O°C to 70°CStorage temperature range ......................................... - 65°C to 150 °erecommended operating conditionsSN54ALS2967SN74ALS2967SN54ALS2968 SN74ALS2968 UNITMIN NOM MAX MIN NOM MAXVee Supply voltage 4.5 5 5.5 4.5 5 5.5 VVIH High·level input voltage 2 2 VVIL Low·level input voltage 0.8 0.8 V10H High·level output current -1 -2.6 mA10L Low·level output current 12 12 mA(23) RASI low or RASI high 15 15tw Pulse duration (24) RASI high or RASI low 15 15 .ns(25) LE high 20 20tsuthSetup timeHold time(26) An before LE! 5 5(27) SELn before LE! 5 5(28) MeO or Me1 before RASlt or RASI! 25 25(29) SELn before RASI! or RASlt 15 15(30) An after LE! 5 5(31) SELn after LE! 5TA Operating free·air temperature -55 125 0 70 °eelectrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)5nsns&ItJ)Q)(.)oSQ)cen...JSN54ALS2967SN74ALS2967PARAMETER TEST CONDITIONS SN54ALS2968 SN74ALS2968 UNITMIN Typt MAXMIN Typt MAXVIK Vee = 4.5 V, II = -18 mA -1.5 -1.5 VVee = 4.5 V, 10H = -1 mA 2.4 3.3VOHVVee = 4.5 V, 10H = -2.6 mA 2.4 3.2VOLVee = 4.5 V, 10L = 1 mA 0.'5 0.5 0.15 0.5Vee = 4.5 V, 10L = 12 mA 0.35 0.8 0.35 0.810L i Vee = 4.5 V, Vo = 2 V 30 30 mA10ZH Vee = 5.5 V, Vo = 2.7 V 20 20 p.A10ZL Vee = 5.5 V, Vo = 0.4 V -20 -20 p.AII Vee = 5.5 V, VI = 7 V 0.1 0.1 mAIIH Vee = 5.5 V, VI = 2.7 V 20 20 p.AIlL Vee = 5.5 V, VI = 0.4 V -0.1 -0.1 mAlo§ Vee = 5.5 V, Vo = 2.25 V -30 -112 -30 -112 mAlee Vee = 5.5 V mAt All typical values are at Vee = 5 V, TA = 25°e.i Not more than one output should be tested at a time, and duration should not exceed 1 second.§ The output conditions have been chosen to produce a current .that closely approximates one half the true short-circuit output current, lOS.VTEXAS l!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TE~AS 752652-493

SN54ALS2967, SN74ALS2967DYNAMIC MEMORY CONTROLLERS, AlS2967 switching characteristics, Cl == 50 pFIIrtnCCDc:::(:;'CDfnPARAMETERFROM(INPUT)TO(OUTPUT)t pd(l) RASI Any Qt pd(2) RASI RASnt pd(3) CASI CASntpd(4) Any A Any Qtpd(5) MSEL Any Qtpd(6) LEi Any Qt pd(7) LEi Any RAStpd(S) LEi Any CAStpd(9) MCO or MCl Any Qt pd(10) MCO or MCl Any RASTEST CONDITIONSttpd(ll) MCO or MCl Any CAS VCC = 4.5 V to 5.5 V,t pd(12) CS Any Q TA = MIN to MAXt pd(13) CS Any RAStpd(14) CS Any CAStpd(15) SELO or SEL 1 Any RASt pd(16) SELO or SEL 1 Any CAStent 171 OE~ Any Qt en (l'S) OE~ Any RASt en (19) OE~ Any CAStdis(20) OEi Any Qtdis(21) OEi Any RAStdis(22) OEi Any"CA"S' AlS2967 switching characteristics, Cl\150 pFSN54ALS2967MIN TYP* MAXPARAMETERFROMTOSN54ALS2967TEST CONDITIONSt(INPUT) (OUTPUT) MIN TYP* MAXtpd(l) RASI Any Q17tpd(2) RASI RASn15tpd(3) CASI CASn14tpd(4) Any A Any Q27tpd(5) MSEL Any Q19tpd(6) LEi Any Q20t pd(7) LEi Any RAS20tpd(S) LEi Any CAS VCC = 4.5 V to 5.5 V,19tpd(9) MCO or MCl Any Q TA = MIN to MAX20tpd(10) MCO or MCl Any RAS19t pd(11) MCO or MCl Any CAS17t pd(12) CS .Any Q19t pd(13) CS Any RAS14tpd(14) CS Any CAS14tpd(15) SELO or SEL 1 Any RAS15t pd(16) SELO or SEL 1 Any CAS141210S22141515141514121612111211141313151313SN74ALS2967UNITMIN TYP* MAX12 ns10 nsSns22 ns14 ns15 ns15 ns14 ns15 ns14 ns12 ns16 ns12 ns11 ns12 ns11 ns14 ns13 ns13 ns15 ns13 ns13 nsSN74ALS2967UNITMIN TYP* MAX17 ns15 ns14 ns27 ns19 ns20 ns20 ns19 ns20 ns19 ns17 ns19 ns14 ns14 ns15 ns14 nst See Figures 10, 11, 12, and 13 for test circuit and switching waveforms.:1: All typical values at VCC =5 V, T A = 25°C.2-494 TEXAS -1!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54ALS2968, SN74ALS2968DYNAMIC MEMORY CONTROLLERS, ALS2968 switching characteristics, CL 50 pFPARAMETERFROM(INPUT)TO(OUTPUT)t pd(1 ) RASI Any Qt pd(2) RASI RASnt pd(3) CASI CASnt pd(4) Any A Any Qt pd(5) MSEL Any Qt pd(6) LEt Any Qt pd(7) LEt Any RASt pd(8) LEt Any CASt pd(9) MCO or MC1 Any Qt pd(10) MCO or MC1 Any RASTEST CONDITIONStt pd(11 ) MCO or MC1 Any CAS VCC = 4.5 V to 5.5 V,t pd(12) CS Any Q TA = MIN to MAXt pd(13) CS Any RASt pd(14) CS Any CASt ed(15) SELO or SEL1 Any RASt pd(16) SELO or SEL1 Any CASt en (17) OE~ Any Qt en (18) OE~ Any RASt en(19) OE~ Any CAStdis(20) OEt Any Qtdis(21 ) OEt Any RAStdis(22) OEt Any CAS, ALS2968 switching characteristics, CL 150 pFPARAMETERFROM(INPUT)TO(OUTPUT)t pd(1) RASI Any Qt pd(2) RASI RASntpd(3) CASI CASnt pd(4) Any A Any Qt pd(5) MSEL Any Qt pd(6) LEt Any Qt pd(7) LEt Any RASTEST CONDITIONStt pd(8) LEt Any CAS Vee = 4.5 V to 5.5 V,t pd(9) MCO or MC1 Any Q TA= MIN to MAXt pd(10) MCO or MC1 Any RASt ed(11) MCO or MC1 Any CASt pd(12) es Any Qt pd(13) CS Any RASt pd(14) CS Any CASt pd(15) SELO or SEL 1 Any RASt pd(16) SELO or SEL 1 Any CASt See Figures 10, 11, 12, and 13 for test circuit and switching waveforms.* All typical values at VCC = 5 V, T A = 25 ac.SN54ALS2968 SN74ALS2968MIN TYP; MAX MIN TYP; MAXUNIT5 12 20 5 12 20 ns3 10 18 3 10 18 ns3 8 17 3 8 17 ns5 22 30 5 22 30 ns3 14 20 3 14 20 ns15 25 15 25 ns15 25 15 25 ns14 24 14 24 ns5 15 25 5 15 25 ns3 14 21 3 14 21 ns3 12 19 3 12 19 ns16 23 16 23 ns12 20 12 20 ns11 19 11 19 ns12 20 12 20 ns11 18 11 18 ns14 21 14 21 ns13 19 13 19 ns13 19 13 19 ns15 22 15 22 ns13 20 13 20 ns13 20 13 20 nsSN54ALS2968 SN74ALS2968MIN TYP; MAX MIN TYP* MAXUNIT12 17 30 12 17 30 ns9 15 23 9 15 23 ns9 14 .22 9 14 22 ns10 27 35 10 27 35 ns9 19 26 9 19 26 ns20 28 20 28 ns20 28 20 28 ns19 27 19 27 ns10 20 27 10 20 27 ns9 19 25 9 19 25 ns9 17 23 9 17 23 ns19 27 19 27 ns14 22 14 22 ns14 22 14 22 ns15 23 15 23 ns14 22 14 22 nsrnQ)CJoSQ)cen..JTEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-495

SN54ALS2967, SN74ALS2967, SN54ALS2968, SN74ALS2968DYNAMIC MEMORY CONTROLLERSA INPUTS",,--~_~____P_R_OC_E_S_SO_R_A_D_D_RE_S_S ______---J~\\\~DON'T CfiRE~\\\~Q OUTPUTS ROW ADDRESS VALID COLUMN ADDRESS VALID ROW REFRESH ADDI I II&/I//ffi!DON'T CARE W!l///4I--tI tpd(9) tc----r--------4-------~R~EA~D-I-W-R-IT-E-M--O~r~E:~------------------~~~____R_E_F_RE_S_H __ M_O_D_E _____MC INPUTSRASI ('ALS2967)RASI (' ALS2968)RASn OUTPUTMSELJCAS I (' ALS2967)CASII'ALS29681rencCD

____________________________SN54ALS2967, SN74ALS2967, SN54ALS2968, SN74ALS2968DYNAMIC MEMORY CONTROLLERSAINPUTS~~~~~~P:R~OC!ES~S~OR~A~O~OR~ES~S~~~~~~~~DO~N1T~CA~R~E~~~~~~~~~PR~O~CE~SS~O~R~AD~D~RE~SS~I+-tpd(4)~~:'~------------~.j~,~------------~.~~---------QOUTPUTS __________ ~------,~,,'-~I--R-OW--AD-D-RE-SS-V-A-lID--~,V,,~-C_O_lU_M_N_AD_D_RE_SS_V_A_lID __ JI I1'1cs __________ ~--------~-+I--------------~~----------------~--------------+l I~-----------MC INPUTS __ READ/WRITE MODE MC 1,0 - til READ/WRIE MODE MC1,O - HlJ"~ ~ +-+-______________ ~~RASI (. ALS2967))"---+-.....l.. I __-+-_________ I 4-+-_____ II ...:.-.....J~ Y t d(2)-oo: pII+- t pd(2)-+j I 1- IRASI ('ALS2968)- ---------r-~--~I~I~~--------~~------~{J t ; I L I+- th(AIl) t --.l I f\tsu(AR) -+j I ~I I 1RASnOUTPUT----------~----------~I-;~~~\\~ ____________ I~--------------~t~V~~~-----------tsu(26)-+I If-~ th(30)Ij4-I ILE~~--~~I 1 ~~----~~CASI ('ALS2967)MSEL ______ k-I I j4- tpd(5)_~ *- t p d(5)-':___ tw_(~15-)-~_rI----~------~I~------~:--------~~~----~1 __________1 1 I 1I I ,. I rr----r-: ----1 1 ~ t p d(3) -+l i+-tpd(3)--+jCASI (' ALS2968) I I I J I \ ......______1 ________------~-~----+------- t I I I -I I I tsu(AC) -"I I4t- ICASnOUTPUT-----ts-U-(2-7-1~--I~--~~------TI----------------~--~\~\\~n~"~------------I -+I th(31) ~SELINPUTS~~~~~~==B~A~NK~S~El~EC~T==)s~~~~~~~~~~D~O[N~TC~A~RE~~~~~~==~B~AN~K~S~ElE~C:T==FIGURE 5. READ/WRITE CYCLE TIMING USING INPUT LATCHES (MC1. MCO H. l)tJ)Q)(J">cQ)en...It tsu(AR). tsu(AC). and th(AR) are timing requirements of the dynamic RAM. See the DRAM data sheet for applicable specifications.TEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-497

SN54ALS2967, SN74ALS2967, SN54ALS2968, SN74ALS2968DYNAMIC MEMORY CONTROLLERSA INPUTS ~flgN;T)CARE(:_DDN'TCARE~Q OUTPUTS _____,""'.,......R°_W_R_EF_R_ES_H_AD_D_RE_S_S V_A_Ll_D,JNEXT ROW REFRESH ADDRESS VALID~I' ......----------~''''I:'--~~~I~---ICS ~DON.TCAf!~);_:~*~:~f:rj:~~ t pd(9) -+i . I --.I t pd(9) 14-Me INPUTS _,.,., ...... _R_EF_R_ES_H+M_OD_E_M_C_l_.0_-_L_L ____ ~~----RE-FR-ES-H-M-O-DE-M-Cl-.0---L-L-.J ,-_R_EA_D_/W_R_ITE_M_O_DE_j+- t pd(1) 4\RASI ('ALS2967),-----r-----( : ,"-------~IRASI (' ALS2968). I II I I \. I Itsu(AR) t -J If-I tiLt-tw(RH) t --+II I+-- twIRL) --+j !IRASn OUTPUT ----------.~:m~\ JIll ~~~lo.Jo. ______"4fJ1rJ/1\~--------------IrC/)CCD

SN54ALS2967, SN74ALS2967, SN54ALS2968, SN74ALS2968DYNAMIC MEMORY CONTROLLERSQ OUTPUTSROW REFRESH ADDRESS VALIDCOLUMN REFRESH ADDRESS VALID--If-~tp-d-(9-'1 ~ , I 1+ tpd(91+1MCINPUTS:::JK ________ ~I----------R-E-FR-ES-H-M-O-D-E-M+;C-'+}_-_L_H ________________--JX~------------------+I t4 t f4- I 1 I--~'t 1 I 1----11--------RASI ('AlS29671FI--__________ --r-+I _____I 1 I I+- tpdl21--+fRASI (' AlS29681 ___ -JJ I I 14-- th(ARI t --+I : ~----~II__--------tsu(ARI t 4t i+1 I I 1RAsnouTPuT----+:---~~m~~~~~ _____ +I~! _____ ~I __ ~h~~"rA"-----------------It2t ___...J~~.r-----..;j4-_+t-Pd-(-51---_l4--tpd(51-.1MSEl ---~,I-------..J!~f I : \1...-__I I ICASI (' AlS29671 I l ~ l',~ t3 t ----... ~I+_ tpd(31---.1CASI ('AlS29681 _______________I4- tp d(31--.!I-+1 _______ _...J 1 : I \ ..... ____________ _--.! L. 'I tsu(ACI tCASnOUTPUT*---------------------------------------;~~\\~ 1/11FIGURE 7. REFRESH CYCLE TIMING (MC1, MCO = L, H) WITH MEMORY SCRUBBINGt Parameters tsu(ARI. tsu(ACI' and th(ARI are timing requirements of the dynamic RAM. Parameters t2. t3. and t4 represent the minimumtiming requirements at the inputs to the DMC that guarantee DRAM timing specifications and maximum system performance. The minimumrequirement for t2. t3. and t4 are as follows:t2(minl = tpd(21 max + th(ARI min - t pd(51 mint3(minl = t2 min + tpd(51 max + tsu(ACI - t pd(31 mint4(minl = tpd(SI max + tsu(ARI min ,- tpd(21 minSee the DRAM data sheet for applicable tsu(ARI' tsu(ACI' and th(ARI' In addition. note that propagation delay times given in the aboveequations are functions of capacitive loading. The values used in these equations must correspond to actual system capacitive loading.* A CASn output is selected by the bank counter. All other CASn outputs will remain high.•criQ)(J'SQ)cen..JTEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-499

SN54ALS2967, SN74ALS2967, SN54ALS2968, SN74ALS2968DYNAMIC MEMORY CONTROLLERSa OUTPUTS _________ --J\\~ ____________ J./ ___ ______________, ~14---tsu(28) ., I~v~ _______________________ X~ __________Me INPUTS "- eLR REFRESH MODE Me1 ,0 - HH , _~tw(23)-+I-----------------~ 7 1 RASI('ALS2967) ,.--------------------14--tw(24)~RASI ('ALS2968_)_________---J{'\\..____________________iii-.! t pd(2) !4-RASn OUTPUT { /r- MSEL __ '\~\_~\-~.D6Wt'gA)tf~\~~'\~\-\\~encCD

SN54ALS2967, SN74ALS2967, SN54ALS2968, SN74ALS2968DYNAMIC MEMORY CONTROLLERS.oEr-----------------------------r-AINPUTS_~:------------JJ~-------------~X~-----~:---~ten(17)14- ~ t pd(9) I+- tpd(12)~ t4- tdis(20)~ l+-I ,,;-1'___ ~,..----II--~I,__---""' I I ! JQ OUTPUTS ~~~( ______, 'X ) I I ¥ i m-I ~ t pd(9) ~ : tpd(12)~ r4- I ~ t pd(6) I+- ICS: I I < }~----+I--_il---I I I II II I I IMCINPUTS_~~~~~~-M~CO~.-1---L~.H~~~M~C~O~.1--~H~L~I~R~E~AD~/~W~R~IT~E~M~O~D~E--~I~M~C~O~.1--~H~L---I I I I I I-+jten(1S)14- I tpd(10)--.t 14- I tpd(12)~ I+- II tdis(21)...t l+-I I I I I I I I I IRASn OUTPUT -H1lolo«__ +: -~)---"1":_----+l__......1 _.J( I , l ~~~: ...... >'JI}'}..I tpd(10)~ 14- I ~d(13)~ 14-: ~ t pd(7)14-,LE I I I I '\-.,.1___ ~t II+-fIII tpd(15)~ I+- I II I I I I~ten(19)14-: tpd(11)~ 14- tpd(14)~ j4- I tdis(22)~.CASn OUTPUT --~«t< =::t! =J~~ __....,.:__ ~ ____--'l? \~___: _.JX:· ::~-'->WJtpd(11)~14- I ~pd(14)~ t+- - -+/tpd(S)1.-SEL INPUTS :::::::B~A:N:K:S~E~LE~C~T::::::::~*~,.::~:~::::~BA:N:K:S~E:LE;:C:T:::::::::X BANK SELECTt pd(16)-+fRASI (' ALS2967) - L. RASI (' ALS296S) - H. MSEL - H or L. CAS I (' ALS2967) - L. CASI (' ALS296S) - HFIGURE 9. MISCELLANEOUS TIMINGtJ)Q)(,)0>Q)cen..JTEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-501

SN54ALS2967, SN74ALS2967, SN54ALS2968, SN74ALS2968DYNAMIC MEMORY CONTROLLERSSWITCHING TEST CIRCUITFROMflO ~ ~kODEVICEl1OUTPUT~,:CCLZ'ZLFROM 680!1 S,DEVICEOUTPUT 21 Cl - 50 pF 1HZ, ZH* tpd specified at CL = 50, 150 pFFIGURE 10. CAPACITIVE LOAD SWITCHINGFIGURE 11. THREE-STATE ENABLE/DISABLEIIrC/)CCDc:::C:;"CDUJINPUT,:s V XTYPICAL SWITCHING CHARACTERISTICSVOLTAGE WAVEFORMS),(r,.-s-v--- 3 V---- I '--____ J I, 0 VtpLH -I4--.c tpHL --++---+!rl1OUTPUT 2.4V' ~I. ~VOLOVTYPICAL OUTPUT DRIVER---e---VCCOUTPUT TO-. RAM ADDRESSOR CONTROLLINESFIGURE 12. OUTPUT DRIVE LEVELS---e_--GNDTHREE-STATE TIMING3-STATEr---------------"-\ - - - - - - - - - -- 3 VCONT~O~~-----.."f. ~- - ----------~.~VOUTPUT141.4---1 ..... 1- tpHZ tpZH 14 .1_____....;..1___ 1 (DISABLE) (ENABLE) I: VOHVOH : ~ VOH - 0.5 V : 1-------- 2.4 V: I (HIGH IMPEDANCE) : I: tVOL - O.SV : \---------0.8V------.-1 ---' I I: VOLVOL 11'114---;.~I-(DI~i~LE) (E~~ZBLLE) 14 .1NOTE: Decoupling is needed for all AC testsFIGURE 13. THREE-STATE CONTROL LEVELS2-502 TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TeXAS 75265

PRODUCTPREVIEWSN54ALS6301,.SN74ALS6301, SN54ALS6302, SN74ALS6302DYNAMIC MEMORY CONTROLLERS• Provides Control for 16K, 64K, 256K, and1 M Dynamic RAMs• Highest-Order Two-Address Bits Select Oneof Four Banks of RAMs• Supports Scrubbing Operations and NibbleMode Access• Separate Output Enable for Multi-ChannelAccess to Memory• 52-Pin Dual-In-Line PackagedescriptionThe' ALS6301 and' ALS6302 dynamic memorycontrollers (DMCs) are designed for use intoday's high-performance memory systems. TheDMC acts as the address controller between anyprocessor and dynamic memory array.Two versions are provided that help simplifyinterfacing to the system dynamic timingcontroller. The' ALS6301 offers active-low RowAddress Strobe Input (RASI) and ColumnAddress Strobe Input (CASI), while the, ALS6302 offers active-high Row AddressStrobe Input (RASI) and Column Address StrobeInput (CAS!) inputs.Using two 1 O-bit address latches, the DMC willhold the row and column addresses for anyDRAM up to 1 M. These latches and the tworow/column refresh address counters feed intoa 10-bit, 4-input MUX for output to the dynamicRAM address lines. A 2-bit bank select latch isprovided to select one of the four RAS and CASoutputs. The two bits are normally obtained fromthe two ~ighest-order address bits.D2900. JANUARY 1986SN54AlS6301. SN54AlS6302 ... JD PACKAGESN74AlS6301. SN74AlS6302 ... JD OR N PACKAGE(TOP VIEW)CSAOAl0AlAllA2A12 00A3 01A13 02A4 03A14 04GNDGNDTPOEMSELCASI or CASI tRASOCASORASlCASlLEVCCA5 05A15 06A6 07A16 08A7 09A17RAS2A8CAS2A18RAS3A9CAS3A19RASI or RASI tSELOMCOSEL 1MClt, AlS6301 has active-low inputs CAS I and RASI; 'ALS6302 hasactive-high inputs CASI and RASI.The' ALS6301 and' ALS6302 have two basic modes of operation, read/write and refresh. During normalread/write operations, the row and column addresses are multiplexed to the dynamic RAM, with thecorresponding RAS and CAS signals activated to strobe the addresses into the RAM. In the refresh mode,the two counters _ cycle through the refresh addresses. If memory scrubbing is not being implemented,only the row counter is used. When memory scrubbing is being performed, both the row and column countersare used to perform read-modify-write cycles. In this mode all RAS outputs will be active (low) while onlyone CAS output is active at a time.The SN54ALS6301 and SN54ALS6302 are characterized for operation over the full military temperaturerange of - 55 °C to 125°C. The SN74ALS6301 and SN74ALS6302 are characterized for operation fromOOC to 70 o C.IIItJ)Q)(.)":;Q)Cen..JPRODUCT PREVIEW documents contain informationCopyright © 1986. Texas Instruments Incorporatedon products in the formative or design ~hase ofdevelopment. Characteristic data and otherspecifications are design goals. Texas InstrumentsTEXAS -1.!12-503reserves the right to change or discontinue these INSTRUMENTSproducts without notice.POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54ALS6301, SN74ALS6301, SN54ALS6302, SN74ALS6302DYNAMIC MEMORY CONTROLLERSlogic diagram (positive logic)MUX~en0CD

SN54ALS6301, SN74ALS6301, SN54ALS6302, SN74ALS6302DYNAMIC MEMORY CONTROLLERSlogic symbols t'ALS6301'ALS6302(131fii(401OE(28iMCI>(271MC1(521MSEL(11cs(291RASI(141LE(21AO(4)A1(6)A2(8)A3(10)A4(15)A5(17)A6(19)A7121)A8(23)A9(3)A10(5)A11mA12191A13111)A14116)A15(18)A16120)A17122)A18124)A19125)SELO(26)SEL1(511CASIDYNAMIC MEMORY. CONTROLLER,., TP 4>'ALS6301EN~ } MODE"'01MSEL2,., CS 3,., RASI Q:~~R67RAs{:89,0'"1234>~~~RCAsH(461(451(441(431(421(381(371(36)135)(34)DYNAMIC MEMORYCONTROLLERfii 113) ,., TP 4>140)'ALS63021"0OEEN128)(46)00 MCO0127) ~} MODE145)01 MC11144)02152) 2MSELMSEL 143)03 11)3csCS(42)04 129)RASIRASI4Qc (38)05114106070809(50)RASO(48)RAS1(33)RAS23 _ (311RAS3567 130)89,~}SEL,., CAS I(49)CASO1471cAs1(32)CAS2CAS30001020304LELE 505137)12) 606AO0(36)14)707A11 135)16) 808A22 (34)18),909A33110)A44 ROW(15) (50)AS5>ADDRRASO(17) (48)A66RAS1119) RAs{1 (33)A77RAS2(21)131)A88RAS3123)A9 913)A100(5)A11117)A12219)A133111)149)A144CASO116)147)A155 >~~~RCAS1(18)A166CAsH~132)CAS21201(30)A177122)CAS3A1881241A199125)SELO(26)SEL1~} SEL151)CASICASIEll(J)Q)(,)oSQ)C(J)...ItThese symbols are in accordance with ANSI/IEEE Std-91-1984 and lEe Publication 617-12.TEXAS -1!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-505

SN54ALS6301, SN74ALS6301, SN54ALS6302, SN74ALS6302DYNAMIC MEMORY CONTROLLERSTABLE 1. PIN FUNCTIONIrencen

SN54ALS6301, SN74ALS6301, SN54ALS6302, SN74ALS6302DYNAMIC MEMORY CONTROLLERSMC1LLHHMCOLHLHTABLE 2. MODE-CONTROL FUNCTION TABLEOPERATING MODERefresh Mode without Scrubbing: Refresh cycles are performed with only the row counter being used to generatethe addresses. In this mode, all four "i'iAS outputs are active while the four ~ outputs remain high.Refresh with Scrubbing/lnitialize. During this mode, refresh cycles are done with both the row and column countersgenerating the addresses. MSEL is used to select either the row or the column counter. All four"i'iAS outputs go lowin response to RASI ('ALS6301) or RASI ('ALS6302), while only one CASn output goes low in response to CASI(' ALS6301) or CASI (' ALS6302). The bank counter keeps track of which CAS output goes active. This mode canalso be used during system power-up so that the memory can be written with a known data pattern.Read/Write. This mode is used to perform read/write cycles. Both the Rowand Column addresses are multiplexedto the address output lines using MSEL. SELO and SEL 1 are decoded to determine which RASn and CASnoutputs will be active.Clear Refresh Counters. This mode clears the three refresh counters (row, column, and bank) on the inactive transitionof RASI (' ALS6301) or RASI (' ALS6302), putting them at start of the refresh sequence (see timing diagrams for moredetail). In this mode, all four"i'iAS outputs are driven low after the active edge of RAS1 (' ALS6301) or RASI (' ALS6302)so that DRAM wake-up cycles may also be performed.EllU)Q)o'>Q)cen..JTEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-507

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PRODUCTPREVIEWSN74ALS8400EXPANDABLE ERROR CHECKER AND CORRECTOR02921. APRIL 1986• Direct Replacement for NationalSemiconductor DP8400JDDUAL-IN-LiNE PACKAGE(TOP VIEW)•Fast Single- and Double-Error DetectionD05D04•Fast Single-Error Correction and FunctionallyD06 D03Expandable to 100% Double-ErrorD07D02Correction CapabilityD08D01•Double-Error Correction after Catastrophic D09 DOOFailure without Additional Check Bits or ICs D010 OBOD011OLE•Functionally Expandable Capability Up toD012 DLETriple-Error DetectionD013EO•Expandable to and beyond 64 Bits with D014 AEAdditional 'ALS8400s D015 GND• Complete Error Recording OB1 XPGNDVCC• Byte Parity Generating and Checking CO E1• Separate Byte Controls for Data Output in C1 M2Byte-Write Operation C2 M1C3MO• Syndrome I/O Port for Error Logging and C4 SOManagement C5 S1-.• Full Memory Check Diagnostic and Check C6 S2Bits Simulation Diagnostics CapabilityBPO(C7)S3OESS4Self-Test of 'ALS8400 on the Memory Card CSLE S5Under Processor Control BP1 S6•Complete Memory Failure Detection•Power-On Clears Data and SyndromeLatchesEllenQ)0'S:Q)Cen..JdescriptionThe' ALS8400 is a monolithic Advanced Low-Power Schottky error checker and corrector (ECC) integratedcircuit designed to aid in system reliability and integrity by detecting errors in memory data and correctingsingle- or double-bit errors. The ECC has a separate syndrome I/O bus, which can be used for error loggingor error management. It can also be used in BYTE-WRITE applications (for up to 72 data bits) becauseit has separate byte controls for the data buffers. In 16- or 32-bit systems, the' ALS8400 will generateand check system byte parity, if required, for integrity of the data supplied from or to the processor. Thereare three latch controls to enable latching of data in various modes and configurations.The' ALS8400 is easily expandable to other data configurations. For 32-bit data bus with seven checkbits. two' ALS8400s can be used in cascade with no other ICs. Three' ALS8400s can be used for 48bits, and four' ALS8400s for 64 data bits, both using eight check bits. In all these configurations, singleerrorand double-error detection and single-error correction are easy to implement.The' ALS8400 is characterized for operation from °C to 70°C.PRODUCT PREVIEW documents contain informationon products in the formative or design phase ofdevelopment. Characteristic data and otherspecifications are design goals. Texas Instrumentsreserves the right to change or discontinue theseproducts without notice.TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1986. Texas Instruments Incorporated2-509

SN74ALS8400EXPANDABLE ERROR CHECKER AND CORRECTORIEOPIN NAMES I/OAE 0BPO/C7 I/OBP1/S7 I/OCSLEICO-C6 I/OOLEI000-0015 I/O0E1 0GNDMO-M2 IOBO.OB1 IDESIOLEISO-56 I/OVCCIXPIDESCRIPTIONAny errer eutput. In the nermal read mede. when lew. AE indicates no. errer and when high. indicates thatan errer has eccurred. In any write mede. AE is permanently lew.Byte parity O/check bit 7. When XP is at 0 V. this pin is byte-O parity I/O. In the nermal write mede. BPOreceives system byte-O parity. and in the nermal read mede. eutputs system byte-O parity. When the XP pinis epen er at VCC. the BPO/C7 pin becemes the check bit C7 I/O. the eighth check bit fer the memery checkbits. fer 48-bit expansien cenfiguratien and beyend.Byte parity 1 /syndreme bit 7. When XP pin is at 0 V. this pin is byte 1 parity I/O. In the nermal write mede.BP1 receives system byte-1 parity. and in tho nermal read mede eutputs system byte-1 parity. When theXP pin is epen er at VCC. the BP1 /57 pin becemes the syndreme bit 57 I/O. the eighth syndreme bit. fer48-bit expansien cenfiguratien and beyend.Input check bit and syndreme latch enable. When high. the eutputs ef the check bit input latches fellew inputcheck bit and. if

SN74ALS8400EXPANDABLE ERROR CHECKER AND CORRECTORfunctional descriptionThe' ALS8400, with its 16-bit bidirectional data bus connected to the memory data bus, monitors databetween the processor and memory. It uses an encoding matrix to generate six check bits from the 16 bitsof data. In a write cycle, the data word and the corresponding check bits are written into memory. Whenthe same location of memory is subsequently read, the ECC generates six new check bits from the memorydata and compares them with the six check bits read from memory to create six syndrome bits. If thereis a difference (causing some syndrome bits to go high), then that memory location contains an error andthe ECC indicates the type of error with three error flags. If the error is a single-bit error, the ECC willautomatically correct it.When the memory has more than one error, or better system integrity is preferred, double-error correctioncan be performed. One approach requires a further write-read cycle using complemented data and checkbits from the ECC. If at least one of the two errors is a hard error, the ECC will correct both errors. Thisimplementation requires no more memory check bits or ECCs than the single-error correct configuration .•t/)Q)CJoS;Q)Cen...JTEXAS "!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-511

(3~Nen ....N~~z~(J)~-i~;o~~C:~~~;:1'Tls:z~ ~.ctxl;....'"m'"8P1IS71-------------------------,BPO IC71----------------------.D~~O~~~: :: T r I I DATACSlE-----+------4I~---.JsaO!Aaa IS1 •BUS ttl080 081IOIECO~C6.C7- c:: men::::I >

PRODUCTPREVIEW• Advanced Schottky IMPACT·XTM Process• Three-Operand, 64-Word by 40-Bit RegisterFile• Supports' AS888 and 'AS8832 Register FileExpansion• Four 10-Bit Input Ports with Individual ParityCheckers and Write Enables• Four 10-Bit Output Ports with IndividualThree-State Enables• Two Write Address Ports• Two Read Address Ports and Y Output MuxPermit LSH/MSH Swap Operations• 156-Pin Package• 8-mA Bus Drivers• Texas Instruments Quality and Reliabilitylogic symboltWER1 (011WEA2 (N41WIT1 (N121WEl2 (L141RAAO :~4~1RAA1RAA2 (lllRAA3(J31RAA4(K11RAA5 (J21RABO (J11RAB,IH4JRAB2 1H31RAB3(H11RAB41H21RABS 1G1 'IF'51AL1BRSN54AS8834, SN74AS883440·BIT REGISTER FILE02936. NOVEMBER 19B5-REVISED MARCH 1986109·001 I10'9·0'011029·02011039·030140-B1T REGISTER FILE'Ase834wEA PORT AoRdescriptionThe SN54AS8834 and SN74AS8834 are highspeed, three-operand, 64-word register files ina 156-pin ceramic pin grid array.The register files are designed to support registerfile expansion for bit-slice systems usingthe' AS888 or 'AS8832. Internal parity checksand a 40-bit word width support I/O operationsfor graphics and 32-bit error detection andcorrection boards.The SN54AS8834 is characterized for operationover the full military temperature range of- 55°C to 125°C. The SN74AS8834 ischaracterized for operation from O°C to 70°C.oOIG"1O"G1S1021H131031H12104 (H151DS(H141OSIJ'5107 (J14108 (K1SI09 K141010 fl1S1011 (J121012 (P12J013 (P141014 (N,HD'S/Q1S)o161P111I TEST PINS 1109.001PARITY CHECK [019-0101CLOCK 1029·0201MASTER OUTPUT ENABLE 1039-0301(061 PRl1071 PR2WSI Pl1IM81 Pl2(8151 YOIE141 Y1IA15) Y210141 Y3(0131 Y4IC14) Y5(C12) Y610121 Y718131 YBIB111 Y9IA14) Y1018101 Y11(A12) Y12(89) Y13(A111 Y141091 Y15(A101 Y16tJ)Q)(.)os:Q)CCI)..oJ017(0141IC91 Y1701S,M101IA91 V,S019'0131(B8) Y19020 lN 'OI(871 Y20021 (0121lAS) Y21022 (P101(C71 Y22023'0111IA51 Y23024 lN9 )(07) Y24025 (010)IA4) Y25026 (pg)(86) V26027 (091(A31 V2702S IM7 )029 1051030 lP71031 (041(B51 V28IA" V291841 Y30(82) V31032 (PGIIC4) V32033(03)o3. INSI035 (02J036 (P5)1831 V33(031 V341021 V35IE21 V3S037 (P311811 V37D3S(N5)IF2J V3S039 (P4)39(C~I Y39IMPACT-X is a trademark .of Texas Instrumentst This symbol is in accordance with ANSI/lEEE Std 91-1984.PRODUCT PREVIEW documents contain informationon products in the formative or design phase ofdevelopment. Characteristic data and otherspecifications are design goals. Texas Instrumentsreserves the right to change or discontinue theseproducts without notice.TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1985. Texas Instruments Incorporated2-513

SN54AS8834, SN74AS883440·81T REGISTER FILESN54AS8834. SN74AS8834GB PIN-GRID-ARRAY PACKAGE(TOP VIEW)1 2 3 4 5 6 7 8 9- 10 11 12 13 14 15A •••••••••••••••B .@•••••••••••• @.c···· ·..D · ... ..•E• • • • ••F· · G• • • • H• • • ·• • • •J · ·...K• • • • ••L· ·..• • M• • • •• • • •N• • • • ...........p • @ • • • • • • • • • • • @ •Q•••••renoCD

SN54AS8834, SN74AS883440·BIT REGISTER FILEPINNAME NO.Al/BR F15AR/Bl G2ClK P15DO G1401 G1502 H1303 H1204 H1505 H1406 J1507 J1408 K1509 K14010 l15011 J12012 P12013 P14014 N11015 015016 P11017 014018 M10019 013020 N10021 012022 P10023 011024 N9025 010026 P9027 09028 M7029 05030 P7031 04032 P6033 03034 N6035 02036 P5037 P3038 N5039 P4GND1 E3GND1 E13GND1 C6GND1 C8GND1 C10GN01 N8I/OIIIIIIIDESCRIPTIONOutput select for Y20-Y39 output data. High selects DA20-DA39; low selects DBO-DB19.Output select for YO-Y10 output data. High selects DAO-DA19; low selects DA20-DA39.Clocks data into register file on rising edge.Input data bits 0 through 9Input data bits 10 through 19Input data bits 20 through 29Input data bits 30 through 395-volt ground (All ground pins must be used.)IIITExAs ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-515

SN54AS8834, SN74AS883440·81T REGISTER FILEIIPINNAME NO. 1/0GN02GN02F3F13GN02 J13 2-volt ground (All ground pins must be used.)GN02K2GN02 03DESCRIPTIONM8 PL2 0 Parity check result. High indicates odd number of high inputs on 030-039.MOE G12 I Master output enable, active low. Places YO-Y39 and parity outputs in the high-impedance state when high.NCNCNCNCNCNCNCNCNCA2A7A8A13B14C2C3C13C15NC 01NCNCNCNCNCElM15NlN15PlNC 08No internal connectionOEL1 F14 Y20-Y29 output enable, active lowOEL2 015 Y30-Y39 output enable, active lowIO'ER 1 FlYO-YS output enable, active low0'ER2 G4 Yl 0-Y19 output enable, active lowPL1 P8 "arity check result. High indicates odd number of high inputs on 020-029.PL2 M8 Parity check result. High indicates odd number of high inputs on 030-039.0PRl 06 Parity check"result. High indicates odd number of high inputs on OO-OS.PR2 07 Parity check result. High indicates odd number of high inputs on 010-019.RAAORAA1RAA2RAA3RAA4RAA5RABORAB1RAB2RA83RAB4RAB5TPlTP2MlJ4LlJ3KlJ2JlH4H3HlH2G1G13E15IIIRegister file A port read address select (0 = LSB)Register file A port read address select (0 = LSB)Functional testing input. Ouring normal operation, should be maintained high or open.2-516 TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54AS8834, SN74AS883440-81T REGISTER FILEPINNAME NO.VCCl C5VCCl Cl1VCCl D8VCCl N7VCC2 G3VCC2 K13VCC2 L3WALO N14WALl L13WAL2 M14WAL3 M13WAL4 N13WAL5 P13WARO L2WARl P2WAR2 M2WAR3 M3WAR4 N2WAR5 N3WEll N12WEL2 L14WERl QlWER2 N4YO B15Yl E14Y2 A15Y3 D14Y4 013Y5 C14Y6 C12Y7 B12Y8 B13Y9 611Yl0 A14Yll 610Y12 A12Y13 69Y14 AllY15 D9Y16 Al0Y17 C9Y18 A9Y19 68110III00DESCRIPTION5-volt supply for TTL-compatible 1102-volt supply for internal Schottky transistor logicWrite address for D20-D39 input dataWrite address for DO-D 19 input dataD20-D29 write enable, active lowD30·D39 write enable, active lowDO-D9 write enable, active lowD 1 O-D 19 write enable, active lowOutput data bits 0 through 9Output data bits 10 through 19;EllenQ)(,)oS;cQ)en...ITEXAS '1!1INSTRUMENlSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-517

SN54AS883~ SN74AS883440·81T REGISTER FILEIrC/)CCD

039-030 029-020 019-010 09-00."o~~--~z~.~g;iJ~~C:~~~~rTI~z; Cri.ctxl;'"0>NtnCO"'~: r Ii! I I:~1 ~10 ,10 ,10r:~ M'MOEl WAlS-WAlOWEl210WEl1 : __ on : WER2RAAS-RAAOJ J WARS-WARO64 X 10 64 X 10 64 X 10REG REG REGFilE FilE FilEAL/BR It '- ., ,I 4 AR/BLOEl2 , I q J ~ OER1OEl1~ ~ OER2ClK•Y39-Y30 Y29-Y20 Y19-Y10 Y9-YOALS8834 REGISTER FILElSI Devices IICHECKPR2WER1RABS-RABOen2tl"I~~:z:.cen• CICI~CICI-1(,.)=~men~2en .....-I~m:z:.=en"TICICI_CICIr- (,.)m~

SN54AS8834, SN74AS883440·811 REGISTER FILElEIrencCD

SN54AS8834, SN74AS8834. 40·81T REGISTER FILEabsolute maximum ratings ·over operating temperature range (unless otherwise noted)Supply voltage. Vee1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 VSupply voltage. Vee2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3 VInput voltage .............................................................. 7 VHigh-level voltage applied to 3-state outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VOperating case temperature range: SN54AS8834. . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°COperating free-air temperature range: SN74AS8834 .... . . . . . . . . . . . . . . . . . . . . .. ooe to 70°CStorage temperature range ......................................... - 65°C to 150°Crecommended operating conditionsPARAMETERSN54AS8834SN74AS8834MIN NOM MAX MIN NOM MAXVCC1 I/O supply voltage 4.5 5 5.5 4.5 5 5.5 VVCC2 STL internal logic supply voltage 1.9 2 2.1 1.9 2 2.1 VVIH High-level input voltage 2 2 VVIL Low-level input voltage 0.8 0.8 V10H High-level output current -1 2.6 rnA•10L Low-level output current 8 8 rnATC Operating case temperature 125 °cTA Operating free-air temperature -55 0 70 °celectrical characteristics over recommended operating temperature range (unless otherwise noted)SN54AS8834 SN74AS8834PARAMETERTEST CONDITIONSUNITMIN Typt MAX MIN Typt MAXVIK VCC1 = 4.5 V. II = -18 rnA -1.2 -1.2 VVCC1 = 4.5 V. 10H = -1 rnA 2.4VOHVVCC1 = 4.5 V. 10H = -2.6 rnA 2.4VOL VCC1 = 4.5 V. 10L = 8 rnA 0.5 0.5 V10ZH VCC1 = 5.5 V. Vo = 2.7 V 20 p.A10ZL VCC1 - 5.5 V, Vo = 0.4 V -0.4 rnAII VCC1 = 5.5 V, VI = 7 V 0.1 0.1 rnAIIH VCC1 = 5.5 V, VI = 2.7 V 20 20 p.AIlL VCC1 = 5.5 V, VI = 0.5 V -0.4 -0.4 rnAlOt VCC1 = 5.5 V, Vo = 2.25 V -30 -112 -30 -112 rnAICC1 VCC1 = 5.5 V rnAICC2 VCC2 = 2.1 V rnAt All typical values are at VCC = 5 V, TA = 25°C.t The output conditions have been chosen to produce a current that closely approximates one-half the true short-circuit current, lOS.UNITtJ)Q)CJ"SQ)c(J)..JTEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-521

SN54AS8834, SN74AS883440·81T REGISTER FILEtiming requirementsPARAMETERWELl-WEL2 before CLKfWER1-WER2 before CLKftsu Setup time WALO-WAL5 before CLKfWARO-WAR5 before CLKf00-039 before CLKfWEL 1-WEL2 after CLKfWER1-WER2 after CLKfth Hold time WALO-WAL5 after CLKfWARO-WAR5 after CLKf00-039 after CLKfSN54AS8834SN74AS8834MIN MAX MIN MAXUNITnsnsIrenc(1)~.n(1)enswitching characteristics over recommended ranges of operating temperature and supply voltage (seeNote 1)PARAMETERFROM TO SN54AS8834 SN74AS8834(INPUT) (OUTPUT) MIN MAX MIN MAX030-039 PL2020-029 PLl010-019 PR200-09 PRltpd RAAO-RAA5 YO-Y39 nsRABO-RAB5YO-Y39AUBRAR/BLCLKMOEMOEY20-Y39YO-Y19YO-Y39 tPL2-PL 1 orPR2-PRlYO-Y39ten OEL2 Y30-Y39 nsOELlOER2OERlMOEMOEY20-Y29Yl0-Y19YO-Y9PL2-PL 1 orPR2-PRlYO-Y39tdis OEL2 Y30-Y39 nsOELlOER2OERlY20-Y29Yl0-Y19YO-Y9tWhen read and write address are already selected.NOTE 1: Load circuit and voltage waveforms are shown in Section 1.UNIT2-522 TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54AS8838, SN74AS883832·BIT BARREL SHIFTERS02938. NOVEM8ER 1985-REVISED MARCH 1986• High·Speed "Flash" Shift Operations• Shifts up to 32 Positions in Less than 25 ns• Performs Logical. Circular. and ArithmeticShifts• 3-State Outputs Allow 32-Bit and 16-BitBus Interface• 24-mA Bus Drivers• 84-Pin Package• Uses Less than 1.5 W (Maxi• Texas Instruments Quality and ReliabilitydescriptionThe SN54AS8838 and SN74AS8838 are highspeed32-bit barrel shifters in an 84-pin ceramicpin-grid array. The devices can shift up to 32 bitsin a single instruction cycle of under 25nanoseconds. Five basic shifts can beprogrammed: circular left and right, logical leftand right. and arithmetic right.Unlike conventional shift registers, whose shiftoperations are controlled by the number of inputclock pulses applied, the number of positions tobe shifted by the' AS8838 is determined by aninput decoder. This form of implementation doesnot require an input clock, thus, the shiftoperation is restricted only by internalpropagation delays. The delay is the sameregardless of the number of positions to beshifted, resulting in a high-speed "flash" shift.Three-state output controls allow the devices tobe interfaced with 32- or 16-bit data buses.The SN54AS8838 is characterized for operationover. the full military temperature range of- 55 °e to 125°e. The SN74AS8838 ischaracterized for operation from 0 °e to 70 o e.SN54AS8838. SN74AS8838GB PIN-GRID-ARRAY PACKAGE(TOP VIEW)2 3 4 5 6 7 8 9 10 11•A • • • • • • • • • • •8 .@ ••••••• @.c • •.0. 0::F • • • •G • • • •H••• •• •• •• •• ••• • • • • •• @ • • • • • • • @ •L • • • • • • • • •••PINPINNO. NAME NO. NAMEAl GNO F9 YOELA2 VCC2 FlO Y7A3 Y30 Fll Y6A4 Y28 Gl 020A5 Y25 G2 019A6 Y23 G3 018A7 GNO G9 Y4A8 Y20 Gl0 Y5A9 Y18 Gll GNOAl0 Y16 Hl 017All GNO H2 01681 031 Hl0 Y282 GNO Hll Y383 Y31 Jl 01584 Y29 J2 01485 Y26 J5 0786 Y24 J6 0287 Y22 J7 MUXl88 Y19 Jl0 YO89 Y17 Jll Yl810 VCCl Kl VCCl811 Y15 K2 013Cl 029 K3 011C2 030 K4 09C5 Y27 K5 06C6 YO EM K6 03C7 Y21· K7 DOCl0 Y14 K8 SFT4Cll Y13 K9 GND01 027 Kl0 SFTl02 028 Kll SFTO010 Y12 L1 GND011 Yll L2 012El 024 L3 010E2 025 L4 08E3 026 L5 05E9 YlO L6 04El0 Y9 L7 01Ell Y8 L8 MUXOFl 023 L9 SFT3F2 022 L10 VCC2F3 021 L11 SFT2•(/)Q)CJ'SQ)cen~This document contains information on products inmore than one phase of development. The status ofeach device is indicated on the pagels) specifying itselectrical characteristics.TEXAS -I!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265Copyright © 1985. Texas Instruments Incorporated2-523

SN54AS8838, SN74AS883832·BIT BARREL SHIFTERSlogic symboltcI>32-BIT BARREL SHIFTER'ASSB3SMUXO (LS)MUX1 (J7)MUXOMUX1MUX1 MUXO SHIFT OPERATIONL L LOGICAL LEFTL H LOGICAL RIGHTH L CIRCULAR LEFTH H ARITHMETIC RIGHT0SHIFT POSITION CONTROLENrrncCD

SN54AS8838, SN74AS883832·BIT BARREL SHIFTERSPINNAME NO.DO K701 L702 J603 K604 L605 L506 K507 J508 L409 K4010 L3011 K3012 L2013 K2014 J2015 Jl016 H2017 Hl018 G3019 G2020 Gl021 F3022 F2023 Fl024 El025 E2026 E3027 01028 02029 Cl030 C2031 BlGNO AlGNO A7GNO AllGNO B2GNO GllGNO K9GNO LlMUXO L8MUXl J7SFTO KllSFTl Kl0SFT2 L 11SFT3 L9SFT4 K8VCCl Bl0VCCl KlVCC2 A2VCC2 Ll0110IIIDESCRIPTIONInput data bits 0 through 31Ground (All ground pins must be used.)Shift instruction control. Specifies the type of shift operation to be performed. See Table 1 for further information.Shift position control. Specifies the number of bit positions to shift. See Table 1 for further information.5-Volt supply for TTL-compatible 1/02-Volt supply for internal Schottky Transistor Logic (STL)C/)Q)(.)"S:Q)cCJ)..JTEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-525

SN54AS8838, SN74AS883832-BIT BARREL SHIFTERSrC/)CCD

SN54AS8838, SN74AS883832·BIT BARREL SHIFTERSfunctional block diagramMUX1-MUXO -.~2"--ISFT4-SFTO -+_5~~SHIFTCONTROLBLOCK32031-00 --+~O

SN54AS8838, SN74AS883832·BIT BARREL SHIFTERSshift operation exampleslogical shift left 1M 1 - MO = LL)In the shift left mode, SFT4-SFTO define the number of bit positions to be shifted. The following exampleshifts a 32-bit word 8 positions to the left and fills the vacated bit positions with zeros.CONTROL SIGNALSAssume 031-00 is hex ABCOO 123.SHIFTINSTRUCTIONNUMBER OF BITSTO SHIFTM2-MOSFT4-SFTO00 01000Input Oata031-001 a 1 a 1 011 11 00 11 01 0000 000 1 00 1 a 00 11 IResultY31-YO1100 1101 0000 0001 0010 0011 0000 0000 IC logical shift right IM1 - MO ... LH)CD< In the shift right mode, the two's complement of the number of bit positions to be shifted must be placedn' on SFT4-SFTO. The following example shifts a 32-bit word 8 positions to the right and fills the vacatedbit positions with zeros.mCONTROL SIGNALSSHIFTNUMBER OF BITSINSTRUCTIONTO SHIFTM2-MOSFT4-SFTO01 11000Assume 031-00 is hex ABC00123.Input Oata031-001 a 1 a 1 011 11 00 11 01 0000 000 1 00 1 a 00 11 IResultY31-YOI 0000 0000 1 a 1 a 1 011 11 00 11 01 0000 000 1 I2-528 TEXAS ..INSTRUMENTSPOST OFFice BOX 225012 • DALLAS. TeXAS 75265

SN54AS8838, SN74AS883832·BIT BARREL SHIFTERScircular shift left 1M 1 - MO == HL)In the circular shift left mode, SFT4-SFTO define the number of bit positions to be shifted. The followingexample circular shifts a 32-bit word 8 positions to the left.CONTROL SIGNALSAssume 031-00 is hex ABC00123.circular shift right (M 1 - MO = HL)SHIFTINSTRUCTIONNUMBER OF BITSTO SHIFTM2·MOSFT4·SFTO10 01000031-00Input Oata 11010 1011 1100 1101 00000001 001000111Y31-YOResult 11100 1101 0000 0001 0010 0011 1010 10111A circular right shift can be performed by placing the two's complement of the number of bit positionsto be shifted on SFT 4-SFTO and using the circular left shift mode (M 1 - MO = HL). The following examplecircular shifts a 32-bit word 8 positions to the right.Assume 031-00 is hex ABC00123.SHIFTINSTRUCTIONCONTROL SIGNALSNUMBER OF BITSTO SHIFTM2·MOSFT4·SFTO10 11000031-00Input Oata 11010 1011 1100 1101 0000 0001 001000111EllU)Q)(.)0$Q)cen...IY31-YOResult 100100011 1010 1011 1100 1101 0000 00011TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-529

SN54AS8838, SN74AS883832·BIT BARREL SHIFTERSarithmetic shift right(M 1 - MO .. HH)In the arithmetic shift right mode, SFT4-SFTO define the number of bit positions to be shifted. The followingexample shifts a 32-bit word 8 positions to the right and fills the vacated bit positions with the sign bit(031 from the input data).CONTROL SIGNALSSHIFTNUMBER OF BITSINSTRUCTIONTO SHIFTM2-MOSFT4-SFTO11 11000Assume 031-00 is hex ABC00123.031-00IrC/)CCD

PRODUCTPREVIEWSN54AS883832·BIT BARREL SHIFTERSelectrical characteristics over recommended operating temperature range (unless otherwise noted)PARAMETERTEST CONDITIONSSNS4AS8838MIN Typt MAXVIK VCCl = 4.5 V. 11= -18 mA -1.2 VVOHVOLVCCl = 4.S V to 5.S V. 10H = -0.4 mA VCC-2VCCl = 4.S V. IOH= -1 mA 2.4VCCl = 4.5 V. IOl - 12 mA 0.4VCCl = 4.5 V.IOl = 24 mA10ZH VCCl = 5.5 V. Va = 2.7 V 20 I'A10Zl VCCl = 5.5 V. VI = 0.4 V -0.4 mAII VCCl = 5.5 V. VI = 7 V 0.1 mAIIH VCCl = 5.5 V. VI = 2.7 V 20 I'AIII VCCl = 5.5 V. VI = 0.4 V -0.4 mAlot VCCl = 5.5 V. Va = 2.25 V -30 -112 mAICCl VCCl = 5.5 V 150 mAICC2 VCC2= 2.1 V 145 mAUNITVVswitching characteristics over recommended operating temperature range (see Note 1)PARAMETERVCC - 4.S V to S.S V.CL - so pF.FROM TO R1 - SOO fl.(INPUT) (OUTPUT) R2 - SOO flSNS4AS8838MUX1-MUXO Y31-YO 22MIN Typt MAX UNITtpd SFT4-SFTO Y31-YO 22 ns031-00 Y31-YO 22tentdisYaEL Y15-YO 12YOEM Y31-Y16 12YOEl Y15-YO 6YOEM Y31-Y16 6nsnstnQ)(.)'SQ)cen...Jt All typical values are at VeC1 = 5 V. TA = 2Soe.:i:The output conditions have been chosen to produce a current that closely approximates one-half the true short-circuit current. lOS.NOTE1: For load circuit and voltage waveforms. see pages 1-12 of The TTL Data Book. Volume 3. 1984.PRODUCT PREVIEW documents contain informationon products in the formative or design IIhase ofdevelopment. Characteristic data anil otherIpacifications are design goall. Texas Instrumentsraserves the right to change or discontinue theseproducts without notice.TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-531

SN74AS883832·81T BARREL SHIFTERSelectrical characteristics over recommended operating free·air temperature range (unless otherwisenoted)PARAMETERTEST CONDITIONSSN74AS8838VIK VCC1 = 4.5 V, 11= -18 mA -1.2 VVCC1 = 4.5 V to 5.5 V, 10H = -0.4 mA Vcc- 2VOH VCCl = 4.5 V, 10H= -1 mA VVOLMINVCC1 = 4.5 V, 10H = -2.6 mA 2.4MAXVCC1 = 4.5 V, 10l = 12 mA 0.4VCC1 = 4.5 V, 10l = 24 mA 0.510ZH VCC1 = 5.5 V, Vo = 2.7 V 20 p.A'OZl. VCC1 = 5.5 V, V, = 0.4 V -0.4 mAII VCCl = 5.5 V, V, = 7 V 0.1 mAIIH VCC1 = 5.5 V, V, = 2.7 V 20 p.A',l VCC1 = 5.5 V, V, = 0.4 V -0.4 mA10~ VCC1 = 5.5 V, Vo = 2.25 V -30 -112 mAICC1 VCC1 = 5.5 V 150 mAICC2 VCC2 = 2.1 V 145 mAt The output conditions have been chosen to produce a current that closely approximates one-half the true short-circuit current, lOS.UNITVrencCD

PRODUCTPREVIEW• High·Speed 8-Bit Parallel Output Register• Serial Shadow Register with Right-ShiftOnly• • ALS29818 Performs Parallel-to-Serial andSerial-to-Parallel Conversion• Designed Specifically for Use in Applicationssuch as:Write Control Store ('ALS29818)Serial Shadow-Register Diagnostics• • ALS29819 Provides Even-Parity Output• Low Power Dissipation ... 215 mW Typical• • ALS29818 is Functionally Equivalent toAMD AM29818• Package Options Include Both Plastic andCeramic Chip Carriers in Addition to Plasticand Ceramic DIPsoDependable Texas Instruments Quality andReliabilitydescriptionThe' ALS29818 and' ALS29819 are 8-bitoutputregisters with on-chip shadow register for usein applications such as write control store andshadow register diagnostics.The output registers of the ' ALS29818 and, ALS29819 are loaded in parallel from either theI/O port (DOO-D07) or the shadow register.The shadow register of the' ALS29818 is loadedserially from either the I/O port (YO- Y7) or theoutput register. The' ALS29819 shadow registeris loaded serially from the I/O port (DOO-D07).In addition, the' ALS29819 provides a ParityEven (PE) output, which monitors parity of theoutput register. Operation of these devices iscontrolled by the Mode and SDI inputs as shownin the function table.The SN54ALS29818 and SN54ALS29819 arecharacterized for operation over the full militarytemperature range of - 55°C to 125°C. TheSN74ALS29818 and SN74ALS29819 arecharacterized for operation from 0 °e to 70°C.SN54ALS29818, SN54ALS29819SN74ALS29818, SN74ALS298198·BIT DIAGNOSTICS/PIPELINE REGISTERS02298. JANUARY 1986SN54ALS29818 ... JT PACKAGESN74ALS29818 ... OW OR NT PACKAGEOEYSRCLKDQOOQlOQ2DQ3(TOP VIEW)VCCMODEYOYlY2DQ5Y5DQ6Y6DQ7 10 15 Y7SDI 11 14 SDOGND 12 13 ORCLKSN54ALS29818 ... FK PACKAGESN74ALS29818 ... FN PACKAGE(TOP VIEW)DQlDQ2DQ3NCDQ4 9DQ5 10DQ6 111 28272625! Yl24 Y223 Y322 NC21 Y420 Y519 Y612 13 14 15161718g~~~g~~oSN54ALS29819 ... JT PACKAGESN74ALS29819 ... OW OR JT PACKAGE(TOP VIEW)PESRCLKVCCMODEDQ5DQ6DQ7 10 15 Y7SDI 11 14 SDOGND 12 13 ORCLKSN54ALS29819 ... FK PACKAGESN74ALS29819 ... FN PACKAGE(TOP VIEW)" wo d U Og~~~~~~1 282726DQl 5 25 YlDQ2 6 24 Y2DQ3 7 23 Y3NC 22 NCDQ4 21 Y4DQ5 10 20 Y5DQ6 11 19 Y612 131415161718•U)Q)CJ'SQ)oen-oJg~~~g~~0NC-No internal connectionPRODUCT PREVIEW documents contain informationon products in the formative or design phase ofdevelopment. Characteristic data and otherspecifications are design goals. Texas Instrumentsreserves the right to change or discontinue theseproducts without notice.TEXAS "'I}INSTRUMENTSPOST OFFICE BOX 2250'12 • DALLAS. TEXAS 75265Copyright © 1986. Texas Instruments Incorporated2-533

SN54ALS29818, SN54ALS29819SN74ALS29818, SN74ALS298198·BIT DIAGNOSTICS/PIPELINE REGISTERS'ALS29818 FUNCTION TABLEIrencCDc:::ri"CDenINPUTS OUTPUT AND 1/0MODE OEY SOl SRCLK ORCLK SDO VO-Y7 DOO-DQ7L X X t X SR7 - HI-ZH H L t X SOl INPUT HI-ZH L L T No T SOl OUTPUT HI-ZL X X X T SR7 - INPUTtL X X T t SR7 - INPUTtH X X No T t SOl - -H X X X X SOl - -H L L t t SOl OUTPUT HI-ZH X H X ·X SOl - -H X H t X SOl - OUTPUTtThe 000-007 outputs must be disabled before applying data to 000-007.'ALS29819 FUNCTION TABLEINPUTS OUTPUT AND 1/0MODE SOl SRCLK ORCLK SDOVO-V7PE000-007L X t X SR7 OUTPUT HI-ZH L T XSOl(L)OUTPUTINPUTSOlH L t tOUTPUT INPUT(L)L X X tX L X TSR7 OUTPUT INPUTL X t t SR7 OUTPUT INPUTH H No t tSOl(H)OUTPUTH X X X SDI OUTPUT -OUTPUTSOlOUTPUTH H X, X OUTPUT(H)HOLDL X X X- OUTPUT HI·ZX L X XOPERATION OR FUNCTIONSerial input, shift right, disable 000-007Parallel load shadow register from VO- Y7,disable 000-007Parallel load shadow register from outputregister, disable 000-007Load output register from 000-007Load output register from 000-007 whileshifting shadow registerLoad output register from shadow registerSerial data in to serial data outExchange data between registers,000-007 disabledHold shadow register, transitions on SRCLKdo not effect shadow registerEnable 000-007 for parallel shadowregister outputOPERATION OR FUNCTIONSerial input, shift rightParallel load shadow register fromDOO-DQ7Parallel load shadow register and outputregister from DOO-DQ7Load output register from 000-007Load output register from 000-007 whileshifting shadow registerLoad output register from shadow registerSerial data in to serial data outHold shadow register, enable 000-007,transitions on SRCLK ignoredDisable 000-007 outputs2-534 TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54ALS29818, SN54ALS29819SN74ALS29818, SN74ALS298198·BIT DIAGNOSTICS/PIPELINE REGISTERSlogic symbols t'ALS29818'ALS29819,...,(PIPELINE REGISTER((1)OEYEN8(131ORCLKC7SRG8+(21SRCLK1-IC3MUX(231(141MODEMl/5.30.EN6SOOSO 1(11) M2/Z4/G5 27 1rL ~.30 (SHADOW REGISTER)30.1.2.30(3)000Z10Z204- ';7631.1.2.30(4)001 ZllZ214- ';76(5)002(6)003(7)004(8)DOS(9)00637.1.2.30(10)007Z17Z274- ';76MUX [>(22)10.18';7YO7020.1Z30 ~ (21)Yl(20)Y2(19)Y3(18)Y4(17)Y5(16)Y6MUX [>(15)17.1 708';7Y727.1Z37~ORCLK (13)SRCLK (2)MODE (23)SOl 111)L ~.20(PIPELINE REGISTER)C6SRG81-IC2MUXMl/4EN5~!~Z3/G4 7 1(SHADOW REGISTER)000 (3)1.20/Z10L:-001 '(4)5';7L.- 1.20/Z115';715)002(6)003(7)004(8)DOS(9)006(10)0071.20/Z174. 5';710.60 [>17.60 [>2k(EVEN PARITYFOR Y OUTPUTS)rZ7(14)SOO(22) YO(21) Yl(20) Y2(19) Y3(18) Y4(17) Y5(16) Y6(15) Y7(1)PEIIr.J)Q)(.)'$Q)Cen...JtThese symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.TEXAS -li1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-535

SN54ALS29818, SN54ALS29819SN74ALS29818, SN74ALS298198·BIT DIAGNOSTICS/PIPELINE REGISTERSlogic diagrams (positive logic)'ALS29818OEy~(1~)--------------______ ------------------------------------,ORCLK~(1~3)~ __________________________________________ --,SRCLK~(2~)-+~~~--------~SHADOWREGISTERSOI(11)Y7-YOr(J)CCD

SN54ALS29818SN74ALS298188·BIT DIAGNOSTICS/PIPELINE REGISTERS, ALS29818 gate-level logic diagram (positive logic)t:>--t-+--+-~(22);:. ....... ---oOIIr.--'---' YOIII(21) YlDQ2~DQ3~DQ4~DQ5~DQ6~5 (DENTICAL SECTIONSNOT SHOWN~Y2~ ~Y3---.--..-------Y4 ~~Y5---.--..------- ~ Y6(151P-~-+--~ >~ __ ~--Y7(10)DQ7--~~~+-~r-~~------~~--------

SN54ALS29819SN74ALS298198·BIT DIAGNOSTICS/PIPELINE REGISTERS, ALS29819 gate-level logic diagram (positive logic)ORClKSRClK ------------i >-------,SOlMODEDOO~(3~1 ___ ~~-+~-------~--_r--~TO NEXTSHEETrencCD

SN54ALS29819SN74ALS298198-BIT DIAGNOSTICS/PIPELINE REGISTERS, ALS29819 gate-level logic diagram (positive logic) (continued)QYO---------.~--QY1 ~-+ ___ .... _+_

SN54ALS29818, SN54ALS29819SN74ALS29818, SN74ALS298198-BIT DIAGNOSTICS/PIPELINE REGISTERSabsolute maximum ratings over operating free-air temperature rangeSupply voltage, Vee ......................................................... 7 VInput voltage, any input or I/O port ............................................ 5.5 VOperating free-air temperature range: SN54ALS' . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°CSN74ALS' ............................. ooe to 70°CStorage temperature range ......................................... - 65°C to 1 50°Crecommended operating conditionsISN54ALS29818SN54ALS29819MIN NOM MAXVCC Supply voltage 4.5 5 5.5VIH High-level input voltage 2VIL Low-level input voltage 0.8IOH High-level output currentYO-Y7 -3All others -1IOLfclocktwtsuLow-level output currentClock frequencyPulse durationSetup time before SRCLKiYO-Y7 16All others 4SRCLKORCLKSRCLK high or lowORCLK high or lowYO-Y7MODESDIORCLK. (' ALS29818) tDOO-DQ7tsu Setup time before ORCLKi MODESRCLKtYO-Y7th Hold time after SRCLKi MODESDIDOO-DQ7th Hold time after ORCLKi MODESDI (' ALS29819)TA Operating free-air temperature -55 125t This setup time ensures that the shadow register will see stable data from the output register.t This setup time ensures that the output register will see stable data from the shadow register.SN74ALS29818SN74ALS29819 UNITMIN NOM MAX4.75 5 5.25 V2 V0.8 V-3mA-124mA8MHznsnsnsnsns0 70 °c2-540TEXAS -I.!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54ALS29818, SN54ALS29819SN74ALS29818, SN74ALS298198·BIT DIAGNOSTICS/PIPELINE REGISTERSelectrical characteristics over recommended operating temperature range (unless otherwise noted)SN54ALS29818SN74ALS29818PARAMETER TEST CONDITIONSt SN54ALS29819 SN74ALS29819MIN TYP* MAX MIN TYP* MAXVIK Vee = MIN, II = 18 rnA -1.2 -1.2All outputs Vee = MIN to MAX, 10H = -0.4 rnA Vec- 2 Vcc- 2VOH YO-Y7 Vee = MIN, 10H= -3 rnA 2.4 3.2 2.4 3.2All others Vee = MIN, 10H= -1 rnA 2.4 3.2VOLAll outputsVee = MIN, 10L = 4 rnA 0.25 0.5 0.25 0.5Vee = MIN, 10L = 8 rnA 0.35 0.5Vee = MIN, 10L = 16 rnA 0.25 0.5 0.25 0.5YO-Y7Vee = MIN, 10L = 24 rnA 0.35 0.5MODE 0.4 0.4IISReLKVee = MAX, VI = 5.5 V0.3 0.3SOI,OEY 0.2 0.2All others 0.1 0.1MODE 80 80SReLK 60 60IIH Vee = MAX, VI = 2.4 VSOI,OEY 40 40All others§ 20 20MODE -0.4 -0.4IlLSReLKVee = MAX, VI = 0.5 V-0.3 -0.3SOI,OEY -0.2 -0.2All others§ -0.1 -0.1lOS' Vee = MAX, Vo = 0 -75 -250 -75 -250lee Vee = MAX (see Note 1) 43 43t For conditions shown as MIN or MAX, use appropriate value specified under recommended operating conditions.* All typical values are at Vee = 5 V, T A = 25 ce.§ For I/O ports, the parameters IIH and IlL include the off-state output current., Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.NOTE 1: lee is measured with all three-state outputs in the high-impedance state.UNITVVVrnAp.ArnArnArnAEllenQ)(,)oS;Q)cen...ITEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-541

SN54ALS29818SN74ALS298188·BIT DIAGNOSTICS/PIPELINE REGISTERS, ALS29818 switching characteristics (see Note 2)IrencCl)

SN54ALS29819SN74ALS298198·BIT DIAGNOSTICS/PIPELINE REGISTERS'ALS29819 switching characteristics (see Note 2)Vce - 5 V. Vec - MIN TO MAX. tPARAMETERTEST CL - 50 pF. eL - 50 pF.FROM TOCONDITIONS TA - 25 0 e TA ~ MIN TO MAXt(INPUT) (OUTPUT)See Figure 1 'ALS29819 SN54ALS29819 SN74ALS29819UNITMIN TYP MAX MIN MAX MIN MAX37fmax:~~~~:37MHztpLH 8MODE SOO RL = 2 kntpHL 8nstpLH 8SOl , SOO RL = 2 kntpHL 8nstpLH 9ORCLK YO-Y7 RL = 2 kntpHL 9nstpLH 9ORCLK PE RL = 2 kntpHL 5nstpLHSRCLK SOO RL = 2 kn13tpHL 13nstpLH R1 = 5 kn. 12SRCLK 000-007tpHL R2 = 2 kn 12nstpZH MODE R1 = 5 kn. 7000-007tpZL or SOl R2 = 2 kn 9nstpHZ MODE R1 = 5 kn. 7OOO-OQ7tpLZ or SOl R2 = 2 kn 9nst For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.Ell(f)Q)(.)0>Q)cen...JTEXAS -I.!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-543

SN54ALS29818, SN54ALS29819SN74ALS29818, SN74ALS298198·BIT DIAGNOSTICS/PIPELINE REGISTERSPARAMETER MEASUREMENT INFORMATIONVCCTESTPOINTVCCRL S1,/ R2 IFROM OUTPUT_ ........ 4II........._C1' ~FROM OUTPUT ~""~I---4IUNDER TESTUNDER TESTLOAD CIRCUIT FORBI-STATETOTEM-POLE OUTPUTSCLIS".'''A'1LOAD CIRCUIT FORTHREE-STATE OUTPUTSALL DIODES1N916 OR1N3064SWITCH POSITION TABLETEST S1 S2tpLH Closed ClosedtpHL Closed ClosedtpZH Open ClosedtpZL Closed OpentPHZ Closed ClosedtPLZ Closed ClosedIrencCDc::(=rCDenTIMING3VINPUT~.SV___...J_ _ - --- - --0 V1~tsu...,..th~DATA ~;.~;3VINPUT J ..... v ~ 0 VINPUT J1.SVVOLTAGE WAVEFORMSSETUP AND HOLD TIMES\~~--3V: I 0 VtPLH~ ~tPHLIN-PHASE I /' I ~1-!;~ VOHOUTPUT I . 1.SV: . ef I VOLtpHL ~ I4----++-tpLH1 ~VOHOUT-OF-PHASE 1 . S V 1.S VOUTPUT \ • .VOLVOLTAGE WAVEFORMSPROPAGATION DELAY TIMESHIGH-LEVEL ~ - - - 3 VPULSE --./! 1.S V 1.S V~LOW-LEVELPULSEOUTPUTCONTROL:.-- tw ---oJ 0 V~tw~, 3V~1.SV --1.SV~~---OVVOLTAGE WAVEFORMSPULSE DURATIONS~15V ~3V~ s--L1~-~---OVtpZL~ ~ II I tPLZ~ I+-WAVEFORM 1 1\~:~11--- :~::~(See Note BI I I __ -t.I-. VOLtpZH~ t4-: .. I ....... Lo 3 VI tpHZ......., ii .WAVEFORM 2-1 S V~~ -VOH(See Note BI· _ ~ ~ _____ ~i ~VOLTAGE WAVEFORMSENABLE AND DISABLE TIMES, THREE-STATE OUTPUTSNOTES: A. CL includes probe and jig capacitance.S. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.C: All input pulses are supplied by generators having the following characteristics: PRR ~ 10 MHz, Zo = SO n, tr ~ 2.S ns,tf ~ 2.S ns.FIGURE 12-544 TEXAS -1.!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

PRODUCTPREVIEWSN54ALS29821. SN54ALS29822SN74ALS29821. SN74ALS2982210·BIT BUS INTERFACE FLlp·FLOPS WITH 3·STATE OUTPUTSD2825. JANUARY 1986• Functionally Equivalent to AMD's AM29821and AM29822• Provides Extra Data Width Necessary forWider Address/Data Paths or Buses withParity• Outputs Have Undershoot ProtectionCircuitry• Power-Up High-Impedance State• Package Options Include Both Plastic andCeramic Carriers in Addition to Plastic andCeramic DIPs• Buffered Control Inputs to Reduce DCLoading Effects• Dependable Texas Instruments Quality andReliabilitydescriptionThese 10-bit flip-flops feature three-stateoutputs designed specifically for driving highlycapacitiveor relatively low-impedance loads.They are particularly suitable for implementingwider buffer registers, I/O ports, bidirectional busdrivers with parity, and working registers.The ten flip-flops are edge-triggered D-type flipflops.On the positive transition of the clock theQ outputs on the' ALS29821 will be true, andon the I ALS29822 will be complementary to thedata input.A buffered output-control (OC)input can be usedto place the ten outputs in either a normal logicstate (high or low levels) or a high-impedancestate. In the high-impedance state the outputsneither load nor drive the bus lines significantly.The high-impedance state and increased driveprovide the capability to drive the bus lines in abus-organized system without need for interfaceor pull-up components. The output control doesnot affect the internal operation of the flip-flops.Old data can be retained or new data can beentered while the outputs are in the highimpedancestate.The SN54'family is characterized for operationover the full military temperature range of- 55°C to 125°C. The SN74' family ischaracterized for operation from OOC to 70°C.SN54ALS29821 ... JT PACKAGESN74ALS29821 ... OW OR NT PACKAGE(TOP VIEW)oc 24 vCClD 23 102D 3 22 203D 4 21 304D 20 405D 19 506D 7 18 607D 8 17 708D 9 16 809D 10 15 9010D 11 14 100GND 12 13 ClKSN54ALS29821 ... FK PACKAGESN74ALS29821 ... FN PACKAGE(TOP VIEW)~~lg~~~~4 3 2 1 28 27261213141516171825 3024 4023 5022 NC20 7019 aoSN54ALS29822 ... JT PACKAGESN74ALS29822 ... OW OR NT PACKAGE(TOP VIEW)5C 24 VCC10 23 1020 3 22 2030 4 21 3045 20 4050 19 5060 18 6070 17 7080 16 8090 10 15 90100 14 100GND 12 " 13 ClKSN54ALS29822 ... FK PACKAGESN74ALS29822 ... FN PACKAGE(TOP VIEW)1~1~lg ~ ~ ~ ~4 3 2 1 28 272630 5 25~ 3040 6 24( 4055 23~ 50NC22[ NC60 21[ 6070 10 20[ 7080 11 19[ 8012 1314 151617 1SBIllCJ)(1)CJ"S(1)c(/)-JPRODUCT PREVIEW documents contain informationon products in the formative or design Jlhase ofdevelopment. Characteristic data and otherspecifications are design goals. Texas Instrumentsreserves the right to change or discontinue theseproducts without notice.TEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265lolooU~OOm~~2d~mNC-No internal connectionCopyright © 1986. Texas Instruments Incorporated2-545

SN54ALS29821, SN74ALS2982110·BIT BUS INTERFACE FLlP·FLOPS WITH 3·STATE OUTPUTS'ALS29821 FUNCTION TABLE (EACH FLIP-FLOP)INPUTSOUTPUTOC CLK 0 QL t H HL t L LL L X 00H X X, Z'ALS29821 logic diagram (positive logic)oc (1)'ALS29821 logic symboltIrCJ)CCDc:::n'CDf/lDceLK(231101Q(3) (2212020(4) (21)303Q(51 (20)4040(61 (19)5050171 (i8)606070(8) (17170(9) (1618080(15)90(1490100 10QtThis symbol is in accordance with ANSI/IEEE Std 91-1984 andlEe Publication 617-12.Pin numbers shown are for DW, JT, and NT packages.20 (3)3D _(4_)___-t---I40.;.,(5..;.,) ---t--_I50 _(6_)___ t--_I60 17170 (8)80 ...;.(9...;.) __ --i~_I(10)90 ~~---i~-I(11 )100 -------1Pin numbers shown are for DW, JT, and NT packages.2-546 TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54ALS29822, SN74ALS2982210-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS'AlS29822 FUNCTION TABLE (EACH FLIP-FLOP'INPUTSOUTPUTOC ClK 0 QL t H LL t L HL L X 00H X X Z'ALS29822 logic diagram (positive logic)oc ...;,1...,;.11 ___ ----401, ALS29822 logic symbolt20 (3110 1020 2035 3040 4050 5065 6070 7080 8090100tThis symbol is in accordance with ANSI/lEEE Std 91-1984 andlEG Publication 617-12.Pin numbers shown are for OW, JT, and NT packages.30 (4140 (5'50 (6160 ...;.(7..,.;.'_____ I--Cl70...;.(B-I--__ I--Clen(1)CJ'S(1)cen....I80 _(9_1 ___ t-~90 (101 .100 (111Pin numbers shown are for OW, JT, and NT packages.TEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-547

SN54AS29821, SN54AS29822, SN74AS29821, SN74AS2982210·BIT BUS INTERFACE FLlP·FLOPS WITH 3·STATE OUTPUTSabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, Vee .................................. : . . . . . . . . . . . . . . . . . . . . .. 7 VInput voltage ............................................................. 5.5 VVoltage applied to a disabled 3-state output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VInput current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 mAOutput current .................................................. - 30 mA to 5 mAOperating free-air temperature range: SN54ALS29821, SN54ALS29822 .' . . . . .. - 55 °e to 125°eSN7 4ALS29821, SN74ALS29822 . . . . . . . . . .. ooe to 70 0 eStorage temperature range ......................................... - 65 °e to 150 0 erecommended operating conditionsrC/)CCD

SN54ALS29821, SN54ALS29822, SN74ALS29821, SN74ALS2982210·BIT BUS INTERFACE FLlp·FLOPS WITH 3·STATE OUTPUTSswitching characteristicsVee - 5 V,Vee - MIN TO MAX, tTEST TA - 25°C TA - MIN TO MAXtFROM TOPARAMETERCONDITIONS 'ALS29821 SN54ALS29821 SN74ALS29821 UNIT(INPUT) (OUTPUT)See Figure 1 'ALS29822 SN54ALS29822 SN74ALS29822MIN TYP MAX MIN MAX MIN MAXtpLHCL = 300 pFtpHLCLK Any QnstpLH6CL = 50 pFtpHL7tpZHCL = 300 pFtpZLDC Any QnstpZH12CL = 50 pFtpZL11tpHZCL = 50 pFtpLZDC Any QnstPHZ5CL = 5 pFtpLZ6t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.Additional information' on these products can be obtained from the factory as it becomes available.•enQ)(.)'SQ)cen...JTEXAS -1!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-549

SN54AS29821. SN54AS29822. SN74AS29821. SN74AS2982210·BIT BUS INTERFACE FLlp·FLOPS WITH 3·STATE OUTPUTSPARAMETER MEASUREMENT INFORMATIONTESTPOINTVCC_fROM OUTPUT ~~~~~~~-arS1 / ~ RL IUNDER TEST 180 !l(S ... ,,,.,1CLSWITCH POSITION TABLETEST S1 S2tPLH Closed ClosedtpHL Closed ClosedtpZH Open ClosedtpZL Closed OpentpHZ Closed ClosedtPLZ Closed ClosedLOAD CIRCUITrC/)cCD

PRODUCTPREVIEWSN54ALS29823, SN54ALS29824SN74ALS29823, SN74ALS298249·BIT BUS INTERFACE FLlp·FLOPS WITH 3·STATE OUTPUTS02825, JANUARY 1986• Functionally Equivalent to AMD's AM29823and AM29824• Provides Extra Data Width Necessary forWider Address/Data Paths or Buses withParity• Outputs Have Undershoot ProtectionCircuitry• Power·Up High·lmpedance State• Buffered Control Inputs to Reduce DCLoading Effects• Package Options Include both Plastic andCeramic Carriers in Addition to Plastic andCeramic DIPs• Dependable Texas Instruments Quality andReliabilitydescriptionThese 9-bit flip-flops feature three-state outputsdesigned specifically for driving highly capacitiveor relatively low-impedance loads. They areparticularly suitable for implementing widerbuffer registers, I/O ports, bidirectional busdrivers, parity bus interfacing and workingregisters.With the clock enable (CLKEN) low, the nine D-. type edge-triggered flip-flops enter data on thelow-to-high transitions of the clock. TakingCLKEN high will disable the clock buffer, thuslatching the outputs. The ' ALS29823 hasnoninverting D inputs and the' ALS29824 hasinverting D inputs. Taking the CLR input lowcauses the nine Q outputs to go lowindependently of the clock.A buffered output-control input (Oe)can be usedto place the nine outputs in either normal logicstate (high or low level) or a high-impedancestate. In the high-impedance state the outputsneither load nor drive the bus lines significantly.The high-impedance state and increased driveprovide t~e capability to drive the bus lines in abus-organized system without need for interfaceor pull-up components. The output control doesnot affect the internal operation of the flip-flops.Old data can be retained or new data can beentered while the outputs are in the highimpedancestate.SN54ALS29823 ... JT PACKAGESN74ALS29823 ... OW OR NT PACKAGE(TOP VIEW)203040 40506070 7Q80 8090 10 15 90ClR 11 14 ClKENGNO 12 13 ClKSN54ALS29823 ..• FK PACKAGESN74ALS29823 ... FN PACKAGE(TOP VIEW)u~ ~Ig ~ ~~ 24 3 2 1 2827 2612 1314 15 16 17 18SN54ALS29824 ... JT PACKAGESN74ALS29824 ... OW OR NT PACKAGE(TOP VIEW)VCC102030 3040 4050 506070 7080 8090 10 15 90ClR 11 14 ClKENGNO 12 13 ClKSN54ALS29824 ... FK PACKAGESN74ALS29824 ... FN PACKAGE(TOP VIEW)u1~1~lg ~ ~~ 24 3 2 1121314151617183040507080•CJ)Q)CJoSQ)cen...JPRODUCT PREVIEW documents contain informationon products in the formative or design phase ofdevelopment. Characteristic data and otherspecifications are design goals. Texas Instrumentsreserves the right to change or discontinue theseproducts without notice.TEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DAllAS. TEXAS 75265Copyright © 1986, Texas Instruments Incorporated2-551

SN54ALS29823, SN54ALS29824, SN74ALS29823, SN74ALS298249·BIT BUS INTERFACE FLlp·FLOPS WITH 3·STATE OUTPUTSThe SN54AS' family is characterized for operation over the full military temperature range of - 55°C to125°C. The SN74AS' family is characterized for operation from OOC to 70°C.'AlS29823 FUNCTION TABLEINPUTSOUTPUTOC ClR ClKEN ClK D 0L L X X X LL H L t H HL H L t L LL H H X X 00H X X X X Z'ALS29823 logic symbol t'ALS29823 logic diagram (positive logic)(23) 1020 (3)(22) 203D (4)(21) 30rencCD

SN54ALS29824, SN74ALS298249-BIT BUS INTERFACE FLIP-FLOPS' WITH 3-STATE OUTP~TS'AlS29824 FUNCTION TABLEINPUTSOC ClR ClKEN ClK 0L l X X XL H l t HL H L t lL H H X XH X X X X• ALS29824 logic symbol tOUTPUT'QlLH00ZI ALS29824 logic diagram (positive logic)Oc ...:.(..:.!1)__________ qClR ....:....;.'-'----

SN54ALS29823. SN54ALS29824. SN74ALS29823. SN74ALS298249·BIT BUS INTERFACE FLlp·FLOPS WITH 3·STATE OUTPUTSabsolute maximum ratings over operating free-air temperature range (unless othe~wise noted)Supply voltage, Vee ................................... ,. . . . . . . . . . . . . . . . . . . . .. 7 VInput voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VVoltage applied to a disabled 3-state output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VInput current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 mAOutput current .................................................. - 30 mA to 5 mAOperating free-air temperature range: SN54ALS29823, SN54ALS29824 . . . . . .. - 55°C to 125°CSN74ALs29823, SN74ALS29824 ........... oDe to 70DeStorage temperature range ........... .' ................... '.......... - 65 DC to 150 DCrecommended operating conditionsIrCJ)CCD

SN54ALS29023. SN54ALS29024. SN74ALS29023. SN74ALS290249·BIT BUS INTERFACE FLlp·FLOPS WITH 3·STATE OUTPUTSelectrical characteristics over recommended operating free·air temperature range (unless otherwisenoted)SN54ALS29823SN74ALS29823PARAMETER TEST CONDITIONS t SN54ALS29824 SN74ALS29824 UNITMIN TYP* MAX MIN TYP* MAXVIK Vee = MIN II = -18 rnA -1.2 -1.2 VVee = MIN to MAX, IOH = -0.4 rnA Vcc- 2 Vcc- 2VOH Vee = MIN, IOH = -15 rnA 2.4 3.3 VVee = MIN, IOH = -24 rnA 2.4 3.2VOLVee = MIN, IOL = 32 rnA 0.25 0.4 0.25 0.4Vee = MIN, IOL = 48 rnA 0.35 0.5IOZH Vee = MAX, Vo = 2.4 V 20 20 J.l.AIOZl Vee = MAX, Vo = 0.4 V -20 -20 ~II Vee = MAX, VI = 5.5 V 0.1 0.1 rnAIIH Vee = MAX, VI = 2.7 V 20 20 J.l.AIII Vee = MAX, VI = 0.4 V -0.1 -0.1 rnAIOS~ Vee = MAX, Vo = 0 -75 -250 -75 -250 rnAICC'AlS29823'AlS29824Vee = MAXOutputs highOutputs lowOutputs disabled 48 48Outputs highOutputs lowOutputs disabled 48 48t For conditions shown as MIN or MAX, use appropriate value specificed under recommended operating conditions.i All typical values are at Vee = 5 V, TA = 25 ce.'§ Not more than one output should be shorted at a time and duration of the short circuit should not e~ceed one second.Additional Information on these products can be obtained from the factory as it becomes available.VrnATEXAS ."INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-555

SN54ALS29823, SN54ALS29824, SN74ALS29823, SN74ALS298249·BIT BUS INTERFACE FLlp·FLOPS WITH 3·STATE OUTPUTSswitching characteristicsVCC - 5 V, Vcc - MIN TO MAX, tTEST TA - 25°C TA - MIN TO MAXtFROM TOPARAMETER CONDITIONS 'AlS29823 SN54AlS29823 SN74AlS29823(INPUT) (OUTPUT)See Figure 1 'AlS29824 SN54AlS29824 SN74AlS29824tpLHCL = 300 pFtpHLClK Any QtpLH 5.5CL = 50 pFtpHl6.5tpHL ClR Any Q CL = 50 pF 13tpZHCL = 300 pFtpZLOC Any QtpZH.12CL = 50 pFtpZL 11tpHZCL = 50 pFtpLZOC Any QtpHZ 5CL = 5 pFtpLZ 5.5MIN TYP MAX MIN MAX MIN MAXUNITnsnsnsns• t Fm coo'Wo", ,howo " MIN 0' MAX, ""

SN54ALS29823, SN54ALS29824, SN74ALS29823, SN74ALS298249·BIT BUS INTERFACE FLlp·FLOPS WITH 3·STATE OUTPUTSPARAMETER MEASUREMENT INFORMATIONTESTPOINTVCC_ -1HHt--I'IIII!t-.... ~JS1"., RL IFROM OUTPUT ~UNDER TEST180 nALL DIODES1N916 OR1N3064SWITCH POSITION TABLETEST S1 S2tplH Closed ClosedtpHl Closed ClosedtpZH Open ClosedtpZl Closed OpentpHZ Closed ClosedtplZ Closed ClosedLOAD CIRCUITTIMING/.,.----- 3 VINPUT_____/:_1.:..5 ~ _____ 0 V:-- t su -eJ4- th ~~-,----3VDATA 1.5 V 1.5 VINPUT0 VVOLTAGE WAVEFORMSSETUP AND HOLD TIMESINPUT J1.5 V ~ 1.5~--: ~tPLH~~tPHLIN-PHASE I /' I i1-"~ VOHeOUTPUT I 1.5 V:I I VOLtpHL~ ~tpLHOUT-OF-PHASE \11.5 V ~ VOHOUTPUT . ;rl.~ \ VOLVOLTAGE WAVEFORMSPROPAGATION DELAY TIMESOUTPUTCONTROLHIGH-LEVEL~---3VPULSE ~1.5 V 1.5 Vl'..-o VLOW-LEVELPULSE14- tw ------.~.5vtw1.5~3V--- - 0 VVOLTAGE WAVEFORMSPULSE DURATIONS~15V F3V~~~·~---OVtpZL~ ~ II J_~L~1.J~~__ ~4.5VI --. VOLI I IWAVEFORM 1 I 1 5 V J..K!I ~ 1.5 V(See Note B) I' I __ of.'PZH~ ;PHZt~1 ~i LO.3 VI - - VOHWAVEFORM 2_ 1 5 V(See Note B) 1.5 V - .0.3 V-------- ",OV•tnQ)CJ0>Q)CCI)...JVOLTAGE WAVEFORMSENABLE AND DISABLE TIMES. THREE·STATE OUTPUTSNOTES: A. Cl includes probe and jig capacitance.B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.C. All input pulses are supplied by generators having the following characteristics: PRR :5 10 MHz. Zo =' 50 n. tr :5 2.5 ns.tf :5 2.5 ns.FIGURE 1TEXAS -I!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-557

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PRODUCTP~EVIEWSN54ALS29825. SN54ALS29826SN74ALS29825. SN74ALS298268·BIT BUS INTERFACE FLlP·FLOPS WITH 3·STATE OUTPUTS02829. JANUARY 1986• Functionally Equivalent to AMD's AM~9825and AM29826• Improved IOH 'Specifications• Multiple Output Enables Allow MultiuserControl of the Interface• Outputs Have Undershoot ProtectionCircuitry• Power-Up High-Impedance State!t Package Options Include Both Plastic andCeramic Chip Carriers in Addition to Plasticand Ceramic DIPs• Buffered Control Inputs to Reduce DCLoading Effect• Dependable Texas Instruments Quality andReliabilitydescriptionThese 8-bit flip-flops feature three-state outputsdesigned specifically for driving highly capacitiveor relatively low-impedance loads. They areparticularly suitable for implementing multiuserregisters, I/O ports. bidirectional bus drivers. andworking registers.With the clock enable .(CLKEN) low. the eight Dtype edge-triggered flip-flops enter data on thelow-to-high transitions of the clock. TakingCLKEN high will disable the clock buffer. thuslatching the outputs. The' ALS29825 has noninvertingD inputs and the • ALS29826 hasinverting D inputs. Taking the CLR input lowcauses the eight Q outputs to go lowindependently of the clock.Multiuser buffered output-control inputs (OC 1.OC2. and OC3) can be used to place the eightoutputs in either a normal logic state (high or lowlevel) or a high-impedance state. In the highimpedancestate the outputs neither load nordrive the bus lines significantly. The highimpedancestate and increased drive provide thecapability to qrive the bus lines in a busorganizedsystem without need for interface orpull-up components. The output controls do notaffect the internal operation of the flip-flops. Olddata can be retained or new data can be enteredwhile the outputs are in the high-impedancestate.SN54ALS29825 ... JT PACKAGESN74ALS29825 ... OW OR NT PACKAGE(TOP VIEW)2030405060 6070 7080 10 80ClR 11 14 ClKENGNO 12 13 ClKSN54ALS29825 .•. FK PACKAGESN74ALS29825 ... FN PACKAGE(TOP VIEW)N _ UM~Iglg ~ ~Ig ~4 3 2 1 2827262D ]5 25 203D ]6 24 304D 7 23( 40NC 8 22( NC50 9 21( 506D 10 20[ 607D 11 19l 7012 1314 151617 180la: CO-JZZ...JUJCD 0 U ~Iz dU

SN54ALS29825, SN54ALS29826SN74ALS29825, SN74A~S298268-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTSThe SN54'family is ~haracterized for operat!on over the full military 'temperature range of - 55°C to 125°C.The SN74' family is characterized for operation from OOC to 70°C. .'ALS29825 FUNCTION TABLEINPUTSO\JTPUT()C* CLR CLKEN CLK 0 QL L . X X X LL H L t H HL H L t L LL H H X X 00H X X X X Z~C' = H if any of OC1, OC2, or OC3 is high.DC' = L if all of DC1, DC2, and OC3 are low., ALS29825 logic diagram (positive logic)oa ..;.(..;.:11________---.OC2~(~2)~------__ --~oa ,,!;12::;:3:;..)_________-'(22) 10, ALS29825 logic symbolt~enCCD

SN54ALS29825, SN54ALS29826SN74ALS29825, SN74ALS298268-BIT BUS INTERFACE FLIP-FLOPS ,WITH 3-STATE OUTPUTS'AlS29826 FUNCTION TABLEINPUTSOC* ClR ClKEN ClK 0L L X X XL H L t HL H L t LL H H X XH X X X XOUTPUTQLLH00Z, ALS29826 logic diagram (positive logic)0C1 ..,.(-'11________--..- (21OC2~(~23~1-------------qOC3 ~"---'--------'ac' = H if any of OC1.,OC2. or OC3 is high.ac' = L if all of OC1. OC2. and OC3 are low.Cl K ~:':"-__ ---l>-.-+-.:.:(2c:;,,2;....1 la, ALS29826 logic symbol tOclOC2Oc3ClRC'i:i

SN54ALS29825; SN54ALS29826SN74ALS29825, SN74ALS298268·BIT BUS INTERFACE FLlp·FLOPS WITH 3·STATE OUTPUTSrecommended operating conditionsSN54AlS29825SN54AlS29826MIN NOM MAXVee Supply voltage 4.5 5 5.5VIH High-level input voltage 2VIL low-level input voltage 0.8IOH High-level output current -15IOl low-level output current 32ClR lowtw Pulse duration elK highelK lowtsu Setup time before elKf DatathHold time, data after elKfelR inactiveelKEN high or lowDataClKENTA Operating free-air temperature -55 125SN74AlS29825SN74AlS29826 UNITMIN NOM MAX4.75 5 5.25 V2 V0.8 V-24 rnA48 rnAnsnsns0 70 °crencCD~.oCDenelectrical characteristics over recommended operating free·air temperature range (unless otherwisenoted)SN54AlS29825SN74AlS29825PARAMETER TEST CONDITIONSt SN54AlS29826 SN74AlS29826MIN TYP* MAX MIN TYP* MAXVIK Vec = MIN. II = -18 rnA -1.2 -1.2Vee = MIN to MAX, IOH = -0.4 rnA Vcc- 2 Vcc- 2VOH Vee = MIN, IOH = -15 rnA 2.4 3.3VOLVee = MIN, 10H = -24 rnA 2.4 3.2Vee = MIN, 10l = 32 rnA 0.25 0.4 0.25 0.4Vee = MIN, IOl = 48 rnA 0.35 0.5IOZH Vec = MAX, Vo = 2.4 V 20 20IOZl Vec '" MAX, Vo = 0.4 V -20 -20II Vee = MAX, VI = 5.5 V 0.1 0.1IIH Vee = MAX, VI =; 2.7 V 20 20III Vee = MAX, VI = 0.4 V -0.1 -0.1IOS§ Vee = MAX, Va = 0 -75 -250 -75 -250lee'AlS29825'AlS29826Vee = MAXOutputs highOutputs lowOutputs disabled 48 48Outputs highOutputs lowOutputs disabled 48 48UNITVVV/lA/lArnA/lArnArnArnAt For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.t All typical values are at Vee = 5 V, T A = 25°e.§ Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.Additional information on these products can be obtained from the factory as it becomes available.2-562 TEXAS.INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

switching characteristicsFROMPARAMETER (INPUT)tpLHtpHltpLHClKTO(OUTPUT)Any QtpHltpHl CLR Any QtpZHtpZlOC Any QtpZHtpZltpHZtpLZOC Any QtpHZtpLZSN54ALS29825, SN54ALS29826SN74ALS29825, SN74ALS298268·BIT BUS INTERFACE FLlp·FLOPS WITH 3~STATE OUTPUTSVee - 5 V,Vee - MIN TO MAX, tTEST TA - 25°C TA - MIN TO MAXtCONDITIONS 'ALS29825 SN54ALS29825 SN74ALS29825 UNITSee Figure 1 'ALS29826 SN54ALS29826 SN74ALS29826MIN TYP MAX MIN MAX MIN MAXCL = 300 pFnsCl = 50 pF67Cl = 50 pF 13 nsCl = 300 pFCL = 50 pFCL = 50 pFCL = 5 pFt For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.Additional information on these products can be obtained from the factory as it becomes available.o flip-flop signal conventions121156It is normal TI practice to name the outputs and other inputs of a O-type flip-flop and to draw its logicsymbol based on the assumption of true data (0) inputs. Then outputs that produce data in phase withthe data inputs are called 0 and those producing complementary data are called Q. An input that causesa 0 output to go high or a 0 output to go low is called Preset; an input that causes a 0 output to go highor a 0 output to go low is called Clear. Bars are used over these pin names (PRE and CLR) if they areactive-low.The devices on this data sheet are second-source designs and the pin-name convention used by the originalmanufacturer has been retained. That makes it necessary to designate the inputs and outputs of the invertingcircuit 0 and O. In some applications it may be advantageous to redesignate the inputs and outputs aso and O. In that case, outputs should be renamed as shown below. Also shown are corresponding changesin the graphical symbol. Arbitrary pin numbers are shown in parentheses.Notice that 0 and 0 exchange names, which causes Preset and Clear to do likewise. Also notice that thepolarity indicators (t::::::.) on PRE and CLR remain since these inputs are still active-low, but that the presenceor absence of the polarity changes at 0, 0, and O. Of course pins 5 (0) is still in phase with the datainput 0, but now both are considered active high.nsnsIII(/)Q)(J"S:Q)cen...JCLR R PRE SQCLK C1 CLK C11DD 10(6)as CLR R(5)aa. TEXAS -I.!}INSTRUMENlSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-563

SN54ALS29825, SN54ALS29826SN74ALS29825, SN74ALS298268·BIT BUS INTERFACE FLlP·FLOPS WITH 3·STATE OUTPUTSPARAMETER MEASUREMENT INFORMATIONTESTPOINTVCC_~HHt-..... t-""~'jS1,/ RL IFROM OUTPUT ~UNDER TEST180 flALL DIODES1N916 OR1N3064SWITCH POSITION TABLETEST 51 52tpLH Closed ClosedtpHL Closed ClosedtpZH Open ClosedtpZL Closed OpentpHZ Closed ClosedtpLZ Closed ClosedLOAD CIRCUITrOOCCD

PRODUCTPREVIEWSN54ALS29827, SN54ALS29828SN74ALS29827, SN74ALS2982810·BIT BUFFERS AND BUS DRIVERS WITH 3·STATE OUTPUTSD2912, JANUARY 1986• Functionally Equivalent to AM29827 andAM29828• 3-State Outputs Drive Bus Lines or BufferMemory Address Registers• P-N-P Inputs Reduce D-C Loading• Data Flow-Thru Pinout (All Inputs onOpposite Side from Outputs)• Power-Up High-Impedance State• Package Options Include Both Plastic andCeramic Chip Carriers in Addition to Plasticand Ceramic DIPs• Dependable Texas Instruments Quality andReliabilitydescriptionThese 10-bit buffers and bus drivers providehigh-performance bus interface for wide datapaths or busses carrying parity,The three-state control gate is a 2-input NORsuch that if either G1 or G2 is high, all tenoutputs are in the high-impedance state.The ' ALS29827 provides true data and the'ALS29828 provides inverted data at theoutputs.The SN54' family is characterized for operationover the full military temperature range of- 55 DC to 125 DC. The SN74' family ischaracterized for operation from 0 DC to 70 DC.SN54AlS' ... JT PACKAGESN74ALS' . , , OW OR NT PACKAGE(TOP VIEW)(31 VCCA1Y1A2Y2A3Y3A4Y4A5Y5A6Y6A7Y7A8Y8A9Y9'A10Y10GNDG2SN54ALS' ... FK PACKAGESN74AlS' ... FN PACKAGE(TOP VIEW)UN,,-,,-UU"-N« « It:) z > >- >-4 3 2 1 2827 26A3 25 Y3A4 6 24 Y4A5 7 23 Y5NC 8 22 NCA6 9 21 Y6A7 10 20 Y7A8 11 19 Y812 13 14 15 16 17 18cnOClUNOcn« ..- Z Z It:) ..- >-«t:) >-•(J)Q)(.)oSQ)Cen-IPRODUCT PREVIEW documents contain informationCopyright © 1986, Texas Instruments Incorporatedon products in the formative or design ~hase ofdevelopment. Characteristic data and otherspecifications are design goals. Texas InstrumentsTEXAS ..2-565reserves the right to chenge or discontinue these INSTRUMENTSproducts without notice.POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SN54ALS29827, SN54ALS29828SN74ALS29827, SN74ALS2982810-BIT BUFFERS AND BUS DRIVERS WITH 3-STATE OUTPUTSlogic symbols t'ALS29827'ALS29828Al (21A2 (31. A3 (41A4 (51AS (61A6 (71A7 (SIAS (91A9 (101Al0 (111(231 Vl(221 V2(211 V3(201 V4(191 V5(lSI V6(111 V7(161 VS(151 Y9(141 Vl0Al (21A2 (3)A3 (4)A4 (51AS (61A6 (71A7 (S)AS (91A9 (10)Al0 (11)tThese symbols are in accordance with ANSI/IEEE Std 91·1984 and lEG Publication 617·12.EIr-C/)logic diagrams (positive logic)'ALS29827(;1 (1) G1 (1)(;2 (13) G2 (13)A1 (2) (23) V1 A1 (2)'ALS29828(23) V1CCD

SN54ALS29827, SN54ALS29828SN74ALS29827, SN74ALS2982810-BIT BUFFERS AND BUS DRIVERS WITH 3-STATE OUTPUTSabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, Vee ......................................................... 7 VInput voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VVoltage applied to a disabled 3-state output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VOperating free-air temperature range: SN54ALS29827, SN54ALS29828 ..... : - 55°C to 125°CSN74ALS29827, SN74ALS29828 .......... ooe to 70 D eStorage temperature range ............................... ,......... - 65 DC to 150 DCrecommended operating conditionsSN54ALS29827SI\I74ALS29827SN54ALS29828 SN74ALS29828 UNITMIN NOM MAX MIN NOM MAXVee Supply voltage 4.5 5 5.5 4.75 5 5.25 VVIH High-level input voltage 2 2 VVil Low-level input voltage 0.8 0.8 VIOH High-level output current -15 -24 mAIOL Low-level output current 32 48 mATA Operating free-air temperature - 55 125 a 70 °eelectrical characteristics over recommended operating free-air temperature range (unless otherwise noted) ~PARAMETERTEST CONDITIONStSN54ALS29827SN74ALS29827SN54ALS29828 SN74ALS29828MIN Typf MAX MIN Typf MAXVIK Vee = MIN, II = -18 mA -1.2 -1.2Vee = MIN to MAX, IOH = -0.4 mA VCC- 2 VCC-2VOHVOLVee = MIN, IOH = -15 mA 2Vee = MIN, IOH = -24 mA 2Vee = MIN, IOl = 32 mA 0.25 0.4 0.25 0.4Vee = MIN, IOl = 48 mA 0.35 0.5IOZH Vee = MAX, Vo = 2.4 V 20 20IOZl Vee = MAX, Vo = 0.4 V -20 -20II Vee = MAX, VI = 5.5 V 0.1 0.1IIH Vee = MAX, VI = 2.7 V 20 20IlL Vee = MAX, VI = 0.4 V -0.1 -0.1IOS§ Vee = MAX, Vo = a -75 -250 -75 -250leeOutputs high 16 16'AlS29827 Vee = MAX Outputs low 20 20Outputs disabled 19 19Outputs high 12 12'ALS29828 Vee = MAX Outputs low 16 16Outputs disabled 14 14t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.tAli typical values are at Vee = 5 V, TA = 25°e.§ Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.Additional information on these products can be obtained from the factory as it becomes available.UNITVVVf'Af'AmAf'AmAmAmAmA(J)Q)()'S;Q)cen..J. TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-567

IItSN54Als29827, SN54ALS29S28SN74ALS29827, SN74ALS2982810-BIT BUFFERS AND BUS DRIVERS WITH 3-STAtE OUTPUTSswitching characteristicsVee - 5 V,Vee - MIN TO MAX,tTEST TA - 25°C TA - MIN TO MAXtFROM TOPARAMETER CONDITIONS 'ALS29827 SN54ALS29827 SN74ALS29827(lNPUTI (OUTPUTISee Figure 1 'ALS29828 . SN54ALS29828 SN74ALS29828tPLH8CL = 300 pFtpHL 11A VtpLH5CL = 50 pFtpHL 5tpZH 11CL = 300 pFtpZL18G VtpZH 7CL = 50 pFtpZL10tpHZ 11CL = 50 pFtpLZ5G ytpHZ 4CL = 5 pFtpLZ4MIN TYP MAX MIN MAX MIN MAXFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.Additional information on these products can be obtained from the factory as it becomes available.UNITnsnsns2-568 TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54ALS29827, SN54ALS29828SN74ALS29827, SN74ALS2982810-BIT BUFFERS AND BUS DRIVERS WITH 3-STATE OUTPUTSPARAMETER MEASUREMENT INFORMATIONTESTPOINTVCC_~~~~~~.-~S1 / RL IFROM OUTPUT ~UNDER TEST180 nCL,5,. N", "1ALL DIODES1N916 OR1N3064SWITCH POSITION TABLETEST S1 S2tpLH Closed ClosedtpHL Closed ClosedtpZH Ope.n ClosedtPZL Closed OpentpHZ Closed ClosedtpLZ Closed ClosedLOAD CIRCUITTIMING ~ 3 VINPUT___DATAINPUT ~ I .... vINPUT J.1.5...J.4-:- 1 .:.. 5 ~ __ ---0 V.. t su ""'- th ~. ~;.;;-3VVOLTAGE WAVEFORMSSETUP AND HOLD TIMESVtPLHh·~OV~ 1.5~--::~tPHLIN-PHASE I /1.· I i1 __ "~ VOHOUTPUT I 1.5 V: eI I VOLtpHL -14-----+1 I4----++- tpLHOUT-OF-PHASE \1.5 V F VOHOUTPUT • . VOLVOLTAGE WAVEFORMSPROPAGATION DELAY TIMESHIGH.LEVELPULSELOW-LEVELPULSE~---3V-./f1.5V 1.5V~:...- tw --...I 0 V~tw43V1.5 V 1.5 V----OVVOLTAGE WAVEFORMSPULSE DURATIONSOUTPUTCONTROL ~1.5V E11.5V3V~ -----OVtPZL..-.! j+- Ii ~ ~:_1. -l,"-= -- -4.5 VI I IWAVEFORM 1 I 15V ~I ",,1.5V(See Note B) I' I __!:.I -. VOL'PZH~ ;PHZt~l4-i LO.3 VI - - VOHWAVEFORM 2-1 5 V(See Note B) 1.5V - .0.3 V-------- ""QVVOLTAGE WAVEFORMSENABLE AND DISABLE TIMES. THREE-STATE OUTPUTSen(1)(.)os:(1)CCI'J...JNOTES: A. CL includes probe and jig capacitance.B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.C. All input pulses are supplied by generators having the following characteristics: PRR :s 10 MHz. Zo = 50 n. tr :s 2.5 ns,tf :s 2.5 ns.FIGURE 1TEXAS ..INSTRUMENlSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-569

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PRODUCT·PREVIEWSN54ALS29861, SN54ALS29862SN74ALS29861, SN74ALS2986210-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS02915. JANUARY 1986• Functionally Equivalent to AM29861 andAIVI29862• Choice of True or Inverting Logic• Power-Up High-Impedance State• Package Options Include Both Plastic andCeramic Chip Carriers in Addition to Plasticand Ceramic DIPs• Dependable Texas Instruments Quality andReliabilitydescriptionThese 10-bit bus transceivers are designed forasynchronous two-way communicationbetween data buses. The control functionimplementation allows for maximum flexibility intiming.These devices allow data transmission from theA bus to the B bus or from the B bus to the Abus depending upon the logic levels at the enableinputs (GBA and GAB).The enable inputs can be used to disable thedevice so that the buses are effectively isolated.The SN54' family is characterized for operationover the full military temperature range of- 55 DC to 125 DC. The SN74' family ischaracterized for operation from 0 DC to 70 DC.INPUTSFUNCTION TABLEOPERATIONGAB GBA ALS29861 ALS29862L H A to B A to BH L B to A B to AH H Isolation IsolationL L Latch A and B Latch A and B(A=B)(A=B)SN54ALS· ... JTPACKAGESN74ALS' ... OW OR NT PACKAGEA3A4ASNCA6A7A8GABA1A2A3A4A5A6A7A8A9A10GND(TOP VIEW)VCCB1B2B3B4B5B6B7B8B9B10GBASN54ALS' ... FK PACKAGESN74ALS' ... FN PACKAGE(TOP VIEW)aJ UN ....

SN54ALS29861, SN54ALS29862SN74ALS29861, SN74ALS2986210·BIT BUS TRANSCEIVERS WITH 3·STATE OUTPUTSlogic symbols t'ALS29861'ALS29862IIrC/)B8B9C~ tThese symbols are in accordance with ANSI/IEEE Std 91·1984 and lEe Publication 617·12.Pin numbers shown are for DW, JT, and NT packages.c:;'CDen2·572 TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

SN54ALS29861, SN54ALS29862SN74ALS29861, SN74ALS2986210-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTSlogic diagrams'ALS29861'ALS29862GABGABA1(23)B1(23)B1A2(3)(22)B2(22)B2A3(4)(21)B3A3 (4) (21) B3A4(5)(20)B4(20) B4A5A6A7AS(6)(7)(S)(9)(19)B5(1S)86(17) B7(16)BSA6 --___ 1---4.-.-.(19) B5(18) B6(17)B7(16)B8ElltnQ)(.)oSQ)Cen...IA9(10)(15)89A9 (10)(15) B9A10(11)(14)B10(14)A10 -.:.(_11..;..)__.......--1 ~~~--- B10Pin numbers shown are for DW, JT, and NT packages.TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-573

SN54ALS29861, SN54ALS29862SN74ALS29861, SN74ALS2986210-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTSlEIelectricalrtJ)C(1)

SN54ALS29861, SN54ALS29862SN74ALS29861, SN74ALS2986210-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS• ALS29861 switching characteristicsFROMPARAMETER(INPUT)tpLHtpHLtpLHtpHLtpZHtpZLtpZHtpZLtpHZtpLZtpHZtpLZA or BTO(OUTPUT)B or ATESTCONDITIONSSee Figure 1CL = 300 pFCL = 50 pFGAB CL = 300 ~ForGBAGABorGBAA or BA or BCL = 50 pFCL = 50 pFCL = 5 pFVee - 5 V,Vee - MIN TO MAX, tTA - 25°C TA - MIN TO MAXt'ALS29861 SN54ALS29861 SN74ALS29861MIN TYP MAX MIN MAX MIN MAX81155111771011544UNITnsnsns, ALS29862 switching characteristicsPARAMETERtPLHtpHLtpLHtpHLtpZHtpZLtpZHtpZLtpHZtPlZtpHZtpLZFROM(INPUT)A or BGABorGBAGABorGBATO(OUTPUT)B or AA or BA or BTESTCONDITIONSSee Figure 1CL = 300 pFCL = 50 pFCl = 300 pFCl = 50 pFCl = 50 pFCl = 5 pFvce - 5 V,Vee - MIN TO MAX, tTA - 25°C TA - MIN TO MAXt'ALS29862 SN54ALS29862 SN74ALS29862MIN TYP MAX MIN MAX MIN MAX71145111771011544UNITnsnsnstJ)Q)(.)oS;Q)cen...Jt For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.Additional information on these products can be obtained from the factory as it becomes available,'. TEXAS.INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-575

SN54ALS29861, SN54ALS29862SN74Als29861~ SN74ALS29862.. .10-81T BUS TRANSCEIVERS WITH 3-STATE OUTPUTSpARAMETER MEASUREMENT INFORMATIONTESTPOINTVCCSl_fROM OUTPUT ----4HHI....._--....-

PRODUCTPREVIEW9·~ITSN54ALS29863, SN54ALSZ9864SN74ALS29863, SN74ALS29864BUS TRAN~CEIVERS WITH3·STAT~ OUTPUTS02915, JANUARY 1986• Funqtionally Equivalent to AM29863 andAM29864• Choice of True pr Inverting Logic• Power-Up High-Impedance State• Package Options Include Both Plastic andCeramic Chip Carriers in Addition to Plasticand Ceramic DIPs• Dependable Texas Instruments Quality andReliabjlity

SN54ALS29863, SN54ALS29864SN74ALS29863, SN74ALS298649-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTSlogic symbols t'ALS29863'ALS29864.1r(J)CCD

SN54ALS29863. SN54ALS29864SN74ALS29863. SN74ALS298649·BIT BUS TRANSCEIVERS WITH 3·STATE OUTPUTSabsolute maximum ratings over operating free·air temperature range (unless otherwise noted)Supply voltage, Vee ......................................................... 7 VInput voltage: All inputs and I/O ports: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 VOperating free-air temperature range: SN54ALS29863, SN54ALS29864 . . . . . .. - 55°C to 125°CSN74ALS29863, SN74ALS29864 ........... ooe to 70°CStorage temperature range ......................................... - 65°C to 150 °erecommended operating conditionsSN54ALS29863SN74ALS29863SN54ALS29864 SN74ALS29864 UNITMIN NOM MAX MIN NOM MAXVee Supply voltage 4.5 5 5.5 4.5 5 5.5 VVIH High-level input voltage 2 2 VVIL Low-level input voltage 0.8 0.8 VIOH High-level output current -15 -24 mAIOL Low-level output current 32 48 mAIIITA Operating free-air temperature - 55 125 0 70 DCelectrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)SN54ALS29863SN74ALS29863PARAMETER TEST CONDITIONSt SN54ALS29864 SN74ALS29864MIN TYP* MAX MIN TYP* MAXVIK Vee = MIN, II =-18 mA -1.2 -1.2Vee = MIN to MAX, IOH = -0.4 mA VCC-2 VCC-2VOH VCC = MIN, 10H = -15 mA 2VOLVee = MIN, 10H = -24 mA 2Vee = MIN, IOH = -32 mA 0.25 0.4 0.25 0.4Vee = MIN, 10L = 48 mA 0.35 0.5II Vce = MAX, VI = 5.5 VControl inputs 20 20IIHVee = MAX,VI = 2.7 VA or B ports§20 20Control inputs -0.1 -0.1IlL Vee = MAX, VI = 0.4 VA or B ports§ -0.1 -0.1lOS' Vee = MAX, Vo = 0 -75 -250 -75 -250ICCOutputs high 26 26'ALS29863 Outputs low 35 35Vee = MAXOutputs disabled 34 34Outputs high 20 20·'ALS29864 Outputs low 27 27Outputs disabled 26 26t For conditions shown as MIN or MAX, use appropriate value specified under recommended operating conditions.+ All typical values are at Vee = 5 V, TA = 25 D e.§ For I/O ports, the parameters IIH and IlL include the off-state output current., Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.UNITVVVmAp.AmAmAmAU)Q)CJoS;Q)CCJ)...JTEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • OALLAS. TEXAS 752652-579

SN54ALS29863. SN54ALS29864SN74ALS29863. SN74ALS298649·BIT BUS TRANSCEIVERS WITH 3·STATE OUTPUTS, AlS29863 switching characteristicsVee - 5 V.TESTFROM TO TA - 25°CPARAMETERCONDITIONS(INPUT) (OUTPUT) 'ALS29863See Figure 1MIN TYP MAXtpLH 8CL = 300 pFtpHL11A or B B or AtPLH5.CL = 50 pFtpHL 5tpZHtpZLtpZHtpZLtpHZtpLZtpHZtpLZGABorGBAGABorGBAA or BAorBCL = 300 pFCL = 50 pFCL = 50 pFCL = 5 pF111771011544Vee - MIN TO MAX. tT A - MIN TO MAX tSN54ALS29863 SN74ALS29863MIN MAX MIN MAXUNITnsnsns• • ALS29864 switching characteristicsrCJ)CCD

SN54AlS29063, SN54AlS29064SN74AlS29063, SN74AlS290649·BI1 BUS TRANSCEIVERS WITH 3·STATE OUTPUTSPARAMETER MEASUREMENT INFORMATIONTESTPOINTVCC1_FROM OUTPUT --tHH........ t-.... -

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THCT1010-160M, THCT1010-140E, THCT1010-10016-B11 BY 16-BIT MULTIPLIERS/ACCUMULATORS02834, SEPTEMBER 1984-REVISED SEPTEMBER 1985• 16-Bit by 16-Bit ParallelMultiplication/ Accumulation• 35-Bit-Wide Accumulator• Inputs are TTL-Voltage Compatible• Outputs Capable of Driving up to 10 LSTTLLoads• Single 5-V Power Supply• Low Power Dissipation ... 150 mWTypical• Pin-for-Pin Compatible with TRW TDC1010J(DIP only) and AM29510 (DIP only)• High-Speed Twin-Well CMOS Process• Package Options Include Ceramic andPlastic Chip Carriers and DIPs• Dependable Texas Instruments Quality andReliabilitydescriptionThe THCT1 01 0 is a TTL-voltage-compatible,low-power, high-speed 16-bit by 16~bitmultiplier/accumulator for digital signalprocessing, digital filters, fast Fouriertransformations, -array processing, andmicroprocessor throughput enhancement. Th~sedevices are pin-for-pin equivalent to the TRWTDC1010J but dissipate 20 times less power.The lower power dissipation causes thedifferences between junction and ambienttemperatures to be minimized and, therefore,eliminates the heat-sink requirements andincreases reliability. High speed is aChieved'QYusing a modified Booth algorithm, a feed-forwardcarry circuit, and a conditional sum adder thatenhances the final adder stage of the multiplier.The THCT1 01 0 inputs consist of three registers,a 1 6-bit X input, a 16-bit Y input, and an inputcontrol register. The 35-bit output productregister consists of a 16-bit most-significantproduct(MSP) bus, a .16-bit least-significantproduct(LSP) bus that is shared with the 16-bitY input bus, and a 3-bit extended-product (XTP)bus (PR32 thrqugh PR34); see the functionalblock diagram. The input registers areYl/PRI 10Y2/PR2 11Y3/PR3 12Y4/PR4 13Y5/PR5 14Y6/PR6 15Y7/PR7 16GND 17VCC 18YS/PRS 19Y9/PR9 20YIO/PRIO 21YII/PRII 22YI2/PRI2 23YI3/PRI3 24YI4/PRI4 25YI5/PRI5 26JD OR N DUAL-IN-liNE PACKAGE(TOP VIEW)X6 64 X7X5 63 XBX4 3 62 X9X3 61 XIOX2 60 XIIXl 59 Xl2XO 58 Xl3YO/PRO 57 Xl4YI/PR1 56 Xl5Y2/PR2 10 55 OElSY3/PR3 11 54 RNDY4/PR4 12 53 SUBY5/PR5 13 52 ACCY6/PR6 14 51 elK XY7/PR7 15 50 elK YGND 16 49 VceYB/PRS 17 48 TCY9/PR9 18 47 OEXYIO/PRlO 19 46 PRElYll/PRll 20 45 OEMSYI2/PRl2 21 44 elK PRYI3/PRl3 22 43 PR34Yl4/PRl4 23 42 PR33YI5/PRl5 24 41 PR32PRl6 25 40 PR31PRl7 26 39 PR30PRIS 27 38 PR29PRl9 28 37 PR2BPR20 29 36 PR27PR21 30 35 PR26PR22 31 34 PR25PR23 32 33 PR24FK OR FN CHIP-CARRIER PACKAGE(TOP VIEW)O ...... ('\,jMo:tLOO ...... NMo:tl.O(Or--.Q)m ......................... .....xxxxxxxxxxxxxxxx9 8 7 6 54 3 2 1686766656463626160[ OElS59[ RND58[ SUB57[ Ace56[ elK x55[ elK Y54 [ VCC53[ GND52[ NC51 TC50 OEX49 PREl48 OEMS47 ClK PR46 PR3445 PR3344 PR322728293031323234353637383940414243NC - No internal connectionCaution_ These devices have limited built-in gate protection. The leads should be shorted together or the deviceplaced in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.PRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instrumentsstandard warranty. Production processing does notnecessarily include testing of all parameters.Copyright © 1984, Texas Instruments IncorporatedTEXAS ~2-583INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

THCT1 01 0·160M, THCT1 01 0·140E, THCT1 01 0·1 0016·81T 8Y 16·81T MULTIPLIERS/ACCUMULATORSindependently controlled by ClK X andClK Y, and the product registers are D-type positive-edge-triggeredflip-flops. Separate three-state Qutput enables are provided for each output product register. These, incombination with the independent input clocks, allow operation on a microprocessor bus.The THCT1 01 0 has a round control (RND) ~hat rounds the product to the 19 most significant bits. Thepreload control (PREl) is used in conjunction with the output enables to initialize the contents of the outputregisters. The THCT 1010 will perform multiplication and addition, multiplication and subtraction, or straightmultiplication depending upon the states of the accumulate control (ACC) and subtractor control (SUB).The TC control provides the ~apability of formatting the i'nput data to be either two's complement or unsignedmagnitude.The THeT1 01 0-160M is characterized for operation over the full military temperature range" of - 55°Cto 125°C. The THCT1 01 0-140E is characterized for operation from - 40°C to 85 cc. The THCT1 01 0-1 00is characterized for operation from O°C to 70 o e .rOOCCD

THCT10l0·160M, THCT10l0·140E, THCT10l0·l00,16·BIT BY 16·BIT MULTipLIERS/ACCUMULATORSPINNO.NAME56-64,1-7 X15 thru XO8-15,17-24 YO/PROthruY15/PR1525-43 PR16 thru PR3444 ClK PR45 OEMS46 PREl47 OEX48 TC50 ClK Y51 ClK X52 ACC53 SUB54 RND55 OElSDESCRIPTIONX data inputs, X 15 is the most-significant bit. The data is loaded into the X register onthe rising edge of ClKX.110 ports for least significant product (lSP) bits of output product register, input ports forY data. YO/PRO is the least significant bit. The mode is controlled by the PREl and OEMSpins.1/0 ports for output product register bits. PR 16 through PR31 are the most-significantproduct (MSP) bits. PR32 through P.R34 are the extended product (XTP) bits. The mode iscontrolled by PREl, OElS, OEX.Product clock input. On the low-to-high transition, latches the lSP, MSP, and XTP intothe output product register.Active-low output enable for MSP output product registe~. When high, causes the PR31through PR 16 outputs to be i!1 the high-impedance state.Preload control. When high, the output product registl!r's outPUts are disabled. When anoutput enable (OElS, OEMS, OEX) is high, preload data can be entered into the outputproduct register from the PR 1/0 lines on the rising edge of ClK PRoActive-low output enable for XTP output product register. When high, causes t~e PR32through PR34 outputs to be in the high-impedance state.Two's complement control. When TC is high, the input da~a "is in two's complementformat. When TC is low, the input data is in unsigned magnitude format. The TC signal isloaded into the control register on the rising edge of d.K X or ClK Y.Y clock input. On the low-to-high transition, clocks data in from the Y inputs.X clock input. On the'low-to-high transition, clocks data in from the X inputs.Accumulator control. When ACC is high and SUB is low, the cOntent of the outputproduct register is added to the next product generated. The sum is then placed in theoutput prodl!ct register on the rising edge of ClK PRo When ACC is lo~, the product isstored directly into the output register on the rising edge of ClK PRo The ACC signal isloaded into the control register at the rising edge of ClK X or ClK Y.Subtraction control. When SUB and ACC are high, the content of the output productregister is subtracted from the next product generated. The result is then placed in theoutput product register on the rising edge of ClK PRo When SUB is low and ACC is high,the addition operation is performed instead of subtraction. When ACC is low, SUB is a"Don't Care". The SUB signal is loaded into the control register on the rising edge of ClKX or ClK Y.Round control. When high, causes the product of the X and Y inputs to be rounded to the19 most significant bits by adding a 1 to the MSB of the lSP. The RND signal is loadedinto the control register on the rising edge of ClK X or ClK Y.Active-low output enable for lSP output product register. When high, causes the PROthrough PR15 outputs to be in the high-impedance state.enCD(.)"s.:CDC-en..oJPin numbers shown are for the JD and N packages.TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-585

THCT1 01 0-16oM, THCT1 01 0-140E, THCT1 01 0-1 0016-BIT BY 16-BIT MULTIPLIERS/ACCUMULATORSPRELOAD FUNCTION TABLEPREL OEX OEMS OELS XTP MSP LSPL L L L (PR32-PR34) (PR16-PR31 ) (PRO-PR15)L L L H (PR32-PR34) (PR16-PR31) ZL L H L (PR32-PR34) Z (PRO-PR15)L L H H (PR32-PR34) Z ZL H L L Z (PR16-PR31) (PRO-PR15)L H L H Z (PR16-PR31 ) ZL H H L Z Z (PRO-PR15)L H H H Z Z ZH L L L Z Z ZH L L H Z Z PLH L H L Z PL ZH L H H Z PL PLH H L L PL Z ZH H L H PL Z PLH H H L PL PL ZH H H H PL PL PLPL = Output buffers at high impedance or output disabled. Preload data supplied externally atoutput pins will be loaded into the output register on the rising edge of eLK PRorencCD

THCT1010·160M, THCT1010·140E, THCT1010·10016·81T 8Y 16·81T MULTIPLIERS/ACCUMULATORSlogic diagram (positive logic)ClK PRPR El~ lSDE" MSc;--- EXCl KX~ C1X15-XO10 16XI~Y15-YOPR15-PROJMUlTl-16 C1PLiER"' ARRAY C2[ C1REGADDERISUB-.,C1L-c EN 16X \lTRACTOR 16 -1.20 1.20R NO10~- L-c EN 16X \lPR31-PR16A CC10 r- 16~1.20 1.20S UB-.-1310 I-TC103 --< EN 3X \l , PR34-PR32I-1.20 1.20 ~'kClK YC116 16S' J•16, 1016X16,Pin numbers shown are for the JD and N packages.(/)Q)absolute maximum ratings over operating free·air temperature range tCo)'SSupply voltage range, VCC .. _.... _............. _.................. _.. -0.5 V to 7 V Q)Input diode current, 11K (VI < 0 or VI > VCC) ..... _... _.......... _. . . . . . . . . . . .. ± 20 mA cOutput diode current, 10K (VO < 0 or Vo > Vcc) . _. . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mAContinuous output current, 10 (VO = 0 to Vcc) .. _............... _..... _.. _.. _. ± 25 mA enContinuous current through VCC or GND pins. _...... _............. _...... _.. _. ± 50 mA ...JLead temperature 1,6 mm (1116 inch) from case for 60 seconds. _.. _..... _. . . . . . . . . .. 300°CStorage temperature range ...... _...... _...... ~ __ . . . . . . . . . . . . . . . . .. - 65 °C to 150°CtStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.recommended operating conditionsTHCT1010-160M THCT1010·140E THCT1010-100MIN NOM MAX MIN NOM MAX MIN NOM MAXUNITVee Supply voltage 4.5 5 5.5 4.5 5 5.5 4.5 5 5.5 VVIH High-level input voltage I Vee = 4.5 V to 5.5 V 2 2 2 VVIL Low-level input voltage I Vee=4.5Vt05.5V 0 0.8 0 0.8 0 0.8 VVI Input voltage 0 Vee 0 Vee 0 Vee VVo Output voltage 0 Vee 0 Vee 0 Vee Vtt Input transition (rise and fall) times 0 500 0 500 0 500 nsTA Operating free-air temperature -55 125 -40 85 0 70 DeTEXAS -I!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-587

THCT1010·160M. THCT1010·140E. THCT1010·10016·BIT BY 16·BIT MULTIPLIERS/ACCUMULATORSelectrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)PARAMETER TEST CONDITIONS VCCVOHVOLTA - 25°CTHCT1010-160MTHCT1 01 0-140ETHCT1 01 0-1 00MIN TYP MAX MIN MAX MIN MAXVI = VIH or Vll, 10H = - 20 p.A 4.5 V 4.4 4.4 4.4VI = VIH or Vll, 10H = -4 rnA 4.5 V 3.86 3.7 3.76VI = VIH or Vll, 10l = 20 p.A 4.5 V 0.1 0.1 0.1VI = VIH or Vll, 10l = 4 rnA 4.5 V 0.32 0.4 0.37II VI = 0 to VCC 5.5 V ±5 ±100 ± 1000 ± 1000 nA10Z Vo = VCC or 0, VI = VIH or Vil 5.5 V ±0.01 ±0.5 ±10 ±5 p.AICC t VI = VCC or 0, 10 = 0 5.5 V 0.75 2 1 rnA4.5 VCi to 3 10 10 10 pFtSee Figure 4.5.5 Vtiming requirements over recommended operating free-air temperature range (unless otherwise noted)THCT1010-160M. THCT1010-140EUNITVVrencCD

THCT1010·160M, THCT1010·140E, THCT1010·10016·81T 8Y 16·81T MULTIPLIERS/ACCUMULATORSswitching characteristics over recommended operating free·air temperature range (unless otherwisenoted), CL = 50 pF (see Figure 3) .THCT1010-160M, THCT1010-140EtpdtenPARAMETERPropagation delay timeEnable timeVCCTA - 25°C THCTlOl0-160M THCTlOl0-140EMIN TypT MAX MIN MAX MIN MAX4.5 V 45 65 555.5 V 60 504.5 V 35 65 455.5 V60 404.5 V 35 60 45tdis Disable time ns5.5 V 55 40tmaccMultiply/accumulate time4.5 V 100 160 1405.5 V 140 120UNITnsnsnsPower dissipation capacitance No loap, TA = 25°e 750 pF typTHCT1 01 0-1 00VCCTA = 25°CTHCT10l0-l00MIN Typt MAX MIN MAXtpd Propagation delay time 4.75 V 35 45 nsten Enable time 4.75 V 30 40 nstdis Disable time 4.75 V 30 40 nst macc Multiply/accumulate time 4.75 V 90 100 nstTypical values are at Vee = 5 V.3V'TC'RND'~ 1.3VLACC, SUB : : 0 V1 I1 1 3VX INPUT ~ 1.3Vry INPUT ~ If'-- 0 V. PARAMETER MEASUREMENT INFORMATION~tsu""'th-.j~ I ----3VClK X 1.3V 1.3VClK Y le---tw--.l 0 v14---- t macc"-1 ,--__'" ,----"'----- 3VClK PR ______________________ 1.3 -11 V ~ ____________________ 1.3V -JI~----- OVI+-tpd-+lII ___ ~I _____... 3VOElS, OEMS,OEXOUTPUTSPRElJ1.3V \1.3 V : /- i L ov·!.-.t-tdis * ten *..J.-...I I tsu I. .i. th4I I I _________ """\ I 1~--.--,;H-i.Z----

THCT1010·160M, THCT1010·140E, THCT1010·10016·BIT BY 16·BIT MULTIPLIERS/ACCUMULATORSPARAMETER MEASUREMENT INFORMATION~ 3VO'EiS, OEMS, OEX i\1.3 V t·~ _' ________ 0OUTPUTWAVEFORM 1(See Note),'-------------'1t+--tpz L ----.I14--tPLZ---.tI : I 1 ""VCCII ~1.3V, 'I !/-~ I jl10%I i -- VOL11.3 V!4--tPZH-.II, iOUTPUTWAVEFORM 2l ~-- --- VOH(See Note)---------. I4---tPHZ--+1 .., 0 VNOTE: Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform 2 is for an output with internal conditons such that the output is high except when disabled by the output control.FIGURE 2. DETAILED VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMESVrencCD

THCT1010·160M, THCT1010·140E, THCT1010·10016·BIT BY 16·BIT MULTIPLIERS/ACCUMULATORSTHERMAL INFORMATIONTHERMAL RESISTANCEJUNCTION-TO-CASEJUNCTION-TO-FREE-AIRPACKAGE PINS THERMAL RESISTANCE. ROJC THERMAL RESISTANCE. ROJA1°C/WI1°C/WIFK 68 8 36FN 68JD .64 9 32N 64ORDERING INSTRUCTIONSTHCT 1010 - 100~- ~-------------~! . /(2. Circuit Designator)I-----------------------'3. Speed Selection }-______________________ -J- 100 ... 100 ns tmacc (THCT1 01 0-1 00 only)- 140 ... 140 ns tmacc (THCT1 01 0-140E only)- 160 ... 160 ns tmacc (THCT1 01 0-160M only)JDE•FK (Ceramic leadless chip carrier)FN (Plastic leaded chip carrier)JD (Ceramic DIP)N (Plastic DIP)5. Temperature Range J..---------------------JME(Blank)-55°C to 125°C-40°C to 85°CO°C to 70°CTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-591

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PRODUCTPREVIEWTHCT2000M, THCT2000EDIRECTION DISCRIMINATORS• Inputs are TTL- and CMOS-VoltageCompatible• Interfaces Mechanical Devices to Data Bus• Identifies and Measures Forward orBackward Rotation or Direction• Measures Pulse Duration and Frequency• Cascadable 16-Bit Up/Down Counter• 8-Bit Parallel 3-State Bus with Each. OutputCapable of Driving up to 15 LSTTL Loads• Dependable Texas Instruments Quality andReliabilitydescriptionThe THCT2000 direction discriminator candetermine the direction and displacement of amechanical device based on input signals fromtwo transducers in quadrature. It can alsomeasure a pulse duration using a known clockrate, or a frequency over a known time interval.It includes a 16-bit counter, which can be usedseparately. Several of these devices may becascaded to provide accuracy greater than16-bits.The device may be used in many diverseapplications. and is specifically designed for usein many types of microprocessor-based systems.Some of the possibilities include motor controls.robotics. tracker balls (mice). lathe or toolingmachines. automobiles, and conveyer belts orother transport mechanisms.The THCT2000M is characterized for operationover the full military temperature range of- 55 DC to 125 DC. The THCT2000E ischaracterized for operation from - 40 °C to85 D C.THCT2000M ... JD PACKAGETHCT2000E ... JD OR N PACKAGE0203GNO04050607(TOP VIEW)CSRO a'00 BID1WE02 RESET03 LSB/MSBGNOCLK04 B05 A06 MO07 M1BOM2COREADYGNORLl/RLO02889 •. NOVEMBER 1985VecTHCT2000M ... FK PACKAGETHCT2000E ..'. FN PACKAGE(TOP VIEW)uo g I~ I~~lulCil4 3 2 1 2827265 256 247 . 238 229 2110 2011 191213141516171810 IDUZ-lO::::::10 0 10 \>- N ....t:)££Q)cen....IPRODUCT PREVIEW documents contain informationon products in the formative or design !lhase ofdevelopment. Characteristic data and otherspecifications are design goals. Texas Instrumentsreserves the right to change or discontinue theseproducts without notice.TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1985. Texas Instruments Incorporated2-593

THCT2000M,THCT2000EDIRECTION DISCRIMINATORSlogic symbol tA (20)B (21)MO(19)UPDOWNDIRECTIONDISCRIMINATORA I DIRECTIONB SIGNALSTHCT2000MAXCTMINCTM1 (1B) o I MODE RE'GISTERM2 (17)0(13)CO(12)85(3) DO(4)01(5) 02(6) 03~ SELECT 4(B) 045(9) 05CLOCK(10) 06(11) 07LSB/MSB BYTE SELECTCHIP SELECTREADY(16) READYrencCD

THCT2000M, THCT2000EDIRECTION DISCRIMINATORSPINNAMENUMBERA, B 20,21i3i 26BO 12CI 27ClK 22CO 13CS 100-07 3,4,5,6,8,9,10,11GNO 7,14lSB/MSB 23MO, Ml, M2 19, 18, 17RD 2READY 16RESET 24RLi/RlO 15VCC 28WE 25DESCRIPTIONSignal measurement inputs.Cascade input for counting down. In mode 0, i3i is used as the clock input for counting down.Triggering occurs on the high-to-Iow transition.Counter output underflow signal. Active (low) for a duration equal to the low level of the input clock.Cascade input for counting up. In mode 0, CI is used as the clock input for counting up. Triggeringoccurs on the high-to-Iow transition.Clock input. Used for internal synchronization and control timing.Counter output overflow signal. Active (low) for a duration equal to the low level of the input clock.Chip select input. This active-low input is used to enable read and write functions. For additionaldetails, see read and write timing diagrams.Counter load inputs/register output data lines.Pins 7 and 14 are both internally connected to the ground rail of the integrated circuit but both shouldbe connected to the system ground for proper operation.Byte select input. During read operations, a high level selects the least significant byte, while a lowlevel selects the most significant byte. For write operations, this input directs the data on the businto the least significant or most significant byte position of the counter. See write timing diagramsfor additional details.Mode select inputs.Read input. When active (low) in conjunction with CS low, the data stored in the output register willbe present on the data bus as selected by the lSB/MSB input. See read timing diagrams for additionaldetails.Ready output. When active (low), this output indicates to the processor that it may complete the read. or write operation. READY is synchronous with the negative-going edge of ClK. This output requiresa pullup resistor (1 kn nominal).Counter and control logic reset. When active (low), the counter is asynchronously reset to zero whilethe control logic is asynchronously initialized to the proper state as determined by the mode controlinputs. The output register is not affected by RESET.Register load input/register load output (open drain). This pin can be used as an input to directly loadthe output register, or it can be used as an output to detect whenever the output register has beenloaded. When used as an output, a pullup resistor (1 kn nominal) is required. See read timing diagramsfor additional details.Power supply voltage.Write enable input. When active (low) in conjunction with CS low, the data present on 00-07 will beasynchronously loaded into the counter as selected by lSB/MSB. See write timing diagrams foradditional details.IIItJ)Q)CJ0>Q)cen...ITEXAS -1.!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-595

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THCT4502DYNAMIC RAM CONTROLLER02905, OCTOBER 1985• Inputs are TTL- and CMOS-VoltageCompatible• Controls Operation of 64K and 256KDynamic RAMs• Creates Static RAM Appearance• One Package Contains Address Multiplexer.Refresh Control. and Timing Control• Directly Addresses and Drives Up to 2Megabytes of Memory Without ExternalDrivers• Operates from Microprocessor ClockNo Crystals. Delay Lines. or RCNetworksEliminates Arbitration Delays• Refresh May Be Internally or ExternallyInitiated• VersatileStrap-Selected Refresh RateSynchronous. Predictable RefreshSelection of Distributed. Transparent.and Cycle-Steal Refresh ModesInterfaces Easily to PopularMicroprocessorsAsynchronous RESET Function Providedin FK and FN Packages• High-Performance Si-Gate CMOSTechnology• Strap-Selected Wait State Generation forMicroprocessor/Memory Speed Matching• Ability to Synchronize or InterleaveController with the Microprocessor System(Including Multiple Controllers)• 3-State Outputs Allow Multiport MemoryConfiguration• Performance Range:125 ns ALE low to CAS low• Compatible with TMS4500A/B and with VTIVL4500A and VL4502• Available in Plastic and Ceramic ChipCarriers in Addition to Plastic and CeramicDIPs• Dependable Texas Instruments Quality andReliabilityTHCT4502 ... JD OR N PACKAGEACWCASORAOMAOMA1CA1RA1CA2MA2GNOMA3CA3RA3MA4CA4RA4MA5CA5RA5RA6CA6MA6(TOP VIEW)ACRRAS1RASaALEcsRENOROYClKRAS3RAS2CAS1GNOREN1VCCMASCASRA8REFREQTWSTFSOFS1RA7CA7MA7THCT4502 ... FK OR FN PACKAGE(TOP VIEW)9 8 7 6 5 4 3 2 1 6867666564636261NC ~10 60 NCNC ]11 59 NCCA1 12 58 ClKRA 1 13 57 RAS3RA2 14 56 RAS2CA2MA2GNDGNDMA3CA3RAS3MA4CA4RA4NCNC151655 CAS154 GND17 53 REN118 52 VCC19 51 VCCW ~ MAS21 49( CA822 48( RAS23 47 ~ RESET24 46( REFREQ25 45~ NC26 44( NC2728293031323334353637383940414243NC - No internal connectiontJ)Q)(JoSQ)cen..oJPRODUCTION DATA documents contain informationCopyright © 1985, Texas Instruments Incorporatedcurrent as of 'publication date. Products conform tothese specifications ~er the terms of TexasInstruments standard warranty, ProductionTEXAS -II}2-597processing does not necessarily include testing of all INSTRUMENTSparameters,POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

THCT4502DYNAMIC RAM CONTROLLERdescriptionThe THCT4502 is a monolithic DRAM system controller providing address multiplexing, timing, controland refresh/access arbitration functions to simplify the interface of dynamic RAMs to microprocessorsystems.The controller contains an 18-bit multiplexer that generates the address lines for the memory device fromthe 18 system address bits and provides the strobe signals required by the memory to decode the address.A 9-bit refresh counter generates up to 512 row addresses required to refresh.A refresh timer is provided to generate the necessary timing to refresh the dynamic memories and ensuredata retention.The THCT4502 also contains refresh/access arbitration circuitry to resolve conflicts between accessrequests and memory-refresh cycles.The THCT 4502 is characterized for operation from 0 DC to 70 DC.functional block diagramr-enCCD

THCT4502DYNAMIC RAM CONTROLLERpin descriptionsRAO-RA8CAO-CA8MAO-MA8ALERENO, REN1ClKRASO, RAS1RAS2, RAS3RDYInputInputOutputInputInputInputsInputInputInputOutputOutputOutputRow Address - These address inputs are used to generate the row addressfor the multiplexer.Column Address - These address inputs are used to generate the columnaddress for the multiplexer.Memory Address - These three-state outputs are designed to drive theaddresses of the dynamic RAM array.Address latch Enable - This input is used to latch the 18 address inputs,CS, RENO, and REN 1. This also initiates an access cycle if CS is low. Therising edge (low level to high level) of ALE returns all RAS outputs to thehigh level.Chip Select - A low on this input enables an access cycle. The trailingedge of ALE latches the chip select input.RAS Enable 0 and 1 - These inputs are used to select one of four banksof RAM when CS is low. When REN1 is low, the lower banks are enabledvia CASO, RASO, and RAS1. When REN1 is high, the higher banks areenabled via CAS1, RAS2 and RAS3. RENO selects RASO and RAS2 whenlow, or RAS1 and RAS3 when high. (see Table 2).Access Control, Read; Access Control, Write - A low on either of theseinputs causes the column address to appear on MAO-MA8 and a low-goingpulse from CAS. The rising edge of ACR or ACW terminates the cycle byforcing RAS and CAS high. When ACR and ACW are both low, MAO-MA8,RASO, RAS 1, RAS2, RAS3, CASO and CAS 1 go into a high-impedance(floating) state.System Clock - This input provides the master timing to generate refreshcycle timings and refresh rate. Refresh rate is determined by the TWST,FS,1, and FSO inputs.Refresh Request - This input should be driven by an open-collector or opendrainoutput. On input, a low-going edge initiates a refresh cycle and willcause the internal refresh timer to be reset on the next falling edge of theClK. As an output, a low-going edge signals an internal refresh requestand that the refresh timer will be reset on the next low-going edge of ClK.REFREQ will remain low until the refresh cycle is in progress andthe current refresh qddress is present on MAO-MA8. (Note: REFREQcontains an internal active pullup with a nominal resistance of 10 kO, whichis disabled when REFREQ is low).Row Address Strobe - These three-state outputs are used to latch therow address into the bank of DRAMs selected by RENO and REN 1. Onrefresh, all RAS signals are active.Column Address Strobe - These three-state outputs are used to latch thecolumn address into the DRAM array.Ready - This totem-pole output synchronizes memories that are too slowto guarantee microprocessor access time requirements. This output is alsoused to inhibit access cycles during refresh when in cycle-steal mode.TEXAS ...INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-599

THCT4502 . .DYNAMIC RAM CONTROLLERpin ci~scriptions (continued)TWSTFSO, FS1RESETtInputInputsInputTiming/Wait Strap - A high on this input indicates a wait state should beadded to each memory cycle. In addition it is used in conjunction with FSOand FS 1 to determine refresh rate and timing or initialize the controller.Frequency Select 0; Frequency Select 1 - These are strap inputs to selectMode and Frequency of operation as shown in Table 1.RESET - Active-low input to initialize the controller asynchronously.Refresh Address is set to IFF16, internal refresh requests, synchronizer,and frequency divider are cleared. (Note: RESET contains an internal pullupresistor with a nominal resistance of 100 kO, which allows this pin to beleft open.)tThis function is available only in the FK and FN packages.TABLE 1. STRAP CONFIGURATIONSTRAP INPUT MODESWAITSTATES MINIMUM CLOCKFOR CLOCK REFRESH CYCLESMEMORY REFRESH FREQUENCY FREQUENCY FOR EACHTWST FS1 FSO ACCESS RATE (MHz) (kHz) REFRESHL L L t 0 EXTERNAL - REFREQ 4L L H 0 EXTERNAL - REFREQ 3L H L 0 CLK .;. 61 3.904 64·95; 3L H H 0 CLK .;. 91 5.824 64-8S§ 4H l l 1 ClK .;. 61 3.904 64-95; 3H l H 1 ClK .;. 91 5.824 64-75; 4H H l 1 ClK.;. 106 6.784 64-73; 4H H H 1 ClK.;. 121 7.744 64-831 4t This strap configuration resets the Refresh Timer Circuitry.; Upper figure in refresh frequency is the frequency that is produced if the minimum clock frequency of the next select state is used.§ Refresh frequency if clock frequency is 8 MHz.1 Refresh frequency if clock frequency is 10 MHz.TABLE 2. OUTPUT STROBE SELECTIONCONTROL INPUTSELECTED OUTPUTREN1 RENO RASO RAS1 RAS2 RAS3 CASO CAS1l l X Xl H X XH l X XH H X XNOTE: Changing the logic value of REN 1 after a low-to-high transition of ALE and before ACX rises causes the other CAS to fall. BothCAS signals remain low until ACX rises.functional descriptionThe THCT4502 consists of six basic blocks: address and select latches, refresh rate generator, refreshcounter, the multiplexer, the arbiter, and the timing and control block.2-600 TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

THCT4502DYNAMIC RAM CONTROLLERaddress and select latchesThe address and select latches allow the DRAM controller to be used in systems that multiplex addressand data on the same lines without external latches. The row address latches are transparent, meaningthat while ALE is high, the output at MAO-MAS follows the inputs RAO-RAS.refresh rate generatorThe refresh rate generator is a counter that indicates to the arbiter that it is time for a refresh cycle. Thecounter divides the clock frequency according to the configuration straps as shown in Table 1. The counteris reset when a refresh cycle is requested or when TWST, FS1, and FSO are low. The configuration strapsallow the matching of memories to the system access time. Upon power-up it is necessary to providea reset signal by driving all three straps to the controller (or RESET for devices in the FK and FN packagesonly) low. A systems power-on reset (RESET) can be used to do this by connecting it to those strapsthat are desired high during operation. During this reset period, at least four clock cycles should occur.refresh counterThe refresh counter contains the address of the row to be refreshed. The counter is decremented aftereach refresh cycle. A low-to-high transition on TWST sets the refresh counter to 1FF16 (51110).multiplexerarbiterThe multiplexer provides the DRAM array with row, column, and refresh addresses at the proper times.Its inputs are the address latches and the refresh counter. The outputs provide up to 1S multiplexedaddresses on nine lines.The arbiter provides two operational cycles: access and refresh. The arbiter resolves conflicts betweencycle requests and cycles in execution, and schedules the inhibited cycle when used in cycle-steal mode.timing and control blockThe timing and control block executes the operational cycle at the request of the arbiter. It provides theDRAM array with RAS and CAS signals. It provides the CPU with a RDY signal. It controls the multiplexerduring all cycles. It resets the refresh rate generator and decrements the refresh counter during refreshcycles.absolute maximum ratings over operating free-air temperature range (unless otherwise noted) tSupply voltage range, VCC (See Note 1) ................................ - 1.5 V to 7 VInput diode current, 11K (VI < 0, VI > Vcc) .................................. ± 20 mAOutput diode current, 10K (Va < 0, Va > Vcc) ............................... ± 20 mAContinuous output cLirrent, 10 (Va = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mAContinuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mAOperating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooC to 70°CStorage temperature range ......................................... - 65°C to 150°CLead temperature 1,6 mm (1/16 inch) from case for 60 seconds: FK or JD package . . . . . .. 300°CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds: FN or N package. . . . . . .. 260°Ct Stresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only,and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions"section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTE 1: Voltage values are with respect to network ground ..•t/)Q)(Jas:Q)cen..JTEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-601

THCT4502DYNAMIC RAM CONTROLLER.recommended operating conditionsMIN NOM MAX UNITVee Supply voltage 4.5 5 5.5 VVIH High-level input voltage 2 VCC+ O.5 VVIL Low-level input voltage -0.5 t O.S VVo Output voltage -0.5 VCC+O.5 Vtt Input transition (rise and falll time 0 500 nsTA Operating free-air temperature 0 70 °et The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logicvoltage levels only.electrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)rmcCD

THCT4502DYNAMIC RAM CONTROLLERtiming requirements over recommended ranges of supply voltage and operating free-air temperature(unless otherwise noted)THCT4502-125PARAMETERMINMAXUNITtc(C) ClK cycle time 100 nstw(CH) ClK high pulse duration 45 nstw(Cl) ClK low pulse duration 45 nstAEl-Cl Time delay, ALE low to ClK starting low (see Note 1) 25 nstCl-AEl Time delay, ClK low to ALE starting low (see Note 1) 15 nstCl-AEH Time delay, ClK low to ALE 15 nstw(AEH) Pulse width ALE high 45 nstAV-AEl Time delay, address REN 1, CS valid to ALE low 10 nstAEl-AX Time delay, ALE low to address not valid 15 nstAEl-ACl Time delay, ALE low to ACX low (see Notes 3, 4, 5, and 6) thlRA) +30 nstACH-Cl Time delay, ACX high to ClK low (see Notes 3 and 7) 30 nstACl-CH Time delay, ACX low to ClK starting high (to remove ROY) 30 nstRQL-Cl Time delay, REFREQ low to ClK starting low (see Note 8) 35 nstw(RQl) Pulse width REFREQ low 30 nstw(ACl) ACX low width (see Note 9) 120 nstreset Power-up reset 4tcCLK nsNOTES:1. Coincidence of the trailing edge of ClK and the trailing edge of ALE should be avoided as the refresh/access occurs on thetrailing ClK edge.2. If ALE rises before ACX and a refresh request is present, the falling edge of ClK after tCl-AEH will output the refresh addressto MAO-MA7 and initiate a refresh cycle.3. These specifications relate to system timing and do not directly reflect device performance.4. On the access grant cycle following refresh, the occurrence of CAS low depends on the relative occurrence of ALE low toACX low. If ACX occurs prior to or coincident with ALE, then CAS is timed from the ClK high transition that causes RASlow. If ACX occurs20 ns or more after ALE, then CAS is timed from the ClK low transition following the ClK high transitioncausing RAS low.5. For maximum speed access (internal delays on both access and access grant cycles). ACX should occur prior to or coincidentwith ALE.6. th(RA) is the dynaiTIic memory row address hold time. ACX should follow ALE by tAEl-CEl in systems where the requiredth(RA) is greater than tREl-MAX minimum.7. The minimum of 20 ns is specified to ensure arbitration will occur on falling ClK edge, tACH-Cl also affects precharge timesuch that the minimum tACH-Cl should be equal or greater than: tw(RH) - tw(Cl) + 30 ns (for a cycle where ACX highoccurs prior to ALE high) where tw(RH) is the DRAM RAS precharge time.8. This parameter is necessary only if refresh arbitration is to occur on this low-going ClK edge (in systems where refresh issynchronized to external events).9. The specification tw(ACl) is designed to allow a CAS pulse. This assures normal operation of the device in testing and systemoperation.t/)Q)(,)oS;cQ)en....ITEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-603

THCT4502DYNAMIC RAM CONTROLLERswitching characteristics over recommended supply voltage range and operating free-air temperaturerange (see Figure 1)IIrrn- cCD

THCT4502DYNAMIC RAM CONTROLLERswitching characteristics over recommended supply voltage range and operating free-air temperaturerange (see Figure 1) (continued)PARAMETERTEST CONDITIONSTHCT4502-125tCH-REl Time delay, ClK high till access RAS starting low Cl = 180 pF 60 nstCl-CElTime delay, ClK low to access CAS starting low(see Note 12)Cl = 360 pF 100 nstCl-MAX Row address valid after ClK low Cl = 360 pF 25 nstREl-MAX Row address valid after RAS low Cl = 360 pF 25 nstAEH-MAX Column address valid after ALE high Cl = 360 pF 10 nstdis Output disable time (3-state outputs)Cl = 360 pF125 nsten Output enable time (3-state outputs)Cl = 360 pF75 nstCAV-CElTime delay, column address valid toCAS starting low after refresh (see Note 12)Cl = 360 pF 0nstCH-CEltt(CEl)tt(CEH)tt(REl)tt(REH)tt(MAV)tt(RYl)tt(RYH)Time delay, ClK high to access CAS starting low(see Note 13)CAS fall timeCAS rise timeRAS fall timeRAS rise timeAddress transition timeRDY fall timeRDY rise timeCl = 360 pFCl = 360 pFCl = 360 pFCl = 180 pFCl = 180 pFCl -180 pFCl = 40 pFNOTES: 12. The occurrence of CAS low is guaranteed not to occur until the column address is valid on MAX.13. On the access grant· cycle following refresh, the occurrence of CAS low depends on the relative occurrence of ALE low to Q)ACX low. If ACX occurs prior to or coincident with ALE then CAS is timed from the ClK high transition that causes RAS low. CIf ACX occurs 20 ns or more after ALE then CAS is timed from the ClK low transition following the ClK high transitioncausing RAS low. (See Refresh Cycle Timing Diagram)(JJ-ICl -40 pF'PARAMETER MEASUREMENT INFORMATIONMINMAX18020503040402050UNITnsnsnsnsnsnsnsnstnQ)(.)os:. FIGURE 1. LOAD CIRCUITTEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-605

THCT4502DYNAMIC RAM CONTROLLERCLK1r-----~~~~190%1.3 V............. ~ .... 1':"0-:%-:::-:' 1 1'"-__ ..1ICL-AELH I "'.;1;VICL):t I.- IIj4-IW(AEH)~ ~ I t L .J tCL-AEH1 t--*tAEL-CL ~r-------------;""'--~ALE ..s.1.3 V \1.3 V I fl.3 V "\ 3 V--J'l /- 1'1 I "---OV1 I 1 ItAV-AEL /f ~..., tAEL-AX / I I1 I I IREN~REN1, / 1 ----3VROW,COL,Cs_ 1.3V(ACR or ACW)I'~I I r--tAEL-ACL~tACL-CH----.\ 1 t4-tACH-CL-.II3V-----OV1 I I 1 1""''T77'T77'T77'T77'T77'T77T1T--- 3 V1~1.3V I 11.3VII//////IIII///OVI ~ I : 1 --t I4-tt(REH)I I / ~,\4-tt(REL) / I t~CH-RE~:- ..... ----~--....,.----=~(I / I !4-tAEH-REH -+.~".,.,..----------- VOHiiAS I I ~~3%V 1 10 % I 1 '10% 1~~~IRAV-MAVIIII ~ I o:.r---------- VOLI I· 1 I / I I4-tAEH-~AX..,r+--IAEH-MAV~ 90% ~tACL-MAX ~tACH-MAXrC/)CCD

THCT4502DYNAMIC RAM CONTROLLERACR.jWjOUTPUTWAVEFORM 1(See Note 16)OUTPUTWAVEFORM 2(See Note 16)~ . r------------ 3 Vi\"'1._3_V __________ -Jt~3.: _ _ _ _____ 0 VIIIf--ten --.l14--tdis---.jI I III '\ I -VeeI '\."'.------...: -----~ - - - - - VOL/4--ten---.lII~------+I-----R -----VOH-------- ~tdis--.l -0 VVOLTAGE WAVEFORMSNOTE 16: Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the access controls.Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the access controls.CLK \--_...JXFIGURE 4. ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS\ ;: \ ;: \~r~~ __..JI I I ,......--- I! : ;"---",=,"",\ :ALEACX ---~I ____ ~ __--~-~~~I~--~-------~----~-------: \ t \\*\: tCL.RFH~: j( :r-+tCL-MAYMAO-MA7 ===x: REFRESH ADDRESS X4 t CH-MAX: KtCH.RRL ~tCH'RRHRAS I ~~ _________ ~~~tMAV-RRL~ROW ADDRESStCH.RELHIIX .._____j.-.J-tCL-MAXtcAy.CEL~! \: !I tCL-CEL: ~ ~~tcH-cELtlLt On access grant cycle following refresh, CAS low and address multiplexing are timed from ClK high transition (tCH-CEl) if ACX lowoccurs prior to or coincident with the falling edge of ALE.: On access grant cycle following refresh, CAS low and address multiplexing are timed from ClK low transition (tCl-CEl) if ACX low occurs20 ns or more after the falling edge of ALE.NOTE 15: All input pulses are supplied by generators having the following characteristics: PRR :s 1 MHz, Zout = 50!}, tr = 6 ns, tf = 6 ns.FIGURE 5. REFRESH CYCLE TIMING (THREE CYCLE)Q)(.)'>cQ)en-oJTEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-607

THCT4502DYNAMIC RAM CONTROLLERCLKALE __ ~ ______ ~~~ ____ ~ ______________ ~ ______________ ~ ______ ~ ______ _ACX\t$t\tCH-RFH~REFREQ __ ~ __ ~ __ ~ ________________ ~~tcL-MAVtCH-MAXMAO-MA7REFRESH ADDRESSRASCAS~tCH-RRL------~I------~I I~ __ ~ __________________ ~1414------'-.-..1-1 tMAV-RRLIII tCL-CEL * ~ .,\.-- tCH-CEl t --+j\..rencCDc:::n"CDent On access grant cycle following refresh, CAS low and address multiplexing are timed from ClK high transition (tCH-CEl) if ACX lowoccurs prior to or coincident with the falling edge of AlE_* On access grant cycle following refresh, CAS low and address multiplexing are timed from ClK low transition (tCl-CEl) if ACX low occurs20 ns or more after the falling edge of AlE_NOTE 15: All input pulses are supplied by generators having the following characteristics: PRR :$ 1 MHz, Zout = 50 n, tr = 6 ns, tf = 6 ns_CLKALE Jt\ACX(ACR or ACW)ACCESS2 I 3II "'"":I-------JIFIGURE 6. REFRESH CYCLE TIMING (FOUR CYCLE)IREFRESH/ACCESS GRANTACCESSI W, I W2 I 2 I 3 I 2 I 32MAX~~~~__....J/ROY\,---1 ----IFIGURE 7. TYPICAL ACCESS/REFRESH/ACCESS CYCLE (THREE-CYCLE, TWST IS LOW)2-608 TEXAS l!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

CLKI 1ALEh II ACCESS2 I 3REFRESH/ACCESS GRANTTHCT4502DYNAMIC RAM CONTROLLERW1 I W2 I W3 I 2 I 3 I 4 1 I 2 I~--,--~~----,;h~1 _I I I IACX I I(ACR or ACW) I I I I IMAX I8 COLUMN ---RE-FR-ES"--H -~ COLUMN ~RAS iI I t I I I t I ICAS I i \! tI i \! ! II i '+REFREQ I \\\\\\\\\\\\\ I I I I I I •1'\1ROY I I I I I ~. --,---~/I I I I I IFIGURE 8. TYPICAL ACCESS/REFRESH/ACCESS CYCLE (FOUR-CYCLE; TWST IS LOW)ICLKACCESSREFRESH/ACCESS GRANTI 1 I W1 I 2 3 I 1 I W1 I W2 I W3 I 2 3 I 1 I W1 I 2 II~---Ihloo.....l.....-I ----:.....--~ ______ALE Y.\._IAC~ hi I_~I II(ACR or ACW) I ~~---i~--:------:~MAX I COLUMN COLUMNIRASi I I I ICAS I i \ ! ! I-I ~~~---:---JREFREQ I \\\\\\~~ IIROY T'iJ1 II I I II ~ __ -'----~FIGURE 9. TYPICAL ACCESS/REFRESH/ACCESS CYCLE (THREE-CYCLE. TWST IS HIGH)TEXAS -1!1INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-609

THCT4502DYNAMIC RAM CONTROLLERIrencCD

THCT4502DYNAMIC RAM CONTROLLERORDERING INSTRUCTIONS~~ ______ ~ ______________________--J~THCT4502 - 125 JDCircuit DesignatorSpeed Selection }--__________________ --J-125 ... 125 ns. ALE to CAS lowN. JD (Dual in-line packages)FK. FN (Chip carrier packages)(f)Q)(.)oS;Q)Cen..oJTEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-611

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PRODUCTPREVIEWTHCT29520, THCT29521MULTILEVEL PIPELINE REGISTERS02925. NOVEMBER 19B5-REVISED APRIL 1986• Four a-Bit Registers• Dual 2-Level or Single 4-Level PipelineRegisters• Any One of Four Registers Selectable forOutput• High-Speed Low-Power CMOS Logic• Fully TTL Compatible• Dependable Texas Instruments Quality andReliabilitydescriptionThe THCT29520 and THCT29521 are highspeedCMOS multilevel pipeline registers. Theyare interchangeable with the Advanced MicroDevice bipolar AM29520 and AM29521 butdissipate a fraction of the power.NT OR OW PACKAGE(TOP VIEW)10 vee11 so (MUX SEllDOS1 (MUX SEll01 YO02 Y103 Y204 Y305 Y406 Y507 Y6elKY7GNOOEThe THCT29520 and THCT29521 contain four 8-bit positive-edge-triggered registers. The registers canoperate as one set of 4-level pipeline registers or two sets of 2-level pipeline registers. The output canbe selected from anyone of the four registers.The THCT29520 and THCT29521 differ in the way data is transferred in the dual 2-level register modes(I = 01 or 10). For the THCT29520, new data is written into the first-level register while the old datain the first-level register is shifted into the second-level register. For the THCT29521, new data is writtenover the old data in the first-level register. The data in the second-level register remains unchanged.The THCT29520 and THCT29521 are characterized for operation from 0 °C to 70°C. The THCT29520Eand THCT29521 E are characterized for operation from - 40°C to 85 DC.enQ)CJos:Q)cen-ID~THCT29520 MODESB8 D~ B 8B1 B2D~ BE] B E111.10 - 00 11.10-01 11.10 - 10 11.10 - 11SHIFT A B SHIFT B SHIFT A HOLD11 10 OPERATION A1 A2 B1 B2L L SHIFT A 8 D A10 A20 81 0L H SHIFT 8 A10 A20 D 81 0H L SHIFT A D A10 81 0 82 0H H HOLD A10 A20 81 0 82 0PRODUCT PREVIEW documents contain informationon products in the formative or design phase ofdevelopment. Characteristic data and otherspecifications are design goals. Texas Instrumentsreserves the right to change or discontinue theseproducts without notice.TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1985. Texas Instruments Incorporated2-613

THCT29520, THCT29521MULTILEVEL PIPELINE REGISTERSD~THCT29521 MODESBElD-€] BB1 B2D-BB E1 E1'11.10 - 00 11.10 - 01 11.10-10SHIFT A B LOAD B LOAD AB BE1 B11.10 - 11HOLD11 10 OPERATION A1 A2 B1L L SHIFT A B D A10 A20L H LOAD B A10 A20 DH L LOAD A 0 A20 B10H H HOLD A10 A20 B10B2B10B20B20B20IrencCD< logic symbols tc:;'CDen113)OE123)SO(22)S111}10(2)11CLK (11)THCT29520PIPELINE REGISTEREN IOUTPUT ENABLE)~ } G ~ IREGISTER SELECT)~ } M ~ [MODE SELECT)ZS [CLOCK)OUTPUT FUNCTION TABLEINPUTS OUTPUTOE S1 SO YL L L B2L L H B1L H L A2L H H A1H X X ZOE (13)SO (23)S1 122}10 (1)11 (2)CLK (11)THCT29521PIPELINE REGISTEREN [OUTPUT ENABLE)~ } G~ IREGISTER SELECT)~ } M ~ [MODE SELECT)ZS [CLOCK)B x MUXZ7 13IA1)(3)DO'V(4)01ZS 12 'V02 IS) IA2] 'V03 (6) 'V04 17} Z6'VOS IS}Z9 11 'V06 (9)'V07 (10) 240[B1) 'V(21) VODO120} V1 (4)01(19) V2 02 IS}11S) V3 03 (6)(17) V4 04 (7) Z6(16) VS OS IS)11S} V6 06 19}114) V7 07 110}B x MUXZ7 13[A1]'VZS 12 'V[A2) 'V'V'VZ9 11 'V240'V[B1) 240 'V(21) VO(20) V1(19) V211S) V3117) V4(16) VS11S} V6114) V7S 109 [B2)[B2)10tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.2-614 TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

THCT29520, THCT29521MULTILEVEL PIPELINE R~GlSTERSlogic diagram (positive logic)OE (13)SO (23)Sl (22)10 (1)11 (2)ClK (11)3"V"V"V"V"V"V"V8 "V0(21) VO(20) Vl(19) V2(18) V3(17) V4(16) V5(15) V6Ell(14) V7(/)Q)CJ'S;Q)CfJ)...J• The label "OC4/2C4" means that the clock in register A2 affects the eight data inputs of that register, collectively labeled "4D", onlyin modes 0 and 2 (11, 10 = L Land H L, respectively). This logic diagram applies specifically for the THCT29520. For the THCT29521,the labels marked with the asterisks in registers A2 and 82 would both be reduced to "OC4" indicating that these clocks have effectonly in mode 0 in that device. Otherwise this diagram applies to both devices.absolute maximum rating over operating free-air temperature range (see Note 1)Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 VInput diode current, 11K (VI < 0 or VI > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mAOutput diode current, 10K (Va < 0 or Va > VCC .............................. ± 20 mAContinuous output current, 10 (Va = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mAContinuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. ± 70 mALead temperature 1,6 mm (1/16 inch) from case for 60 seconds. . . . . . . . . . . . . . . . . . . . .. 300 0 CStorage temperature range ......................................... - 65 °C to 150 °CNOTE 1: Stress beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stressratings only and functional operation of the device at these or any other conditions beyond those indicated in the "recommendedoperating conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extendedperiods may affect device reliability.TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • OALLAS. TEXAS 752652-615

THCT29520, THCT29521MULTILEVEL PIPELINE REGISTERSrecommended operating conditionsVee Supply voltageVIH High-level input voltageVil low-level input v6.1tageVI Input voltageVo Output voltagett Input transition (rise and fall) timeTA Operating free-air temperatureTHCT29520ETHCT29521EMIN NOM MAX4.5 5 5.520 0.80 Vee0 Vee0 500-40 85THCT29520THCT29521MIN NOM MAXUNIT4.5 5 5.5 V2 V0 0.8 V0 Vee V0 Vee V0 500 ns-0 70 °eelectrical characteristics over recommended operating temperature range, VIotherwise noted)... '"VIH or VIL (unless....enc(1)

THCT29520, THCT29521MULTILEVEL PIPELINE REGISTERSswitching characteristics over recommended free-air temperature range, CL = 50 pF (unless otherwisenoted) See Note 2THCT29520ETHCT29520PARAMETER FROM TO VCCTA - 25°CTHCT29521ETHCT29521MIN TYP MAX MIN MAX MIN MAXtpd elK t y4.5 V 18 27 265.5 V 16 25 24tpd SO, S1 y4.5 V 17 27 265.5 V 15 25 24tenOE! y4.5 V 10 16 155.5 V 7 15 14tdisOE t y4.5 V 14 20 205.5 V 13 20 204.5 V 7 12 12ttY5.5 V 7 12 12UNITnsnsnsnsnsPower dissipation capacitance ttNo load dynamic power dissipation, Pd = epd Vee 2 f + lee VeeNOTE 2: For load circuit and voltage waveforms, see page 1-14 of the High-Speed CMOS Logic Data Book, 1984.TEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-617

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TMS2150CACHE ADDRESS COMPARATORD2911. MARCH 1982-REVISED SEPTEM8ER 1985• Fast Address to Match Valid Delay - ThreeSpeed Ranges: 35 ns, 45 ns, 55 ns• 512 x 9 Internal RAM• 300-Mil 24-Pin Ceramic Side-Brazed orPlastic Dual-In-Line or Small OutlinePackages• Max Power Dissipation: 660 mW• On-Chip Parity Generation and Checking• Parity Error Output/Force Parity Error Input• On-Chip Address/Data Comparator• Asynchronous, Single-Cycle Reset• Easily Expandable• Fully Static• Reliable SMOS (Scaled NMOS) Technologyo TTL- and CMOS-Compatible Inputs andOutputsow. JD. OR NT PACKAGE(TOP VIEW)RESETVCCA5A1A4AOA3A8A2A703 A600 0501 0402 07W 06PEMATCHGNOSdescriptionThis S-bit-slice cache address comparator consists of a high-speed 512 x 9 static RAM array, paritygenerator, parity checker, and 9-bit high-speed comparator. It is fabricated using N-channel silicon gatetechnology for high speed and simple interface with MOS and bipolar TTL circuits. The cache addresscomparator is easily cascadable for wider tag addresses or deeper tag memories. Significant reductionsin cache memory component count, board area, and power dissipation can be achieved with this de,vice.When S is low and IN is high, the cache address comparator compares the contents of the memory locationaddressed by AO-AS with the data on 00-07 plus generated parity. An equality is indicated by a high levelon the MATCH output. A low-level outp'ut from PE signifies a parity error in the internal RAM data. PEis an N-channel open-drain output for easy OR-tying. During a write cycle (S and W low), data on 00-07plus generated even parity are written in the 9-bit memory location addressed by AO-AS. Also during write,a parity error may be forced by holding PE low.IA RESET input is provided for initialization. When RESET goes low, all 512 x 9 RAM locations are clearedand the MATCH output is forced high.The cache address comparator operates from a single + 5 V supply and is offered in a 24-pin 300-mil ceramicside brazed or plastic dual-in-line packages. The device is fully TTL compatible and is characterized foroperation from 0 DC to 70 DC.C/)Q)(,)'SQ)c(J)....IMATCH OUTPUT DESCRIPTIONFUNCTION TABLEMATCH = VOH if: [AO-A8] = 00-07 + parity.or: FiES'Ei' = VIL.or: S = VIH.or: W = VILMATCH = VOL if: [AO-A8] *- 00-07 + parity.with RESET = VIH.S,= VIL. and IN = VIHOUTPUTFUNCTIONMATCH PE DESCRIPTIONL L Parity ErrorL H Not EqualH L Undefined ErrorH H EqualWhere S = VIL. W = VIH. RESET = VIHPRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments~~~~~:~~i~a{~:1~1e ~!~t~~ti~f :llo~:~:~:t:r~~s not, TEXAS -I.!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265Copyright © 1983. Texas Instruments Incorporated2-619

TMS2150CACHE ADDRESS COMPARATORfunctional block diagram (positive logic)RESET --------~ ~----~~------------------------------------~AOAlA2A3A4A5A6A7A8(22)RRAM 512X9(23) (14)(5) MATCH(4)(3)A--.!!....(2) 511(19) (11)PE(20)(21)COMP00010203040506r-07enCCD~.C')CDen(7)(8)(9)(6)(17)(18)(15)(16)S (13)w(10)This diagram has been changed to correct errors in previous versions. No function a) change has been made in the chip.2-620 TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TMS2150CACHE ADDRESS COMPARATORPIN FUNCTIONAL DESCRIPTIONNAMEPINNO.DESCRIPTIONRESET 1 RESET input. Asynchronously clears entire RAM array and forces MATCH high when RESET is atAO 22A1 23A2 5A3 4A4 3A5 '2A6 19A7 20AS 21DO 7D1SD2 9VIL and Vi is at VIH.Add,ress inputs. Address 1 of 51 2-by-9-bit random-access memory locations. Must be stable forthe duration of the write cycle.D3 6 Data inputs. Compared with memory location addressed by AO-AS when Vi is at VIH and 5 is atD4 17 VIL' Provide input data to RAM when Vi is at VIL and S is at VIL.D51SD6 15D7 16W 10 Write control input. Writes DO through D7 and generated parity into RAM and forces MATCH highwhen IN is at VIL and S is at VIL. Places selected device in compare mode if IN is at VIH.PE 11 Parity error input/output. During write cycles, PE can force a parity error into the 9-bit location specifiedGND 12 Groundby AO through AS when PE is at VIL. For compare cycles, PE at VOL indicates a parity error in thestored data. PE is an ~pen-drain output so an external pull-up resistor is required.S 13 Chip select input. Enables device when S is at VIL. Deselects device and forces MATCH high when5 is at VIH.MATCH 14 When MATCH output is at VOH during a compare cycle, DO through D7 plus parity equal the contentsVCC 24 5-V supply voltageof the 9-bit memory location addressed by AO through AS.tJ)Q)(.)0>Q)cen..Jabsolute maximum ratings over operating free-air temperature range (unless otherwise specified)Supply voltage range, VCC (see Note 1) ................................... - 1 .5 to 7 VInput voltage range, any input .......................................... , - 1 .5 to 7 VContinuous power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 WOperating free-air temperature range .................................. : . .. 0 °C to 70°CStorage temperature range ......................................... - 65°C to 150°CNOTE 1: All voltage values are with respect to GND.recommended operating conditionsPARAMETER MIN NOM MAX UNITSupply voltage, VCC 4.5 5 5.5 VHigh-level input voltage, VIH 2 6 VLow-level input voltage,. VIL (See Note 2) -1 O.S VOperating free-air temperature, T A 0 70 DCNOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet forlogic voltage levels only.TEXAS.INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-621

TMS2150CACHE ADDRESS COMPARATORelectrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)TMS2150-4PARAMETER TEST CONDITIONS TMS2150-3 TMS2150-5 UNITMIN TYP MAX MIN TYP MAX10H = -2 mA, VCC = 4.5 V 2.4 2.4VOH(M) MATCH high-level output voltage V10H = -20 p.A, Vee = 4.5 V 3.5 3.5VOL(M) MATeH low-level output voltage 10L = 4 mA, Vee = 4.5 V 0.4 0.4 VVOL(PE) PE low-level output voltage 10L = 12 mA, Vce = 4.5 V 0.4 0.4 VII Input current VI = 0 V to 5.5 V 10 10 p.A10L(PE) PE output sink current VOL = 0.4 V, Vee = 4.5 V 12 12 mAlOS Short-circuit MATCH output current Vo = GND, VCC = 5.5 V -150 -150 mAleC1 Supply current (operative) RESET = VIH 145 135 mAICC2 Suply current (reset) RESET = VIL 155 145 mACi Input capacitance VI = 0 V, f = 1 MHz 5 5 pFCo Output capacitance Vo = 0 V, f = 1 MHz 6 6 pFrOOoCD

TMS2150CACHE ADDRESS COMPARATORswitching characteristics over recommended ranges of supply voltage and operating free-air temperaturePARAMETERTMS21S0-3 TMS21S0-4 TMS21S0-SMIN MAX MIN MAX MIN MAXUNITtalA) Access time from address to MATCH 35 45 55 nstalA-PI Access time from address to PE 45 55 65 nstatS) Access time from 5 to MATCH 20 25 35 nstp(D) Propagation time. data inputs to MATCH 20 35 45 nstp(R-MH) Propagation time. RESET low to MATCH high 30 30 40 nstp(S-MH) Propagation time. S high to MATCH high 20 25 35 nstp(W-MH) Propagation time. W low to MATCH high 20 25 35 nstp(W-PH) Propagation time. W low to PE high 20 25 35 nstv(A) MA TCH valid time after change of address 5 5 5 nstv(A-P) PE valid time after change of address 15 15 15 nstiming requirements over recommended ranges of supply voltage and operating free-air temperaturePARAMETERTMS2150-3 TMS21S0-4 TMS21S0-SMIN MAX MIN MAX MIN MAXtc(W) Write cycle time. without writing PE 30 40 50tcPE(W) Write cycle time. writing PE (see Note 3) 3S 40 50tc(rd) Read cycle time 35 45 55twiRL) Pulse duration. RESET low 35 35 45tw(WL) Pulse duration. W low. without writing PE 20 25 30twPE(Wl) Pulse duration. W low. writing PE (see Note 3) 35 40 45tsu(A) Address setup time before W low 0 0 0tsu(D) Data setup time before W high 20 25 30tsu(P) PE setup time before W high (see Note 3) 20 25 30tsu(S) Chip ~elect setup time before W high 20 25 30tsu(RH) RESET inactive setup time before first tag cycle 0 0 0th(A) Address hold time after W high 0 0 5th(D) Data hold time after W high 5 5 10th(P) PE hold time after W high 0 0 5thiS) Chip select hold time after W high 0 0 0tAVWH Address valid to write enable high 30 40 50UNITnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsC/)Q)Co)'>Q)cen...JNOTE 3: Parameters twPE(WL) and tsu(P) apply only during the write cycle time when writing a parity error. tcPE(W)'ac test conditionsInput pulse levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. GND to 3 VInput rise and fall times ..... . . . . . . . . . . . . . . . . . . . . . . . . . . 5 nsInput timing reference levels .............. _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.5 VOutput timing reference level ........................... _ . . . . . . . . . . . . . . . . . . . .. 1.5 VOutput loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. See Figures 1 and 2. TEXAS "I}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-623

TMS2150CACHE ADDRESS COMPARATORPARAMETER MEASUREMENT INFORMATIONFROM OUTPUTUNDER TEST~10nvccTESTPOINT820 n-= 1'15 pFFIGURE 1. PE OUTPUT LOAD CIRCUITTESTPOINTVccFROM OUTPUTUNDERTEST----~~-----.30n1'960 n510nFIGURE 2. MATCH OUTPUT LOAD CIRCUITIcompare cycle timing (see Note 4)AO·A800·07MATCH~14 tc(rd)II~ talA)I I~ADDRESS VALID.1IDATA VALID II: 14 tp(D) .1III1I ~1 II I II /4-ta(S)------+IIII'

TMS2150CACHE ADDRESS COMPARATORwrite cycle timing (se'e Note 4)AO·ASPARAMETER MEASUREMENT INFORMATION144---------- tc(W)/tcPE(W) _________ ~~1(see Note 3)00·07W- tw(WL)/twPE(WL)~ I.. (see Note 3)1PE (INPUT)MATCHPE (OUTPUT)---\..Jo.---:----JJ:tp(W·MH) 14 ~I~ tsu(P) ------+I 14-- th(P)~I (see Note 3)\ /tJ)Q)(.)'S;Q)cen...Jreset cycle timing (see Note 4)ADDRESS\ I:14---tw(RL)-./ J+---tsu(RH)----+I~rl-F-I-R-ST-T-A-G-C-Y-C-L-EMATCH----~:--...IJ:14~---tt~-tp(R.MH)\'-------NOTES: 3. Parameters twPE(Wl) 'and tsu(P) apply only during the write cycle time when writing a parity error, tcPE(W)'4. Input pulse levels are 0 V and 3 V, with rise and fall times of 5 ns. The timing reference levels on the input pulses are 0.8 Vand 2.0 V. The timing reference level for output pulses is 1.5 V. See Figures 1 and 2 for output loading.TEXAS l!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-625

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TMS4500ADYNAMIC-RAM CONTROLLERD2674, JANUARY 1982-REVISED AUGUST 1985• Controls Operation of 8K, 16K, 32K, and64K Dynamic RAMsTMS4500A ... NL PACKAGE(TOP VIEW)• Creates Static RAM Appearance• One Package Contains Address Multiplexer,Refresh Control, and Timing Control• Directly Addresses and Drives Up to 256KBytes of Memory Without External Drivers• Operates from Microprocessor Clock- No Crystals, Delay Lines, or RCNetworks- Eliminates Arbitration Delays• Refresh May Be Internally or ExternallyInitiated• Versatile- Strap-Selected Refresh Rate- Synchronous, Predictable Refresh- Selection of Distributed, Transparent, andCycle-Steal Refresh Modes- Interfaces Easily to PopularMicroprocessors• Strap-Selected Wait-State Generation forMicroprocessor/Memory Speed Matching• Ability to Synchronize or InterleaveController with the Microprocessor System(including Multiple Controllers)o3-State Outputs Allow Multiport MemoryCqnfiguration• Performance Ranges of 150 ns. 200 ns, or250 nsdescriptionThe TMS4500A is a monolithic DRAM systemcontroller designed to provide address multiplexing.timing. control and refresh/accessarbitration functions to simplify the interface ofdynamic RAMs to microprocessor systems.RASORASlACRACWCASNCRAOClKROYRENlCsALERASORASlACRACWCASRAOCAOMAOMAlCAlRAlRA2CA2MA2GNOVCCREFREQTWSTFSOFSlRA7CA7MA7MA6CA6RA6RA5CA5MA5RA4CA4MA4RA3CA3MA3TMS4500A ... FN PACKAGE(TOP VIEW)IdLJ.J z>-~ u~tiio~--' IUl LJ.J 0 --' U U LJ.J S Ul Ul«ua::a::UZ>a::I-LLLL6 5 4 3 2 1 444342414039383710111213143635343332~NNNOOMMM~~««««zz«««««a:: a:: U::2!CJ CJ::2! ua::::2!UThe controller contains a 16-bit multiplexer that generates the address lines for the memory device fromthe 16 system address bits and provides the strobe signals required by the memory to decode the address.An 8-bit refresh counter generates the 256-row addresses required for refresh.A refresh timer is provided that generates the necessary timing to refresh the dynamic memories and assuredata retention.The TMS4500A also contains refresh/access arbitration circuitry to resolve conflicts between memoryaccess requests and memory refresh cycles. The TMS4500A is offered in a 40-pin. 600-mil dual-in-lineplastic package and 44-pin. 650-mil square plastic chip carrier package. It is characterized for operationfrom 0 DC to 70 DC.RA7CA7MA7MA6CA6NCRA6IIItJ)Q)(.)"S;Q)cen..JPRODUCTION DATA documents contain informationcurrent as of publication date. Products conform tospecifications per the terms of Texas Instruments~~~~~:~~i~a{~:1~1~ ~!~~~~ti~r fl~o::~:~~t::s~s notTEXAS -Ij}INSTRUMENTSPOST OFFICE BOX 225012 • DAlLAS. TeXAS 15265Copyright © 1983, Texas Instruments Incorporated2-627

TMS4500ADYNAMIC·RAM CONTROLLERBLOCK DIAGRAMRAO-RA7 L-.-r----iMUlTIPLEXER8CAO-CA7 L-..."L---1'Q ~---,,c--' MAO-MA7ALE ______ •IIr-ACWen0CD~.(')CDenCSRENlACRREFREQTWSTFSOFS1J--4- RASO'Q~-""'- RASlTIMINGANDCONTROL'Q~-""'-CAS~-""'-RDYClKpin descriptionsRAO-RA7 InputCAO-CA7 InputMAO-MA7 OutputALEInputInputRow Address - These address inputs are used to generate the rowaddress for the multiplexer.Column Address - These address inputs are used to generate the columnaddress for the multiplexer.Memory Address - These three-state outputs are designed to drive theaddresses of the dynamic RAM array.Address Latch Enable - This input is used to latch the 16 address inputs,CS and REN 1. This also initiates an access cycle if chip select is valid.The rising edge (low level to high level) of ALE returns RAS to the highlevel.Chip Select - A Iowan this input enables an access cycle. The trailingedge of ALE latches the chip select input.2-628TEXAS l.!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TMS4500ADYNAMIC·RAM CONTROLLERpin descriptions (continued)REN1ACR, ACWClKRASO, RAS1RDYTWSTFSO, FS1InputInputInputInput/OutputOutputOutputOutputInputInputRAS Enable 1 - This input is used to select one of two banks of RAMvia the RASO and RAS 1 outputs when chip sel~ct is present. When itis low, RASO is selected; when it is high, RAS1 is selected.Access Control, Read; Access Control, Write - A low on either of theseinputs causes the column address to appear on MAO-MA 7 and thecolumn address strobe. The rising edge of ACR or ACW terminates thecycle by ending RAS and CAS strobes. When ACR and ACWare bothlow, MAO-MA7, RASO, RAS1, and CAS go into a high-impedance(floating) state.System Clock - This input provides the master timing to generate refreshcycle timings and refresh rate. Refresh rate is determined by the TWST,FS 1, FSO inputs.Refresh Request - (This input should be driven by an open-collectoroutput.) On input, a low-going edge initiates a refresh cycle and will causethe internal refresh timer to be reset on the next falling edge of the ClK.As an output, a low-going edge signals an internal refresh request andthat the refresh timer will be reset on the next low-going edge of ClK.REFREO will remain low until the refresh cycle in progress and the currentrefresh address is present on MAO-MA7. (Note: REFREO contains aninternal pull-up resistor with a nominal resistance of 10 kilohms.)Row Address Strobe - These three-state outputs are used to latch therow address into the bank of DRAMs selected by REN 1. On refresh bothsignals are driven.Column Address Strobe - This three-state output is used to latch thecolumn address into the DRAM array.Ready - This totem-pole output synchronizes memories that are tooslow to guarantee microprocessor access time requirements. This outputis also used to inhibit access cycles during refresh when in cycle-stealmode.Timing/Wait Strap - A high on this input indicates a wait state shouldbe added to each memory cycle. In addition it is used in conjunction withFSO and FS1 to determine refresh rate 'and timing.Frequency Select 0; Frequency Select 1 - These are strap inputs toselect Mode and Frequency of operation as shown in Table 1.TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-629

TMS4500ADYNAMIC·RAM CONTROLLERSTRAP INPUT MODESTABLE 1. STRAP CONFIGURATIONWAITSTATESCLOCKFOR MINIMUM FOR EACHMEMORY REFRESH ClK FREn. REFRESH FOR EACHTWST FSl FSO ACCESS RATE (MHz) FREn. (kHz) REFRESHl l l t 0 EXTERNAL - REFREQ 4l l H 0 ClK+31 1,984 64-95 t 3l H l 0 ClK+46 2,944 64-85 t 3l H H 0 ClK+61 3,904 64-82§ 4H l l 1 ClK+46 2,944 64-85 t 3H l H 1 ClK+61 3,904 64-80 t 4H H l 1 ClK + 76 4,864 64-77t 4H H H 1 ClK+91 5,824 64-88~ 4t This strap configuration resets the Refresh Timer circuitry.t The highest frequency in the refresh frequency column is the frequency that is produced if the minimum ClK frequency of the next selectstate is used.§ The highest frequency in the refresh column is the refresh frequency if the ClK frequency is 5 MHz.The highest frequency in the refresh column is the refresh frequency if the ClK frequency is 8 MHz.II 'functional descriptionr- TMS4500A consists of six basic blocks; address and select latches, refresh rate generator, refresh counter,rJ) the multiplexer, the arbiter, and timing and control block.cCD

TMS4500ADYNAMIC·RAM CONTROLLERarbiterThe arbiter provides two operational cycles: access and refresh. The arbiter resolves conflicts betweencycle requests and cycles in execution, and schedules the inhibited cycle when used in cyc'le-steal mode.timhlg and control blockThe timing and control block executes the operational cycle at the request of.the arbiter. It provides theDRAM array with RAS and CAS signals. It provides the CPU with a RDY signal. It controls the multiplexerduring all cycles. It resets the refresh rate generator and decrements the refresh counter during refreshcycles.absolute maximum ratings over operating free-air temperature range (unless otherwise noted) tSupply voltage range, VCC (see Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -1.5 V to 7 VInput voltage range (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 1.5 V to 7 VContinuous power dissipation .............. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.2 WOperating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 °C to 70°CStorage temperature range ......................................... - 65°C to 150°Ct Stresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended operating.Conditions" section of this specification is not implied. Exposure to absolute maximum-rated COflditions for extended periods may affectdevice reliability.NOTE 1: Voltage values are with respect to the ground terminal.recommended operating conditionsPARAMETER MIN NOM MAX UNITSupply voltage, VCC 4.5 5 5.5 VHigh-level input voltage, VIH 2.4 6 VLow-level input voltage, VIL -1:1: 0.8 VHigh-level output current, 10H -1 mALow·level output current, 10L 4 mAShort-circuit output current, lOS § - 50 mAOperating free-air temperature, T A 0 70 °c:I: The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for logicvoltage levels only.§ Not more than one output should be shorted at a time.C/)Q)CJ'SQ)cen...Jelectrical characteristics over recommended operating free-air temperature range (unless otherwisenoted)PARAMETER TEST CONDITIONS MIN TYP' MAX UNITI MAO-MA 7, RDY 2.4VCC = 4.5 V, 10H = -1 mAVOH High·level output voltage I RASO, RAS1. CAS2.7 VI REFREQ VCC = 4.5 V, 10H = -100 /lA 2.4VOL Low-level output voltage VCC = 4.5 V, 10L = 4 mA 0.4 VIIH High-level input current except REFREQ VI = 5.5 V 10 /lAI REFREQ -1.25 mAIlL Low-level input currentVI = 0I All others-10 /lA10Z Off-state output current VCC = 5.5 V, Vo = 0 to 4.5 V ±50 /lAICC Operating supply current TA = OoC 100 140 mACi Input capacitance VI = 0, f = 1 MHz 5 pFCo Output capacitance Vo = 0, f = 1 MHz 6 pF, All typical values are at VCC = 5 V, TA = 25°C.TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-631

TMS4500ADYNAMIC-RAM CONTROLLERtiming requirements over recommended supply voltage range and operating free-air temperature (unlessotherwise noted)rOOCCD

TMS4500ADYNAMIC·RAM CONTROLLERswitching characteristics over recommended supply voltage range and operating free-air temperaturerange (see Figure 1)tAEl-REltRAV-MAVtAEH-MAVtAEl-RYltAEl-CEltAEH-REHPARAMETERTime delay, ALE low toRAS starting lowTime delay, row address valid tomemory address validTime delay, ALE high tovalid memory addressTime delay, ALE to ROY startinglow (TWST =1 or refresh in progress)Time delay, ALE low to CASstarting low (see Note 10)Time delay, ALE high to RASstarting highTESTTMS4500A-15 TMS4500A-20 TMS4500A-25CONDITIONS MIN MAX MIN MAX MIN MAX35 40 50Cl = 160 pF 45 50 6065 75 90Cl = 40 pF 40 40 4060 150 70 200 80 25030 30 40tACl-MAX Row address valid after ACX low 15 20 25Time delay, memory addresstMAV-CEl0 0 0valid to CAS starting lowCl = 160 pFTime delay, ACX low to CAStACl-CElstarting low (see Note 10)40 100 45 130 50 165tACH-REHtACH-CEHtACH-MAXtCH-RYHtRFl-RFltCH-RFLtCl-MAVtCH-RRltMAV-RRltCl-RFHtCH-RFHtCH-RRHTime delay, ACX to RASstarting highTime delay, ACX high to CASstarting highColumn address valid afterACX highTime delay, ClK high to ROY startinghigh (after ACX low) (see Note 11)Time delay, REFREQ external tillsupported by REFREQ internalTime delay, ClK high till REFREQinternal starting lowTime delay, ClK low till refreshaddress validTime delay, ClK high tillrefresh RAS starting lowTime delay, refresh addressvalid till refresh RAS lowCl = 40 pFTime delay, ClK low to REFREQ Cl = 160 pFstarting high (3 cycle refresh)Time delay, ClK high to REFREQstarting high (4 cycle refresh)Time delay, ClK high to refreshRAS starting high30 40 505 30 10 40 15 5010 15 1540 45 6030 35 3530 35 4575 100 12510 50 15 60 20 805 5 550 55 7550 55 755 35 10 45 10 60tCH-MAX Refresh address valid after ClK high 15 20 25-- -- -- --NOTES: 10. The falling edge of CAS occurs when both ALE low to CAS low time delay (tAEl-CEl) and ACX low to CAS low time delay(tACl-CEl) have elapsed, i.e., if ACX goes low prior to (tAEl-CEl - tACl-CEl) after the falling edge of ALE, the fallingedge of CAS is measured from the falling edge of ALE (tAEL-CEl)' Otherwise, the access time increases and the fallingedge of CAS is measured from the falling edge of ACX (tACl-CEl).11. ROY returns high on the rising edge of ClK. If TWST = 0, then on an access grant cycle ROY goes high on the same edgethat causes access RAS low. If TWST = 1, then ROY goes to the high level on the first rising ClK edge after ACX goes lowon access cycles and on the next rising edge after the edge that causes access RAS Iowan access grant cycles (assumingACX low).TEXAS lj}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265UNITns2-633U)Q)(.)'S;Q)CCJ)..J

TMS4500ADYNAMIC·RAM CONTROLLERIrC/)CCD

TMS4500ADYNAMIC·RAM CONTROLLERaccess cycle timingClKALEROW ...... .-...----.I-..,.-....,........,..REN1COL CS L....l'-...:!/:....:>!.....:L....JI....::.IRASMAO-MAlCASROYrefresh request timingClK~ \ /\'----1___ tROl-ClHREFREO(EXTERNAL) ~~•rJ)Q)(.)oS;cQ)en...JREFREO(INTERNAL)tW(RO~)14- tRFl-RFlTEXAS -II}INSTRUMENTSPOST OFFICE BOX 22501~ • tJALLAS, TEXAS 152692·635

TMS4500ADYNAMIC·RAM CONTROLLEREIrOOCCD

TMS4500ADYNAMIC·RAM CONTROLLER. refresh cycle timing (three-cycle)ClK \J:---..JIT\J;.----JI: \\...---J!I I I\~----I! : /,.--"""""'!' .... \ :ALE I . I~---------------------------~-------------------------ACX --__ ~ ________ ~------~--~~~: \ ~f\: tCl-RFH~l ¥~tCl-MA'vMAO-MA7 ~ REFRESH ADDRESSX~tCH-MAX: KtCH-RRl f.-+tCH-RRHRAS l 1\~ ________________ ~~!.-tMAV-RRl.jrefresh cycle timing (four-cycle)ClKROW ADDRESStCH-RElHII~tCl-MAXtCAV-CEl~X'""-------! \! !l tCl-CEl f 14 ~ALE~-------~r--\~~--------------~--------------~-------~--ACX\t if\tCH-RFH~REFREO ----~--~--~------------------~tfMAO-MA7tCl-MAV--------I------~I I ~~tCH-RRl1414-------~11- tMAV -R R lREFRESH ADDRESSIItCH-MAX~______________________ ~II tCl-CEl f ~I!+--tCH-CEL t ~"\..tJ)Q)(.)'S;Q)cen...Jt On access grant cycle following refresh, CAS low and address multiplexing are timed from ClK high transition (tCH-CEll if ACX lowoccurs prior to or coincident with the falling edge of ALE.t On access grant cycle following refresh, CAS low and address multiplexing are timed from ClK low transition (tCl-CEll if ACX low occurs20 ns or more after the falling edge of ALE.TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-637

TMS4500ADYNAMIC·RAM CONTROLLERtypical access/refresh/access cycle(three-cycle, TWST is low)NMIIr-rnC/)C/)wUU

TMS4500ADYNAMIC-RAM CONTROLLERtypical access/refresh/access cycle(four-cycle, TWST is low)I-2:«a:t:l(J'J(J'JwUU«J:(J'JWa:u.wa:'

TMS4500ADYNAMIC·RAM CONTROLLERtypical access/refresh/access cycle(three-cycle, TWST is high)Nz~:3o u___________ _MrencCD5:.(')CDenI-ZctII:CJCIlCIlwUUctiCIlwe:wII:NM3:N3:3:------ ---- -I----t--- - -- --MCIlCIlwUUctNW...JctI~>Ca:2-640TEXAS -I/}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

TMS4500ADYNAMIC-RAM CONTROLLERtypical access/refresh/access cycle(four-cycle, TWST is high)

EI2-642

General InformationNumerical IndexGlossaryExplanation of Function TablesParameter Measurement InformationFunctional IndexLSI DevicesApplication ReportsI)Advanced Schottky FamilyError Detection and CorrectionMemory MappingBit-Slice Processor 8-Bit FamilyExcerpt - SN74AS888, SN74AS890Bit-Slice Processor User's GuideMechanical. Data3-1

3-2

Advanced Schottky Family. TEXASINSTRUMENTS3-3CJ)~~oc.Q)a::s:::::o"';:::;ca"~Q.c.td:

IMPORTANT NOTICETexas Instruments reserves the right to make changes at any time inorder to improve design and to supply the best product possible.Texas Instruments assumes no responsibility for infringement of patentsor rights of others based on Texas Instruments applications assistanceor product specifications, since TI does not possess full access to dataconcerning the use or applications of customer's products. TI alsoassumes no responsibility for customer product designs.Copyright © 1984, Texas Instruments Incorporated3-4

Advanced Schottky Family (ALSI AS) ApplicationContentsTitleINTRODUCTION TO ADVANCED SCHOTTKY FAMILy ........................................ . 3-9Speed-Power Slots Filled By Advanced Schottky TTL ............................................. . 3-9Additional Advantages Offered by , ALS and 'AS Devices ......................................... . 3-9Concepts of Defining , ALS and 'AS ........................................................... . 3-10Compatibility With Other TTL .............................................................. . 3-10Fanout .................................................................................. . 3-10Using the Schottky Barrier-Diode ................................................................ . 3-10Analysis of Schottky-Clamped Transistor ..................................................... . 3-10Analysis of ' ALS and' AS NAND Gates ..................................................... . 3-13Circuit Parameters ...................................'....................................... . 3-16Transfer Characteristics .................................................................... . 3-16Input Characteristics ...................................................................... . 3-17Low-Level Input Current ................................................................ . 3-17Input Clamping Diode Test ......................................... : .................... . 3-18High-Level Input Current ................................................................ . 3-18Input Breakdown Test .............. , .................................................... . 3-18Output Characteristics ..................................................................... . 3-18High-Level Output Characteristics ......................................................... . 3-18Low-Level Output Characteristics ......................................................... . 3-19Switching Speed .......................................................................... . 3-19DC Noise Margins ........................................................................ . 3-20Specified Logic Levels and Thresholds ..................................................... . 3-22Noise Rejection .......................................................................... . 3-22GUIDELINES FOR SERIES 'ALS/,AS TTL SYSTEM DESIGN ......... : .......................... .Power Supply, Regulation ..................................................................... .Supply Voltage Ripple ....................................................................... .Noise Considerations ................ ;....................................................... .Noise Types and Control Methods ........................................................... .Shielding ................................................................................ .Grounding and Decoupling ................................................................. .Cross Talk .... : ......................................................................... .Back-Panel Interconnections .............................................................. .Printed Circuit Card Conductors .......................................................... .Transmission-Line Driving Reflections ....................................................... .APPENDIXESA Normalized Load Factors ......................................................... .B Letter Symbols,' Terms, and Definitions ............................................. .Page3-243-253-273-28IIU)...3-28 ....,3-29 03-29 Co(1)3-34ex:3-343-36 C03-37 .';:CO.2Q.3-453-46 Co

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List of IllustrationsFigureTitleSpeed-Power Relationships of Digital Integrated Circuits ...................................... .Series 54174 TTL Family Compatible Levels Showing DC Noise Margins ....................... .Fanout Capability ...................................................................... .Baker Clamp .......................................................................... .Schottky Clamped-Transistor ............................................................. .Schottky Barrier-Diode .................................................................. .Schottky Barrier-Diode Energy Diagrams ................................................... .Metal-N Diode Current-Voltage Characteristics ........................................ , ..... .Difference Between P-N and Schottky Barrier-Diodes ........................................ .Standard Process (,LSI'S) ............................................................... .Advanced Process (' ALSI' AS) ............................................................ ., ALSOOA NAND Gate Schematic ......................................................... ., ASOO NAND Gate Schematic ............................................................ .Input Voltage vs Output Voltage' ALS/' AS ................................................. .Input Current vs Input Voltage for TTL Families ............................................ .Low-Level Input Current vs High-Level Input Voltage ........................................ .DC Equivalent Input Circuit for Series ' ALS Gates .......................................... .Equivalent Output Circuit for ' ALSI' AS Gates .............................................. .High-Level Output Voltage vs High-Level Output Current. .................................... .Low-Level Output Circuit for' ALSI' AS Gates .............................................. .Low-Level Output Voltage vs Low-Level Output Current ..................................... .High- to Low-Level Propagation Delay vs Load Capacitance .................................. .Low- to High-Level Propagation Delay vs Load Capacitance .................................. .Power Dissipation per Gate vs Frequency .................................................. .Stray Coupling Capacitance .............................................................. .Evaluations of Gate Response to Fast Input Pulses ........................................... .Theoretical Required Pulse Width vs Pulse Amplitude for ' ALS and 'AS Inputs .................. .Parameter Measurement Information ....................................................... .Effect of Source Impedance on Input Noise ................................................. .Spurious Output Produced by Supply Voltage Ripple ......................................... .Effect of Ground Noise on Noise Margin .................................................. .Typical Logic Circuit with Noisy Input .................................................... .Diagram Representing a Gate Driving a Transmission Line .................................... .Noise Generation Caused by Poor Transmission-Line Return .................................. .Ideal Transmission-Line Current Handling .................................................. .Circuit with Effective Capacitive Loading .................................................. .Supply Current Transient Comparisons ..................................................... .Transmission-Line Power Buses .......................................................... .Capacitive Storage Supply Voltage System .................................................. .Commonly Used Power Distribution and Decoupling System .................................. .Equivalent Circuit for Sending Line ....................................................... .Equivalent Circuit for Cross Talk ......................................................... .Capacitive Cross Talk Between Two Signal Lines ............................................ .Coupling Impedances Involved in Cross Talk ............................................... .Equivalent Cross-Talk Network ........................................................... .Microstrip Line ........................................................................ .Strip Line .............................................................................. .Line Spacing Versus Cross-Talk Constant .................................................. .TTL Bergeron Diagram ................................................................. ., ALS/' AS Driving Twisted Pair .......................................................... .12345678910111213141516171819202122232425262728293031323334-35363738394041424344454647484950Page3-103-113-113-113-113-123-123-123-133-133-133-143-153-163-173-183-183-193-193-203-203-213-213-223-233-233-243-253-283-283-283-283-293-293-303-303-313-333-33 U)...,-3-333-34 03-34a.(1)3-35 CC3-35C3-35 03-36 .';:;3-36 ca3-37 .23-37 C.3-37 a.«3-7

List of Illustrations (Continued)Figure Title Page51 'AS - ve Transition Bergeron Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3852 'AS - ve Voltage/Time Plot ......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3853 'AS + ve Transition Bergeron Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3954 'AS + ve Voltage/Time Plot ................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3955 'ALS - ve Transition Bergeron Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 3-4056 'ALS - ve Voltage/Time Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4057 'ALS + ve Transition Bergeron Diagram ................. .'. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4158 'ALS + ve Voltage/Time Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4159 Oscilloscope Photograph of 'ASOO - ve Transition Using 50-Ohm Line . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4260 Oscilloscope Photograph of 'ASOO + ve Transition Using 50-Ohm Line ..................... . . . . . 3-4261 Oscilloscope Photograph of 'ASOO -ve Transition Using 25-0hm Line .................. .'....... 3-4262 Oscilloscope Photograph of 'Asob + ve Transition Using 25-0hm Line ............. . . . . . . . . . . . . . 3-4263 Oscilloscope Photograph of 'ALSOOA - ve Transition Using 50-Ohm Line. . . . . . . . . . . . . . . . . . . . . . . . 3-4264 Oscilloscope Photograph of 'ALSOOA + ve Transition Using 50-Ohm Line. . . . . . . . . . . . . . . . . . . . . . . . 3-4265 Oscilloscope Photograph of 'ALSOOA - ve Transition Using 25-0hm Line. . . . . . . . . . . . . . . . . . . . . . . . 3-4366 Oscilloscope Photograph of 'ALSOOA + ve Transition Using 25-0hm Line. . . . . . . . . . . . . . . . . . . . . . . . 3-43List of TablesTable Title PageTypical Performance Characteristics by TTL Series . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102 Worst-Case Output Parameters ............................................................ 3-223 Guidelines for Systems Design for Advanced Schottky TTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-264 Guidelines for Printed Circuit Board Layout Advanced Schottky TTL. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-265 Guidelines for General Usage of Advanced Schottky TTL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-276 Guidelines for Gates and Flip-Flops Using Advanced Schottky TTL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-277 Typical Impedance of Microstrip Lines ..................................................... 3-368 Typical Impedance of Strip Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36A-I Normalized Input Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45A-2 Fanout Capability .... :................................... ,.............................. 3-463-8

INTRODUCTIONThe purpose of this Application Report is to assist thedesigners of high-performance digital logic systems in theuse of the new series of Advanced Schottky-clamped* TTLintegrated circuits.Detailed electrical characteristics of these devices areprovided and, if available, rabies have been included thatcompare specific parameters of the devices with those ofother logic families. In addition, interfamily information isprovided to allow system designers to mix logic families inthe same circuit. This allows the designer to use the relativemerits of each logic family in high preformance state-of-theartdesigns.The major subject areas covered in this ApplicationReport are as follows:• Advanced Schottky process• Fanouts• Transfer characteristics• Input and output parameterso Speed and power information• Noise margins• Power supply considerations• Noise sources and their abatemento Back panel and printed circuit wiringguidelines• Line driving and receivingINTRODUCTION TOADVANCED SCHOTTKY -CLAMPED TTLSeries 54174 transistor-transistor logic (TTL) has, sinceits introduction in 1965, become the most popular digitalintegrated circuit logic family ever offered. Its popularityhas allowed the development of high-volume productiontechniques which have made it the most economical approachto the implementation of major portions of medium-to-highperformance digital logic systems. These systems range fromsimple decision making to highly complex real-time computerinstallations that handle worldwide data processing.The proliferation of and economical impact of thesedigital logic systems has created a demand for constantimprovement in efficiency. In response to demand, TexasInstruments examined the advantages gained by Schottkyclamping. An increase in speed and performance wasdiscovered in the use of Schottky barrier-diode clamping.The process was patented in the United States and theSchottky series 54S174S catalog parts were made availablein the early 1970s. A series 54LS174LS was introduced later.The series 54LS174LS was slower that the 54S174S seriesbut had a much lower power consumption.*Integrated Schottky-Barrier-diode-clamped transistor is patented by TexasInstruments Incorporated, U.S. Patent Number 3,463,975.Recent innovations in integrated circuit design havemade it possible to develop two new families: the AdvancedSchottky (54ASI74AS) series and the Advanced Low-PowerSchottky (54ALSI74ALS) series. The' ALS and' AS seriesprovide considerable higher speeds than the 'LS and'S series,respectively. The' ALS series offers a substantial reductionin power consumption over the 'LS series, and the' AS series~ffers a substantial reduction in power consumption over the's series. The' ALS/' AS series is pin-to-pin compatible withthe 'LSI'S series.SPEED-POWER SLOTS FILLED BY I ALSAND lAS TTLDigital integrated circuits have historically been characterizedfor both speed and power. The series 54S174S devices contain19 mW NAND gates and 125-MHz flip-flops and the series54LS174LS devices contain 2-mW NAND gates and 45-MHzflip-flops. Either of these logic families could be used todesign a 2-MHz system, therefore categorization strictly onthe basis of power and speed is inconclusive with respectto system efficiency. To provide a means of measuring theoverall circuit efficiency and performance, a speed-powerproduct efficiency index for integrated circuits wasdeveloped. The rating of an integrated circuit is obtained bymultiplying the gate propagation delay by the gate powerdissipation.Table 1 provides propagation delay times, powerdissipation, and speed-power product for the TexasInstruments TTL series. In addition, it provides flip-flopfrequency for each family as an indicator of systemperformance. The speed-power product rating system(measured in picojoules) is divided into circuits where speedis the prime factor and circuits where low-power is the pri~efactor. The ' ALS series speed-power product ISapproximately 4 times less than that of the 'LS series andthe' AS series speed-power product is approximately 4 timesless than the'S series. Figure 1 is a graphic analysis of thespeed-power points for the various TTL families.ADDITIONAL ADVANTAGES OFFERED BY'ALS AND 'AS DEVICESThe' ALS and' AS devices offer the following additionaladvantages:1. TTL compatible with 54174, 54S174S, 54L174L,54LS174LS, and 54H174H series gates forselectively upgrading existing systems2. Suppresses the effects of line ringing andsignificantly reduces undershoot3. Higher thresholds (noise immunity) and betterstability across operating free-air temperaturerange4: Input current requirement reduced by up to 50 %3-9tJ)+"":a..oC.0)ex:r::o"';:CO"~C.c.«

Table 1. Typical Performance Characteristics by TTL SeriesMINIMIZING POWERMINIMIZING DELAY TIMEPROP PWR SPD/PWR MAXIMUM PROP PWR SPD/PWR MAXIMUMCIRCUIT TECHNOLOGY FAMILY DELAY DISS PRODUCT FLlp·FLOP FREQ FAMILY DELAY DISS PRODUCT FLlp·FLOP FREQGold DopedSchottky Clamped(ns) (mW) (pJITTL 10 10 100L TTL 33 1 33LS TTL 9 2 18'ALS 4 1.2 4.8(MHz) (ns) (mW) (pJ) (MHz)35 TTL 10 10 100 353 H TTL 6 22 132 50.45 S TTL 3 19 57 12570 'AS 1.7 8 13.6 200l>"C~.oQ),...o·::l:JJCD"Co...,...enVIC~~u';;,0...J.EVIEi=~'OJCc0.~~0~.,enco.,~30 .54L2010 -.54n4LS• 54n4•5- 54n4H.54n4ALS3- • 54n4S2• 54n4AS11 2 3 5 10 20 30Typical Power Dissipation-mWFigure 1. Speed-Power Relationships ofDigital Integrated Circuits5. Fanout is doubled6. Terminated lines or controlled impedance circuitboards are normally not required.7. The' AS series offers shorter propagation delaysand higher clock frequencies with relatively lowpower consumption.8. The maximum flip-flop frequency has beenincreased to 200 MHz.CONCEPTS OF DEFINING SERIES 'AS AND'ALSBoth the' ALS and' AS series are electrically and pinoutcompatible with existing TTL series. The' ALS series issuitable for replacing all TTL families except in the veryhighest frequency applications. Replacement with' ALS willresult in lower power consumption, smaller power supplycurrent spikes, and, in some cases, better noise immunitythan the other families. In those cases where a very highoperating frequency is required, the' AS series can be used.The 'AS devices require less than one-half of the supplycurrent of the'S series and has approximately twice theclocking frequency. The ' ALS devices are ideal forimproving effeciency at the lower speeds. The' AS devicesare ideal for replacement of high-speed logic familiesincluding ECL 10K series.Compatibility With Other TTL FamiliesTo ensure complete electrical compatibility in systemsusing or intending to use a mixture of existing TTL familiesand the new' ALS/' AS families, specific guidelines have beenimplemented. These guidelines ensure the continuation ofdesirable characteristics and incorporate newer techniquesto improve performance and/or simplify the use of TTLfamilies. Figure 2 illustrates the comparison of essentialparameters . of. each family and shows that completecompatibility is maintained throughout the 54174 families .FanoutThe compatible ratings for fanout simplify theimplementation of logic and provide a freedom of choice inthe use of any of the seven performance ranges to designa digital logic system. Any of the Texas Instruments TTLseries gates can be used to drive any other gate without theuse of an interface or level-shifting circuit. The use of totempole-(push-pull)type output stages provides a low outputimpedance and the capability for both sourcing and sinkingcurrent. The output is easily adapted for driving MaS andCMOS circuits as well as the interface circuits between theoutput and the devices it controls. Figure 3 illustrates fanoutcapability.USING THE SCHOTTKY BARRIER DIODEThe Advanced Schottky Family has been developed fromtwo earlier concepts: the Baker Clamp and the SchottkyBarrier-Diode (SBD). The use of the Baker Clamp and SBDconcepts resulted in the Schottky Clamped Transistor. TheSchottky clamped transistor produced the increased switchingspeed associated with the S series integrated circuits. Theadditional advances that have led to the development of' ALSand ' AS gates and the actual gates are discussed later.Analysis of the Schottky Clamped TransistorThe use of the Baker Clamp, shown in Figure 4, is amethod of avoiding saturation of a discrete transistor. Thediode forward voltage is 0.3 V to 0.4 V as compared to0.7 V for the base-emitter junction diode. When the transistoris turned on, base current drives the transistor toward3-10

2.52.0:;; 1.5t:I~..J 1.0o>0.5Fm HIGH LOGIC LEVELDC NOISE MARGINtm1 THRESHOLD REGION ts.;~~,J LOW LOGIC LEVELDC NDISE MARGINFigure 2. Series 54174 TTL Family Compatible Levels Showing DC Noise Margins100908070I- 60::J~ 50ctLI. 40302010074 54 74H 54H 74L 54S 74LSfZZ2J LOW·LEVEL LOADS~ HIGH·LEVEL LOADSFigure 3. Fanout Capability~eN·P·N SILICONTRANSISTORFigure 4 .. Baker Clampsaturation. The collector voltage drops, the germanium diodebegins to conduct forward current, and excess base drive isdiverted from the base-collector junction of the transistor.This causes the transistor to be held out of deep saturation,the excess base charge to not be stored, and the turn-off timeto be dramatically reduced.A germanium diode cannot be incorporated into amonolithic silicon integrated circuit. Therefore, thegermanium diode must be replaced with a silicon diode which~BDN-P-N SILICONTRANSISTORMONOLITHIC COMPOSITION.-

. I J I-MET ~eN SILICONCOMPOSITIONSYMBOLFigure 6. Schottky Barrier-DiodeCurrent in the SBD is carried by majority carriers.Current in the p-n junction is carried by minority carriers.The resultant minority carrier storage causes the switchingRECTIFYINGl>"C~.(')Q),....o·:::J::JlCD"Co,...."""II(f)The qualitative physics of an SBD is illustrated inFigure 7. The valence and conduction bands in a metaloverlap make available a large number of free-energy states.The free-energy states can be filled by any electrons whichare injected into the conduction band. A finite number ofelectrons exist in the conduction band of a semiconductor.The number of electrons depends mainly upon the thermalenergy and the level of impurity atoms in the material. Whena metal-semiconductor junction is formed, free electrons flowacross the junction from the semiconductor, via theconduction band, and fill the free-energy states in the metal.This flow of electrons builds a depletion potential across thebarrier. This depletion potential opposes the electron flowand, eventually, is sufficient to sustain a balance where thereis no net electron flow across the barrier.Under forward bias (metal positive), there are manyelectrons with enough thermal energy to cross the barrierpotential into the metal. This forward bias is called "hotinjection. " Because the barrier width is decreased as forwardbias Vp increases, forward current will increase rapidly withan increase in VF.When the SBD is reverse biased, electrons in thesemiconductor require greater energy to cross the barrier.However, electrons in the metal see a barrier potential fromthe side essentially independent of the bias voltage and a smallnet reverse current will flow. Since this current flow isrelatively independent of the applied reverse bias, the reversecurrent flow will not increase significantly until avalanchebreakdown occurs.A simple metal-n semiconductor collector contact is anohmic contact while the SBD contact is a rectifying contact.The difference is controlled by the level of doping in thesemiconductor material. As the doping is increased, thecontact becomes more ohmic. Figure 8 illustrates the currentvoltagecharacteristics according the doping applied.METALESEMICONDUCTOR(N)eee Ec--------*EfEv~~~ __ --t------L------VLIGHT N DOPING------~ __ ..... ~~----------VMEDIUM DOPING-------------#-~--------- VHEAVY DOPINGFigure 8. Metal-N Diode Current-VoltageCharacteristicsMETAL SEMICONDUCTOR METAL SEMICONDUCTORE(N)E(N).4.- ~1-:;::- V Bias+ f'--eeeEc'--------~EfEv, ee Ec' ... - -- - - - - ~ EfEvZERO BIASFORWARD BIASFigure 7. Schottky Barrier-Diode Energy DiagramsREVERSE BIAS3-12

time of a p-n junction to be limited when switched fromforward bias to reverse bias. A p-n junction is inherentlyslower than an SBO even when doped with gold.Another major difference between the SBO and p-njunction is the forward voltage drop. For diodes of the samesurface area, the SBO will have a larger forward current atthe same forward bias regardless of the type of metal used.The SBO forward voltage drop is lower at a given currentthan a p-n junction. Figure 9 illustrates the current carriersand forward current-voltage characteristics differencesbetween the SBO and p-n junction. The SBO meets therequirements of a silicon diode which will clamp a siliconn-p-n transistor out of saturation.4 edMETALNIII h4 e0 ..p Nd III bCURRENT CARRIERSEMITTERBASE ANDSCHOTTKYFigure 10. Standard Process ('LSI'S)COLLECTORBASE ANDEMITTER SCHOTTKY COLLECTOR1V---......FORWARD I-V CHARACTERISTICFigure 9. Differences Between P-N andSchottky Barrier-DiodesThe Advanced Schottky process differs from theSchottky process in that it uses ion implantation of impuritiesinstead of diffusion. Ion implantation gives greater controlon the depth of doping and resolution. Because of a thinnerepitaxial layer and smaller all around geometries, smallerparasitic capacitances are encountered. The performance ofthe SBO is also enhanced by the use of oxide isolation ofthe transistors. This reduces the collector~substratecapacitance. Figure 10 illustrates the 'LSI'S process whichconsists of conventional masks, junction isolation, and aFigure 11. Advanced Process (' ALSI' AS)standard metal system and Figure 11 illustrates the ' ALSI' ASprocess which consists of composed masks, ion implantation,oxide isolation, and a standard metal system.Analysis of ' ALS and 'AS NAND GatesThe' ALS and' AS NAND gates in Figures 12 and 13combine the desirable features of improved TTL circuits withthe technological advantages of full Schottky clamping, ionimplantation, and oxide isolation to achieve very fastswitching times at a reduced speed-power product. Theimprovements ~md advantages are as follows:1. Full Schottky clamping of all saturatingtransistors virtually eliminates storing excessivebase charge and significantly enhances turn-offtime of the transistors.2. Elimination of transistor storage time providesstable switching times across the temperaturerange.3. An active turn-off is added to square up thetransfer characteristic and provide an improvedhigh-level noise immunity.(f).....~oCoCl)a:s:::o.';::;CO.2C.Co

R314knR750nVee5knOUTPUT0304':"R52.8knR65.6kn05':"':"01B':"Figure 12. 'ALSOOA NAND Gate Schematic4. Input and output clamping is implemented withSchottky diodes to reduce negative-goingexcursions on the inputs and outputs. Becauseof its lower forward voltage drop and fastrecovery time. the Schottky input diode providesimproved clamping action over a conventionalp-n junction diode.5. The ion implantation process allows smallgeometries giving less parasitic capacitances sothat switching times are decreased.6. The reduction of the epi-substrate capacitanceusing oxide isolation also decreases switchingtimes.A key feature of the 'ALS and 'AS families is theimprovement in typical input-threshold voltage. Figure 12is a schematic diagram of the 'ALSOOA NAND gate.Figure 13 is a schematic diagram of the 'ASOO NAND gate.The inpurthreshold voltage of the devices is determined bythe equation:VT = VBE of Q2 + VBE of Q3+ VBE of Q5 - VBE of QIA(or VBE of QIB) (1)From Eq. (1) it can be determined that the inputthreshold voltage is two times VBE or approximately 1.4 V.Low-level input current IlL is reduced in the, ALSOOAI' ASOO gates because of the improved inputcircuits. Buffering by transistors QIA (or Q1B) and Q2causes a significant reduction in low-level input current. Lowlevelinput current is determined by the equation:I IlL = Vee - VBE of Q1A- VI/[R(hFE of Q1A + 1)] (2)By using Eq. (2) low-level input current is reduced byat least the factor of hFE of QIA + 1 and is typically- 10 p.A for the 'ALSOOA and - 50 p.A for the' ASOO. Highleveloutput voltage VOH is determined primarily by Vee,3-14

Rl10knR32knR850 knR726nVee05... ---+---t 06010R42knOUTPUT04R5R62knFigure 13. 'ASOO NAND Gate Schematicresistors R4 and R7, and transistors Q6 and Q7. With noload, the high-level output voltage is approximately equalto Vee - VBE of Q6 because the voltage across resistorR4 is 0 V. For medium-level currents, the high-level outputvoltage is equal to Vee - VBE of Q6 - VBE of Q7because of the Darlington gain of transistors Q6 and Q7. Thecurrent through resistor R3 is typically less than 1 p.A and,therefore, the voltage drop is negligible. As conductionthrough transistors Q6 and Q7 is increased, the voltage dropacross limiting resistor R7 will increase until the Schottkyclamping diode of transistor Q6 starts to become forwardbiased. At this point, the current through resistor R3 (andthe voltage drop) is no longer negligible and the high-leveloutput voltage is determined by:VOH = Vee - IOH through R7 x R7- VeE of Q6 - VBE of Q7 (3)Low-level output voltage VOL is determined by the turningon of transistor Q5. When the input is high and transistorQ2 is turned on, high-current transistor Q5 is turned on bya current path through transistor Q3 and resistor R3.Sufficient base drive is supplied to keep transistor Q5 fullyturned on at an apparent output resistance of 14 n for' ALSand 60 for' AS.The fanout is up to 40 for a '54ALS device that is drivinga '54ALS device and up to 80 for a '74ALS device, that isdriving a '74ALS device and provides a guaranteed low-leveloutput current of 4 rnA and 8 rnA, respectively.The increase in speed-power product of '54ALSI'74ALSdevices, a factor four times better than '54LS1'74LS devices,is due to the design consideration of the quiescent andswitching operations of the circuit. In the quiescent state,transistor Q2 allows the use of a reduced low-level inputcurrent. This reduces the fanout and reduces the overallquiescent current requirements.The design of diodes D2 and D3 (or transistor Q8) andtransistor Q4 enhances the speed-power product of thedevice. Transistor Q4 reduces the turn-off time andconsequently the current transients caused by conduction...tJ)+-'oc.Q)a:c:o"';:ca"~c..c.

overlap of transistor Q5. The same principle is used by diodes02 and 03 and transistor Q3 in turning off transistor Q7.In addition, the active turn-off design produces a squaretransfer characteristic.The 'ASOO gate has additional circuits not on the'ALSOOA gate. The circuits are added to enhance thethroughput of the 'AS Family.Transistor Q 10 has been added as a discharge path forthe base-collector capacitance of transistor Q5. Withouttransistor Q1O, rising voltages at the collector of transistorQ5 would force current, via the base-collector capacitance,into the base oftrimsistor Q5 causing it to turn on. However,diode 010 causes transistor Q10 to turn on (during risingvoltage) and keeps transistor Q5 turned off. Oiodes 06 and09 serve as a discharge path for capacitor-diode 010.CIRCUIT PARAMETERSWorst-case testing of 'ALSI' AS devices provides amargin of safety. [All dc limits shown on the data sheet areguaranteed over the entire temperature range (-55°C to125°C) for series 54ALSI54AS and 0 °C to 70°C for series74ALS174AS)]. In addition, the dc limits are guaranteed overthe entire supply voltage range (4.5 V to 5.5 V).Transfer CharacteristicsSince the most common application for a logic gate isto drive a similar logic gate, the input and output logic levelsmust be compatible. The input and output logic levels for'ALSI' AS devices are as follows:VIL - The voltage value required for a low-levelinput voltage that guarantees operationVIH - The voltage value required for a high-levelinput voltage that guarantees operationVOL - The guaranteed maximum low-level outputvoltage of a gateVOH - The guaranteed minimum high-level outputvoltage of a gate.With the exception of high-level ouput voltage (whichis a direct function of supply voltage), these values remainvirtually unchanged over the temperature range and undernormal operating conditions of the device.Analysis of the input and output response characteristicsof 'ALSI' AS TTL gates is necessary to understand theoperation of these devices in most system applications. Thedc response characteristics can best be depicted by an inputvoltage VI versus output voltage Va transfer plot.Figure 14 plots the 'ALSI' AS characteristics ascompared with members of other TTL logic families.As shown in Figure 14, the 'ALS and 'AS devicesexhibit a much better output savings when compared withstandard TTL devices. The better high-level output voltageis primarily because of the active turn off of the low-leveloutput transistor. The diode voltage drop in the normal outputis replaced by a low-current VBE voltage drop. This provides5' TRANSFER FUNCTIONVCC =5.0 VTA = 25°CLOAD =500n4»"C"ECi"D)r+0"::::s:cCD"Co...r+en>~ 3'0>:;So:::JoI 2o>0.2 0.4 0.6 0.81.0 1.2 1.4 1.6VI-Input Voltage-VFigure 14. Input Voltage vs Output Voltage of' ALSI' AS3-16

a better high-level noise immunity in 'ALS and and 'AS overstandard TTL devices.Input CharacteristicsTo use' ALS/' AS devices fully, a knowledge of the inputand output characteristics is required. This is particularly truewhen a device interfaces with a device not in the same TTLseries. In addition, knowledge of voltage and currentrelationships for all elements is important for proper design.Figure 15 illustrates a typical plot for input current IIversus input voltage, VI, characteristics for' ALS/' AS gateinputs during nornial operation. A typical series 54174characteristic plot is also shown for reference. Any deviceused to drive a TTL gate must source and sink current.Conventionally, current flowing toward a device inputterminal is designated as positive and current flowing outof a device input terminal is designated as negative. Lowlevelinput current is negative current because it flows outof the input terminal. High-level' input current is a positivecurrent because it flows into the input terminal.For transmission line conditions, a more accurate plotof the reverse bias section of these curves is required. Thesecurves, Figure 16, are characteristic of the input clampingdiode.Low-Level Input CurrentFigure 17 illustrates the dc equivalent of a standard, ALSI' AS input circuit and shows the input current pathsduring a low-level input state. The low-level input currentis primarily determined by resistor Rl. However, low-levelinput current is also a function of the supply voltage, theambient temperature, and the low-level input voltage. Too>i"0>;Coc1>-20-30-40/'ALSOOA.-'AS1000~'LSOOII-Input Current-rnA•C/)....."-oc.Q)a:co.~COUc..c.«Figure 15. Input Current vs Input Voltagefor TTL Families3-17

VIL -Low·Level Input Voltage-V2.0 1S 1~ OS o.-----~r-----_,r-----~~----~OVee-10INPUT~02-20Figure 17. DC Equivalent Input Circuit forSeries 'ALS Gate• l>'C'E.C;"Q),.....O·:::J:JJCD'Co...,.....en'ASOO.JI ,'LSOOJ'ALS1000A ~'ALSOOA../~'SOO-30«E.!.-40 ~:::lu-60-70'AS1000 -80Figure 16. Low-Level Input Current vs High-LevelInput Voltage for TTL Families:::lco::.,~-50 -!o ==-II-Iassure desired device operation under all possible conditions,the worst-case test is performed on all devices. Supplyvoltage is taken to the highest allowable value to cause thelow-level input current to be at a maximum. With theexception of the input under test, all unused inputs are takento a high level. This enhances any contribution of these inputsto the low-level input current of the emitter under test.Input Clamping Diode TestThe quality of the input clamping SBD (D2 in Figure 17)is tested by ensuring that the forward voltage drop is notgreater than - 1.2 V for' AS and - 1.5 V for I ALS witha forward current of 18 rnA. These values are guaranteedat minimum supply voltage and are valid across the operatingtemperature range. The characteristic of the input diode isillustrated in Figure 16.High-Level Input CurrentAnother input parameter that must be measured andcontrolled is high-level input current. To ensure desireddevice operation under all possible conditions, the worst-casetest is performed with all unused inputs grounded and supplyvoltage at its maximum value. This provides the highest valueof low-level input current. Those devices with a high-levelinput current of sufficient magnitude to cause a degradationof high-level output voltage at an output must be screened out.Input Breakdown TestAn additional high-level input current test is performedto check for base-emitter breakdown under the applicationof the full range of input voltages. This test is performedunder the worst-case supply voltage conditions and isimportant because the base-emitter junction is small and caneasily be overdissipated during the breakdown conditions .Output CharacteristicsThe most versatile TTL output configuration is the pushpull(totem-pole) type. The totem-pole output has a lowoutput impedance drive capability at both high and low logiclevels. Both I ALS and I AS families use this configurationand have fanouts of 40 in both the high- and low-level states.High-Level Output CharacteristicsThe ability of the totem-pole output to supply high-leveloutput current is parametrically tested by applying a highlevelinput current value during measurement of high-leveloutput voltage. However, the quality of the output stage isbest indicated by parametrically measuring its currentsourcing lOS capability when connected to ground. Figure 18shows the equivalent output circuit under high-level outputconditions.Figure 19 illustrates typical high-level characteristics.When measuring worst-case high-level output voltage,minimum supply voltage is used. A worst-case low-level3-18

input voltage is applied to an input and all unused inputs aretied to supply voltage.~--------~~-Vcc....... -~....--OUTPUT'ALS~----~~-------~--VccLow-Level Output CharacteristicsFigure 20 shows that section of the output drive circuitwhich produces a low-level output voltage VOL. Thischaracteristic is also tested at minimum supply voltage.Figure 21 illustrates the typical curve.Switching SpeedTwo switching-speed parameters are guaranteed onSeries • ALS and • AS gates: propagation delay time for ahigh-level to a low-level at the output tpHL, and a low-levelto high-level transition time tpLH. Both parameters arespecified with respect to the input pulse using standard testconditions as follows:VCC= 4.5 V to 5.5 VCL= 50 pFRL= 500TA = MIN to MAXUnder these conditions, times in the order of 4 ns for' ALSand 1.7 ns for' AS are typical. Figures 22 and 23 illustratehow the propagation delay time for • ALS and 'AS devicesvary with load capacitance.I'ASL---.J\IIo/Ir---c .... OUTPUTFigure 18. Equivalent Output Circuit for, ALSI' AS GatesMost current in the output stage is drawn when bothoutput transistors are on (i.e., during output transitions, theaverage power dissipation of a gate with a totem-pole outputincreases with operating frequency). This is caused by morehigh-current transitions per second at the output as thefrequency increases. Figure 24 illustrates the effect for both'ALS and 'AS devices.4>II::lo>IItJ)+'"...oc.Q)a:t:o'';:COt.)"E..c.«IOH-mAFigure 19. High-Level Output Voltage vs High-Level Output Current3-19

DC Noise MarginsNoise margin is a voltage specification which guaranteesthe static dc immunity of a circuit to adverse operatingconditions. Noise margin is defined as the difference betweenthe worst-case input logic level (VIR minimum or VILmaximum) and the guaranteed worst-case output (VOHminimum or VOL maximum) specified to drive the inputs.Table 2 lists the worst-case output limits for the 'AS and'ALS families.~--~"----~'-~OUTPUT~------------~'-~I-OUTPUT'ALS'AS':"Figure 20. Low-Level Output Circuit for' ALS/' AS Gates3.02.52.0.~1.5»"C 1.0"E..O·Q)r+O' 0.5::J:0CD"C o O~______ ~ ______ ~ ______-L______-L______ ~ ______ ~~ ______ ~ ______ ~ ______ ~~ 0 20 40 60 80 100 120 140 160 180fJ)IOL-mAFigure 21. Low-Level Output Yoltage vs Low-Level Output Current3-20

19181716151413IIIcI 12~11~c 10 0'i 9a.etI.8I 7...J::t 6E-543200 100 200 300 400Load Capacitance-pFFigure 22. High- to Low-Level Propagation Delay vs Load Capacitance500201918171615III 14cI 13~Oi 120c 110'i 10a. 9etI.8I::t...J 7E-6543200 100 200 300 400Load Capacitance-pFFigure 23. Low- to High-Level Propagation Delay vs Load Capacitance500IItJ).......,oc.Q)a:s::::o.~CO.~C.c.«3-21

100605040;: 30E~20e".,c..c.~10a.~i56~0 5c..I"'C 4c..32IJ ' 'level»'C"EoC:;"Q),...O·:::l::DCD'Co ...,...(J)11.0 2.0 4.0 6.0 8.0 10.0 20.0 40.0 60.0 80.0 100.0Specified Logic Levels and ThresholdsThe high-level noise margin is obtained by subtractingVOH minimum from VIH minimum. The low-level noisemargin is obtained by subtracting VIL maximum from VOLmaximum. The worst-case high-level noise margin isguaranteed to be at least 500 mV for both 'AS and 'ALSdevices and at least 300 mV for low-level noise immunityacross the operating free-air temperature ranges.The usefulness of noise margins at the system designis the ability of a device to be impervious to noise spikesat the input. The input voltage falls into one of threecategories: low-logic state (between ground and 0.8 V),threshold region (between 0.8 V and 2 V), or high-logic state(between 2 V and Vee). If an input voltage remainsexclusively in the low-logic or high-logic state, it can undergoPARAMETERIVIf-Frequency-MHzFigure 24. Power Dissipation per Gate vs FrequencyTable 2. Worst Case Output Parameters'AS10°C to 70 °CIVIHIMINI 2VILIMAXI 0.8VOHIMINI @ ee = 4.5 V* 2.5VQLIMAX) 0.5High Level NoiseMargin IVOH-VIH)Low Level NoiseMargin IVIL -VOL)0.50.3*Actual specification for VOH(min) is Vee - 2 V.any excursions within that state. A level change from 5.5 Vto 2 V or from ground to 0.8 V should not affect the outputstate of the device. To guarantee an expected output levelchange, the appropriate input has to undergo a change fromone input state to the other input state (i.e., a transitionthrough the threshold region). If a device will not remainin the correct state when voltage excursions on the input areoccurring, it is violating its truth table.Noise RejectionThe ability of a logic element to operate in a noiseenvironment involves more than the dc or ac noise marginspreviously discussed. To present a problem, an externallygenerated noise pulse must be received into the system andcause a malfunction. Stable logic systems with no storage'ALS 'AS 'ALS10°C to 70 °CI I-55°C to 125°CI I-55°C to 125 0 CI2 2 20.8 0.8 0.82.5 2.5 2.50.5 0.5 0.40.5 0.5 0.50.3 0.3 0.43-22

elements are practically impervious to ac noise. However,large dc voltages could cause noise problems. Systems withtriggerable storage elements or those operating fast enoughfor the noise to appear as a signal are much more susceptibleto noise.The noise voltage must be radiated or coupled into thecircuit. The amount of noise required to develop a give,nvoltage is a function of the circuit impedance. Because ofthe low output impedance of TTL circuits, noise immunityis improved. Noise is transferred from the source (with somearbitrary impedance) through a coupling impedance'to theimpedance of the circuit under consideration.Figure 25 shows a circuit where the coupling impedanceis stray capacitance and the load impedance is provided bythe gates. The relatively tight coupling of this circuit andthe loading effect on the driving source is significant enoughSTRAY COUPLINGCAPACITANCEFigure 25. Stray Coupling Capacitanceto be considered. However, since the source effect is difficultto assess and is in a direction to improve rather than degradethe noise rejection, its effects are ignored. This results ina worst-case type of response indication. In the case ofradiated noise, the source resistance is a definite factor innoise coupling and essentially replaces the reactive couplingimpedance.By ignoring the driving source impedance to makeconditions more nearly standard, it is possible to determinea set of curves relating the developed noise pulse to the noisesource amplitude, the noise rise or fall time, the couplingimpedance, and the load impedance. Curves have beendeveloped1 for several different input waveforms. Since the, ALS waveform is essentially a ramp with a dv Ivt of 1 V Ins(approximately 2.5 V/ns for 'AS), the most applicable curveis that for a ramp input.Figure 26(a) shows the equivalent circuit from whichthe ramp response plot in Figure 26(b) was developed. Theinput pulse shown in Figure 26(c) is a ramp input.whereEj = Maximum input voltage andT = Total rise time of input voltagewhereThe output pulse is represented analytically bytiT'O(t) ~ :i RC (1-' RC/T)eO(i)= Ej T(l_e- i/T )RCT=-T8(i) = ( -ilr)T l-e .eO(i)8(i)=-Eiwith holding for unit time. This is followed by anexponentially decaying voltage with a time constant T. Valuesof T and i on the figure are normalized by the value of thetotal rise time of the stimulated noise pulse ej. UsingFigure 26(b), the pulse width and amplitude of the couplednoise pulse can be estimated.As an example, using the circuit shown in Figure 25,apply a noise pulse of 3 V in amplitude and rising at 1 V InsCla)RE~t2l-I=:. I~ I1.0 r---::--------...,.-1II-------,oI~ 0.8ei .J- T = 00C~ 0.6:::l~c5 04~ .~ 0.2liz2 4 6Normalized Output Pulse Time-iIb)Figure 26. Evaluations of Gate Response toFast Input PulsesIe)T8II(J)........oc.Q)a:co"';::;CO"~C.c.

with gate 2 at a high-logic state. Assume a nominal outputimpedance of 58 n (30 n for' AS) and coupling capacitanceof 10 pF. Use the following formula:T I · . T -~ - 3 tota nse time - 1 V/ns** - ns**2.5 V/ns for 'ASt 1.2 ns for' AS**2.5 V Ins for' ASIIRCT -T (10 x 10- 12)(58)30.58 x 10-930.19 nsTo convert the normalized values of T and i inFigure 26(b) to actual values, multiply by 3 ns. The outputvoltage scale will be multiplied by 3 V. Using the T = 0.19curve gives a peak eo of 0.57 V (0.19 x 3) and a pulse widthof 3 ns at the 50% points. To determine whether this pulsewill cause interference, enter these values (0.57 V and 3 ns)on the graph shown in Figure 27. Since the gates haveapproximately 1.8 V of noise immunity at this point, theyshould not be affected.If an open-collector gate is used with a passive 1 kn pullupresistor, the situation would change. Use the followingformula:Total rise timeT =t 1.2 ns for' AS~- tI V/ns** - 3 ns(10 x 10- 12)(1 x 103)310 x 10-9310= T nsNow the amplitude (from the curves) approaches 2.58 V(0.86 x 3) and the pulse width at the 50% points isapproximately 8.52 ns (2.84 x 3). The next gate willpropagate this pulse.This example is an oversimplification. The couplingimpedances are complex (but resolvable into RLC seriescoupling elements) and the gate output impedance changeswith load. Our purpose is to show why and how the lowimpedance of the active TTL output rejects noise and to makea compadson with a passive pull-up.The ability to operate in a noisy environment is aninteraction of the built-in operating margins, the time requiredfor the device to react, and the ease with which a noisevoltage is developed. In all cases, except the ability to reactto short noise pulses, the TTL design has emhasized noiserejection.Nothing has been discussed concerning noise in devicesother than gate circuits. Many MSI devices are complex gatenetw~rks and, because'oftheir small size, are more superiorin a noisy environment operation than their discrete gateequivalents. Noise tolerance of latching devices is impliedin the setup times, hold times, clock pulse width, data pulsewidths, and similar parameters. Output impedances and inputnoise margins are quite similar to those of the gates and may'be treated in a similar manner. If a latching device doesbecome noise triggered, the effective error is stored and doesnot disappear with the noise.Parameter measurement information is shown inFigure 28.:£I.!:-ti~10987654.. ,\3-;Q.2\PULSE"REJrTEDPULSE PROPAGATED..................r--~'ALS\"'---r---'AS2 3 4 5 6Pulse Amplitude-VFigure 27. Theoretical Required PulseWidth vs Pulse Ainplitude for' AS and' ALS InputsGUIDELINES FOR SERIES • ALSI' AS TTLSYSTEM DESIGNSystem layout and design requirements for AdvancedSchottky TTL circuits are essentially the same as thoseguidelines which have previously been established and areapplicable for all high-performance digital systems. Tables 3through 6 provide a brief summary of the solutions to mostdesign decisions needed to implement systems usingAdvancdd Schottky TTL. Supplementary data which may beuseful for developing specific answers to unique problemsis provided later.3-24

7V?I> RL=R1=R2FROM OUTPUTU(~~E~O~.:~Tt RlI 0 ~~~~FROM OUTPUTUNDER TESTfccRLTCL(S~No""TESTPOINTSlR1FROM OUTPUT - ...--4....- ....-0() tESTUNDER TESTPOINTCL(See Note 1)R2LOAD CIRCUIT FORBI·STATETOTEM·POLE OUTPUTSLOAD CIRCUIT FOROPEN-COLLECTOR OUTPUTS=LOAD CIRCUIT FORTHREE·STATE OUTPUTSTIMING3.5 V::eU~ote 2) _____ .1/1.3 V ____ 0.3 VJ4-th-+tJ4-tsu...... IDATA .-- - 3.5 VINPUT 1.3" 1.3 V(See Note 2)0.3 VVOLTAGE WAVEFORMSSETUP AND HOLD TIMESHIGH.LEVEL - - - 3.5 VPULSE 1.3 V 1.3 VI I 3, I4---tw----+l O. VJ+---tw-----+l3.5 VLOW.LEVELIPULSE 1.3 V 1.3 V----0.3VVOLTAGE WAVEFORMSPULSE WIDTHS:~:u~ote:dl 1.3V \;;;--- 3.5VIN PHASEOUTPUT:"tPLH~ ~tPHL .,I0.3 VI 1.3 V : 1.3 VI, I VOLIif-tpLH+tIf-tPHL -.tII Y I ~i -VOH-----~: Fl VOHOUT OF PHASE 1.3 V 13 VOUTPUT . •(See Note 3) '-____...JVOLTAGE WAVEFORMSPROPAGATION DELAY TIMESVOLOUTPUTCONTROL(LOW·LEVELENABLING)1.3 V 1.3 VII~INOTES: 1. CL includes probe and jig capacitance.2. All input pulses have the following characteristics PRR :s 1 MHz, tr = tf = 2 ns, duty cycle = 50%.3. When measuring propagation delay times of 3·state outputs, switch S1 is open.4. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.POWER SUPPLY REGULATIONPower supply regulation cannot be treated as if it is anindependent characteristic of the device involved. Powersupply regulation, along'with temperature range, affects noisemargins, fanout, switching-speed, and several otherparameters. The characteristics most affected are noise3'5V-1------- 0.3 VI-+I ...... ttpZL ~ I+-1 I' PLZI I I IWAVEFORM 1 ---~I"'" ISl CLOSED I I ___'t.I I _--- ""3.5 V(See Note 4) I tPHZ-+l -.,... - -:t. - - VOLWAVEFORM 2S10PEN(See Note 4)Figure 28. Parameter Measurement Informationl+" .L 0.3 VtpZH-M-+!I _--....--J---- VOH--l.~~vVOLTAGE WAVEFORMSENABLE AND DISABLE TIMES, THREE·STATE OUTPUTSmargin and fanout. When these two parameters are withinthe specified limits, the power-supply regulation willnormally be within specified limits. However, on a devicewhere auxiliary parameters are more critically specified, amore restrictive power-supply regulation is normallyrequired. When power-supply regulation is slightly outsidethe specified limits for TTL devices, the device may still3-25en ....,-oCoQ)a:s::::::o'';:C'C,~CoCo«

operate satisfactorily. However, if high ambient-noise levelsand extreme temperatures are encountered, failures mayoccur.Application of a supply voltage above 7 V (absolutemaximum rating) will result in damage to the circuit.Since power dissipation in the package is directly relatedto supply voltage, the maximum recommended supplyvoltage for TTL devices is specified at 5.5 V. This providesan adequate margin to ensure that functional capability andlong-term reliability are not jeopardized.High-level output voltage is almost directly proportionalto supply voltage (i.e., a drop in supply voltage causes a dropin high-level output voltage and an increase in supply voltageresults in an increase in high-level output voltage). Becauseof this relationship, high-level output voltage for' ALSI' ASdevices is specified as supply voltage - 2 V (Vee - 2 V).Since high-level output voltage is directly related tosupply voltage, the output current of the device is also directlyrelated. The output current value is established by choosingoutput conditions to produce a current that is approximatelyone-half of the true short-circuit current. ,It is advantageous to regulate or clamp the maximumsupply voltage at 5.5 V including noise ripple and spikes.When this conditions exists, unused AND and NAND gatescan be connected directly to the supply voltage.Table 3. Guidelines for Systems Design for Advanced Schottky TTLITEMSingle wire connectionsCoaxial and twisted-pair cablesTransmission-line-groundCross talkReflectionsResistive pull-upGUIDELINEWire lengths up to approximately 12 inches may be used. A form of ground plane is desirable.Use point-to-point routing rather than parallel. If the wire is longer than 12 inches. use either adense ground plane with the wire routed as close to it as possible. or use a twisted-pair cable.Design around approximately 80 {J to 100 {J of characteristic impedance. Cross talk increases athigher impedances. Use a coaxial cable of 93 {J impedance (e.g .• Microdot 293-3913). For twistedpaircable. use number 26 or number 28 wire with the insulation twisted at the rate of 30 turnsper foot.Ensure that transmission-line ground returns are carried through at both transmitting and receivingends. VCC decoupling ground. device ground. and transmission-line ground should have a commontie point.Use point-to-point back-panel wiring to minimize noise pickup between lines. Avoid long unshieldedparallel runs. However. if they must be used. they should carry signals that propagate in the samedirection.Reflections occur when data interconnects become long enough that 2-line propagation delaysare pulse transition times. For series TTL. reflections are normally of no importance for lines shorterthan 12 inches.If fanout of driving output permits. use approximately 300 {J of resistive pull-up at the receivingend of long cables. This provides added noise margin and more rapid rise times.lEITable 4. Guidelines for Printed Circuit Board Layout for Advanced Schottky TTLITEMGUIDELINESignal connections Whenever possible. distribute loads along direct connections. Signal leads should be kept as short as possible.However. lead lengths of up to 15 inches will perform satisfactorily. This is especially for large boards thatuse a ground plane. ground. and/or VCC plane. In addition. it will perform satisfactorily for small boards usingground mesh or grid. In high-frequency applications. avoid radial fanouts and stubs. If they must be used todrive some loads. reduce lead length proportionally and avoid sharp bends. Normal on-board fanouts andinterconnections do not require terminations. Response of lines driving large numbers or highly capacitive loadscan be improved with terminations of 300 {J toVCC and 600 n to ground in parallel with the last load if fanoutof the driving output permits.Conductor widthsSignal-line spacingInsulator materialSignal-line widths down to 0.015 inch are adequate for most signal leads.Signal-lead spacing on any layer down to 0.015 inch can be used especially if care is taken to avoid adjacentuse of maximum length and minimum spacing. Increase spacing wherever layout permits. Pay particular attentionto clock and/or other sensitive signals.Thickness of insulation material used for a multilayer board is not critical. If ground and VCC planes or meshesare used. their capacitive proximity can be used to reduce the number of decoupling capacitors needed andthis also supplements the supply bypass capacitor.3-26

Table 5. Guidelines for General Usage of Advanced Schottky TTLITEMGUIDELINEPower supply For RF bypass supply primary. maintain ripple and regulation at less than or equal to 10%.VCC decouplingOn-board groundingSystem groundingDecouple every 2 to 5 packages with RF capacitors of 0.01 to 0.1 p.F. Capacitors should be located as nearas possible to the decoupled devices. Decouple line driving or receiving devices separately with 0.1 p.F capacitorsbetween VCC and the ground pins.A ground plane is essential when the PCB is relatively large (over 12 inches). Smaller boards will work withground and/or VCC mesh or grid.Try to simulate bus bars with a width to thickness ratio greater than or equal to 4. This can be accomplishedby multiple parallel wires or by using flat braid. Performance will be enhanced when a copper or silver-copperbus is used. The width to thickness ratio required will vary between systems. but greater than or equal to 4will satisfy most systems.Table 6. Guidelines for Gates and Flip-Flops Using Advanced Schottky TTLITEMData input rise and fall timesUnused input of AND and NANDgates and unused preset andclear inputs of flip-flopsUnused input of NOR gatesUnused gatesIncreasing gate/buffer fanoutGUIDELINEReduce input rise and fall times as driver output impedance increases. Rise and fall times shouldbe equal to or less than 15 ns/V and essentially free of noise ripple.Tie the unused input of AND and NAND gates and the unused preset and/or clear inputs offlip-flops as follows:1. Directly to Vcc. if the input voltage rating of 5.5 V maximum is not exceeded.2. Through a resistor equal to or greater than 1 kO to VCC' Several inputs can be tied to oneresistor.3. Directly to a used input of the same gate. if maximum fanout of driving device will not beexceeded. Only the high-level loading of the driver is increased.4. Directly to an unused gate output. if the gate is wired to provide a constant high-level output.Input voltage should not exceed 5.5 V.Tie unused input to used input of same gate. if maximum fanout of driving device will not beexceeded or tie unused input to ground.Tie input of unused NAND and NOR gates to ground for lowest power drain. Tie inputs of unusedAND gates high and use output for driving unused AND or NAND gate inputs.Connect gates of same package in parallel.Clock pulse of flip-flopsSUPPLY VOLTAGE RIPPLEDrive clock inputs with a TIL output. If not available. rise and fall times should be less than 50 ns/Vand free of ripple noise spikes.Ripple in the supply voltage is generally considered apart of the supply voltage regulation. However, whencombined with other effects (e.g., slow rise times), ripplevoltage is more significant.The effect of ripple voltage VR can appear on either thesupply voltage Vee or the ground supply GND. When rippleappears on the supply voltage, it causes modulation of theinput signal. The extent of the effect depends upon circuitparameters and source impedance.The turning on of transistor Q5, shown in Figures 12and 13, is controlled by the voltage at the base of transistorQ2 with respect to ground in accordance with the formula:VB = VBE of Q2 + VBE of Q3 + VBE of Q5When ripple voltage is modulated onto the input voltage,the amplitude depends on the source impedance (Figure 29).The amplitude can be determined by the following equation:wherellVR = VR(RlI~lI! RZ)=VR(RI :lfjRi)Rl = source impedancefj = gain of transistor Q 1.Ripple voltage has the effect of adding extra pulses tothe input signal (Figure 30). When ripple voltage appearsin the ground supply, the threshold voltage is modulated andextra pulses occur (Figure 31).•(f)....,oc.Q)a:s:::o'';:CO(JC.c.«3-27

lEIl>'C"2-(i'Q)r+0'~:0CD'Co"""Ir+tJ)Although decreasing the source impedance will reducethe effects of ripple voltage, it cannot be eliminated entirelybecause the emitter-base junction has an apparent resistanceof approximately 30 O. Because of cancellation between thedriving gate and the driven gate, low-frequency ripple is nota problem.+5VGATEDCONSTANTCURRENTSOURCER1-5 V -= -=Figure 29. Effect of Source Impedance on Input NoisevVB~~~--------------------~TVOL '---------------I~ TFigure 30. Spurious Output Produced by SupplyVoltage RippleVCCVo.: when VI is constant, anincrease in VR will resultin a decrease in V.Figure 31. Effect of Ground Noise on Noise MarginNOISE CONSIDERATIONSExtraneous voltages and currents (called noise)introduced into a digital logic circuit are discussed in thefollowing paragraphs. Figure 32(a) is a typical digital logic(b)PRESETaD----QCLOCKK QCLEAR(a)E:_3:LOCKFigure 32. Typical Logic Circuit with Noisy Inputcircuit consisting of a NAND gate and a J-K flip-flop. Whena small noise pulse is coupled onto the clock input[(Figure 32(b)), the flip-flop does not respond and the Qoutput is correct. However, when a large noise pulse iscoupled onto the clock input [(Figure 32(c)), the flip-flopsees the pulse as a clock transition and an erroneous Q outputoccurs. Therefore, it is essential to protect digital logiccircuits from noise.Noise Types and Control MethodsThe noise types encountered in digital logic systems,their source, and the method of controlling them are asfollows:I. External noise - External noises radiated intothe system. The sources include circuit breakers,motor brushes, arcing relay contacts, andmagnetic-field-generating. The methods ofcontrolled to be considered are shielding,grounding, or decoupling.2. Power-line noise - Noise coupled through theac or dc power distribution system. The initialsources and controlling methods are the same asfor external noise.3. Cross talk - Noise induced into signal lines fromadjacent signal lines. Controlling methods toconsider are shielding, grounding, decoupling,and, where possible, increasing the distancebetween the signal lines.4. Signal-current noise - Noise generated in strayimpedances throughout the circuit. Thecontrolling methods to consider are shielding,grounding, decoupling, and, where possible,reduction of stray capacitance in the circuit.5. Transmission-line reflections - Noise fromunterminated transmission lines that causeringing and overshoot. The method of controlis to use, where possible, terminatedtransmission lines.6. Supply-current spikes - Noise caused byswitching several digital loads simultaneously.The controlling method is to design, wherepossible, the system so that digital loads are notswitched simultaneously.(c)3-28

ShieldingIn addition to its own internally generated noise,electrical equipment must operate in an extremely noisyenvironment. Noise pulses, which may come from a n'umberof sources, consist of an electrostatic field, andelectromagnetic field, or both. The noise waveform must beprevented from entering the equipment. This is accomplishedby shielding. Since the noise fields are usually changing ata rapid rate, the shield required to exclude them may be verysmall. For effective exclusion, the sensitive circuits must becompletely shielded.Aluminum or similar materials are effective in stoppingelectrostatic noise. However, only a ferrous metal cansuccessfully protect equipment against magnetic fields. Whileit is helpful to connect the system to earth ground, the shieldsystem must be complete and must be grounded to the systemground to prevent the shield from coupling noise into thesystem.External noise may be conducted into the system by thepower lines. Decoupling and filtering of these lines shouldbe standard design procedure.Grounding and DecouplingThe total propagation delay is of secondary importancein generation of internal noise. The actual transition timedetermines the amplitude and frequency spectrum of thegenerated signal at the higher harmonics. Application of theFourier integral to series 'ALS/' AS waveforms showsfrequency components of significant amplitude that exceed100 MHz. Because of the frequency spectrum generatedwhen an 'ALSI' AS device switches, a system using thesedevices must consider problems caused by radio frequency(RF) even though the repetition rates may be only a fewmegahertz. The transient currents generated by chargingcapacitors, changes in the levels of dc, line driving, etc.,must be considered. In Figure 33 for example, a gate drivinga'transmission line is represented by a voltage source E,having an output impedance Zs connected to an impedanceZO, and loaded with a resistance RL.Until after a reflected pulse returns from the terminationof the transmitting device, line termination is not a factorin drive. current. In a practical TTL circuit, the linetermination must be high relative to the line impedance. For"ZoLINE INPUT.",---- ........../ ,/ \\I, 'LINE" ' ___ /Iline /" I CURRENTFigure 33. Diagram Representing a Gate Driving aTransmission LineRexplanation purposes, assume that the source voltage is 5 Vin amplitude, the output impedance of the source is 50 nandthe line impedance is 50 n. When the source voltage makesthe transition from 0 V to 5 V, the voltage across the inputof the line VI is determined by the following equation:ZoVI= E--- =2.5 VZs + ZowhereE = source voltageZo = line impedanceZs = source impedanceFor the 50 n line to become charged, the current thatmust flow onto the line is determined by the followingequation:2.5Zo 50= 50 mAIn addition, this current flows in the ground return,which, in this case, is the transmission-line ground. If theline and return are originated and terminated close to thedriving and receiving devices, there is no discontinuity inthe line. Where the ground is poorly returned, the currentflow sees the discontinuity in the cable as a high impedanceand a noise spike is generated (i.e., the ground current seesa low impedance and a current cancellation if the ground isproperly carried through and, if not, it sees a highimpedance). Figure 34 presents a specific example. Assumethat the gate driving the line is switched from the high tolow state. Current flow is indicated by the arrow markedwith an I. Since the line is improperly returned to the driver,a pulse is developed across the impedance. A possibleconsequence is the false output of gate 3 (G3).If the ground return is properly connected, the properresults are obtained. The impedance discontinuity iseliminated and current cancellation occurs at the groundpoint. Undesirable voltage spikes are then eliminated. Twoempirical rules to reduce transmission-line currents have beenestablished and have been found to be effective (Figure 35).1. Carryall returns, including twisted pair andcoaxial cables, to a good ground termination.Ground line returns close to the driving andreceiving devices.*Impedance of poor ground returnFigure 34. Noise Generation Caused by PoorTransmission-Line Return3-29.....rnoc.Q)a:I:o"';:CO"~C.c.«

2. Decouple the supply voltage of line-driving andline-receiving gates with a O.I-I'F disk ceramiccapacitor.As the devices change state, current levels changebecause of the different device currents required in each state,the external loading, the transients caused by charging anddischarging capacitive loads, and the conduction overlap inthe totem-pole output stage. When a gate changes states, itsinternal supply current changes from high to low (these valuesare stated on the data sheet for each device). In addition,any capacitance, stray or otherwise, inust be charged ordischarged for a logic state change. The capacitance mustbe charged by a current determined by -dvI = C dt (4)If the total stray capacitance on a gate output, the logic-levelvoltage excursion, and the associated rise or fall times areknown, then the ideal-case instantaneous current during thetransition can be calculated.Vcc----~-----------Broken arrow shows path of line-charging currentFigure 35. Ideal Transmission-LineCurrent HandlingFrom Eq. (4) it can be determined that the currenttransient for charging load capacitance will increase withhigher speed TTL circuits. Therefore, the SeriesIII54ALS174ALS devices will have lower transient current thanthe Series 54AS174AS devices. Another parameter thatshould be considered is the value of R7 (shown in Figures 12and 13). Resistor R7 acts as a limit on the charging current.» The current required for charging load capacitance CL"C (Figure 36) is supplied by the supply voltage when the'E.. transition is from logic low to logic high at the output ofC:;" gate 1 (Gl). When the output ofGl goes from high to low,Q)r+0"::sJlCD"Co...r+en3-30ICC------__ ------~~------~------VCCCL includes all capacitance: stray. device. etc.Figure 36. Circuit with Effective Capacitive Loadingthe load capacitance is shorted to ground by transistor Q5(shown in Figures 12 and 13) and has no effect on supplycurrent.A characteristic common to all TTL totem-pole outputstages contributes an additional current transient when theoutput changes from a logic low to a logic high. Thistransient, or spike, is caused by the overlap in conductionof the output transistors Q7 and Q5 (shown in Figures 12and 13). The situation arises because transistor Q7 can turnon faster than transistor Q5 can turn off. This places a directcircuit consisting of transistors Q7 and Q5 and resistor R4between supply voltage and ground. For all series' ALS TTLcircuits, the maximum possible peak current can bedetermined bXVcc VCEQ6 - VBEQ7 - VCEQ5ICCmax = ~~----~~R~7~--~~--~~However, due to the active turnoff circuit (consisting of R5,R6; and Q4), Q5 will be only slightly in the linear regionand the current spike will be less.The total supply-current switching transient is then acombination of three major effects: the difference in highleveland low-level supply current, the charging of loadcapacitance, and the conduction overlap. Tests wereperformed to demonstrate these effects. The results are shownin Figure 37. Six types of series TTL devices were testedwith no load (i.e., the oscilloscope was connected to theoutput only when measuring Vo and the photographs weredouble exposed). This was to approximate the effects ofconduction overlap isolated from the transient caused bycharging load capacitance. Different vertical scales were usedon some of the photographs.The results are almost as predicted. The low-powerdevices have the lower transients. Since it is the fastestcircuit, the SN74ASOO device should be highest. However,a decrease is shown, and the reason for the decrease isexplained (Figure 39). The additional circuits to reduceconduction overlap of the output transistors result in a smallertransient even though the typical switching time is 1.7 nscompared to 9 ns for the Series 54174LS.The second series of tests shown in Figure 37 cover acapacitive load of.50 pF. For this test, all of the supplycurrent transient peaks increase in amplitUde and width.Because of the larger transient currents, voltage spikeson the supply voltage measured at the IC package are alsoincreased.From these tests, it can be concluded that the conditionto be avoided (the only one that can be avoided) isunnecessary stray capacitance in circuit wiring. The chargingof load capacitance, in most cases, overshadows the othertwo effects with respect to noise produced on the supplyvoltage line by switching current transients .The flow paths of these currents have been investigatedto determine the grounding and decoupling necessary tocounteract their effects. Supply voltage decoupling may beaccomplished by one of two methods. Maintaining lowimpedance from the individual circuit supply voltage to

VOUT5VICC20 mAVCC0.2Val SN74S00 no loadbl SN74S00 load: CL = 50 pFVOUT5V5mAICC0.2 V20mAVCC5VO.2Vcl SN74LSOO no loaddl SN74LSOO load: CL = 50 pFVOUT5V5VICC10mA20 mAVCCel SN74ASOO no load0.2 Vfl SN74ASOO load: CL = 50 pFNOTES: 1. Vee = 5 V 3. Rise and fall times of input pulse are 1 ns2. Sweep is 50 ns/division 4. Vertical scales are in units shown per divisionFigure 37(a). Supply-Current Transient Comparisons....~0.2V enoCoQ)a:c:o.~CO.~C.Co«3-31

VOUT5V5VICC 20mA 50mAVec 0.2V 0.2Vg) SN74AS1000 no load h) SN74AS1000 load: CL = 50 pFVOUT5V5VICC 5mA 20 mAVec 0.2V0.2Vil SN74ALSOOA no loadil SN74ALSOOA load: CL = 50 pFVOUT 5V 5VICC 20 mA 20mAVcc 0.2 V 0.2Vk) SN74ALS1000A no load I) SN74ALS1000A load: CL = 50 pFNOTES: 1. Vee = 5 V 3. Rise and fall times of input pulse are 1 ns2. Sweep is 50 ns/division 4. Vertical scales are in units shown per divisionFigure 37(b). Supply-Current Transient Comparisons3-32

ground is common to both methods. In the first method, thesupply voltage line may be considered as a transmission lineback to a low impedance supply. The positive bus can belaminated with a ground bus to form a strip transmission lineof extremely low impedance. This line can be electricallyapproximated with lumped capacitances as shown inFigure 38. The inductances are usually a distributedcomponent which must be minimized to lower the lineimpedance.g:ZTTTTDIELECTRICr;J 'GND/COPPERT T! T TFigure 38. Transmission-Line Power BusesThen the equation is as follows:CI = .lIce.lV/.lT50 x 10- 30.10.01 J.tF(50)(20) x 10 - 120.11(20 x 10-9)= 10,000 x 10 - 12The same method may be used for the low-frequencycapacitor C2. However, the factor .IT, which was a worstcasetransient time for calculating C2, now becomes a bitambiguous. An analysis of the current cycling on a statisticalbasis is the best method in all but the simplest systems. Therecommended procedure is to decouple using 10 /IF to 50 J.tFcapacitors.D_lrSrTyR~IB~U4T~E_D __ L ____ ~ ______-4~______.~CCB~The second method is to consider the supply voltage busas a dc connecting element only and to provide a lowimpedancepath near the devices for the transient currentsto be grounded (Figure 39).ClO.OlIlFC250 IlFFigure 39. Capacitive Storage SupplyVoltage SystemFor effective filtering and decoupling, the capacitorsmust be able to supply the change in current for a periodof time greater than the pulse width of this current. Sincethe problem is essentially one of dc changes due to logic statecoupled with high-frequency transients associated with thechanges, two different values of time constant must beconsidered. Capacitors combining the high capacitancerequired for long periods with the low series reactancerequired for fast transients are prohibitive in cost and size.A good compromise is the arrangement shown in Figure 40.The typical component values may be found for the RFcapacitor C I by assuming that the parameters have commonvalues as follows:.lICC= 50 mA.lV= 0.1 V.IT= 20 nsFigure 40. Commonly Used Power Distribution andDecoupling SystemA discrete inductance of f J.tH to 10 J.tH is sometimesused for additional decoupling. However, its benefits arequestionable and its usefulness should be evaluated for theindividual system. The low-pass filter formed must becapable of keeping the transients confined and off thedistribution bus. The possibility of resonance in the inductoror LC combination must be considered.Noise spikes on the supply voltage line that do not forcethe gate output below the threshold level do not present aserious problem. Downward spikes as large as 3 V can betolerated on the supply voltage line without propagatingthrough the logic system. The system designer can beconfident that supply voltage noise can be handled even withminimal consideration.Ground noise, however, cannot be treated lightly. Pulseson a high-impedance ground line can easily exceed the noisethreshold. Only if a good ground system is maintained canthis problem be overcome. If proper attention is paid to theground system, noise problems can be minimized.The concept of a common-ground-plane structure as usedin RF and high-speed digital systems is quite different fromthe concept of the common-ground point as used in lowfrequencycircuits. The more closely the chassis and groundcan approach to being an integral unit, the better the noisesuppression characteristics of the system. Consequently, all...tn.....oc.Q)a:c::o'';:;C'ts.~C.c.«3-33

parts of the chassis and ground bus system must be boundtightly together both electrically and mechanically. Floatingor poorly grounded sections not only break the integrity ofthe ground system, but may actually act as a noise distributionsystem.For grounds and decoupling on printed circuit boards,the most desirable arrangement is a double-clad or multilayerboard with a solid ground plane or a mesh. Where componentdensity prohibits this, the ideal should be relaxed only as faras necessary. Cross talk and ground noise can be reducedon large boards with a ground plane. Some suggestions forboard grounds where a plane is not practical are as follows:1. Use as wide a ground strap as possible.2. Form a complete loop around the board bybringing both sides of the board through separatepins to the system ground.The supply voltage line can provide part of the groundmesh on the board, provided it is properly decoupled. Fora TTL system, a good guideline is 0.01 p.F per synchronouslydriven gate and at least 0.1 p.F for each 20 gates, regardlessof synchronization. This capacitance may be lumped, but ismore effective if distributed over the board. A good nile isto permit no more than 5 inches of wire between any twopackage supply-voltage points. Radio-frequency-typecapacitors must be used for decoupling. Disk ceramics arebest. It is sometimes a good practice to decouple the boardfrom the external supply-voltage line with a 2.2 p.F capacitor.However, this is optional and the RF capacitors are still. required. In addition, it is recommended that gates drivinglong lines have the supply voltage decoupled at the gatesupply voltage terminal and that the capacitor ground, deviceground, and transmission-line ground be connected to acommon point.Cross TalkWhen currents and voltages are impressed on aconnecting line in a system, it is impossible for adjacent linesto remain unaffected. Static and magnetic fields interact andopposing ground currents flow, creating linking magneticfields. These cross-coupling effects are lumped together andcalled cross talk.Back-Panel InterconnectionsInterconnecting signal lines can be grouped into threebroad categories: coaxial lines, twisted-pair lines, and straightwire lines. Because of the low impedance and shieldingcharacteristics of coaxial cable, its cross talk is minimal andis not a problem with TTL.Figure 41 illustrates a practical type of signaltransmission line. The mutual reactances Lm and Cm whichform the noise coupling paths and the line parameters Ls andCg which govern the line impedance, will vary with the typeof line used. Since cross talk is a function of the ratio of themutual impedances to the line characteristic impedances, theselection of transmission-line type must be at least partiallya factor in cross-talk considerations.ALL GATES SN74ALSOOFigure 41. Equivalent Circuit for Sending LineThe use of direct-wired connections is the simplest andlowest cost method, but they are also the poorest for noiserejection. If the lead is not cabled tightly together with similarleads, direct leads up to 12 inches in length can be used.When the length of the signal line is increased, the lineimpedance is seen by the driving and receiving gates. Asshown in Figure 42, a pulse sent along the sending line G3and G4 will be coupled via the coupling impedance Zc ontothe receiving line Gl and G2, which can be in either of thetwo logic states. The extent to which cross talk will occurdepends on the type of lines used and their relationship toeach other.(ZC) - COUPLING IMPEDANCEFigure 42. Equivalent Circuit for Cross TalkThe voltage impressed on the sending line by gate G3is determined by the equation:whereVSL= VG3 Z 0RS3 + ZoV G3 = open-circuit logic voltage swing generatedby gate G3RS3 = output impedance of gate G3Zo = line impedanceV SL = voltage impressed on the sending line.The relationship for the equation is illustrated inFigures 43 and 44.The coupling from the sending line to the receiving linecan be represented by taking coupling impedance Zc into(5)3-34

RS(Zo)TIFigure 43. Capacitive Cross Talk BetweenTwo Signal Linesaccount. An equivalent circuit to represent the coupling fromthe sending line to the receiving line is shown in Figure 44.As the voltage impressed on the sending line propagatesfarther along the line, it can be represented as voltage sourceVSL with a source impedance of ZOI (Figure 45). VSL isthen coupled to the receiving line via the couplingcapacitance, where the impedance looking into the line isline impedance in both directions. Therefore the equationbecomesZo2The voltage impressed on the receiving line (VRd thenpropagates along the receiving line to gate G2 which can beconsidered as an open circuit and voltage doubling occurs.Therefore:VG3( 1 ~)(Rs3 ~ 4i)1.5 + ZoIn the switching period, the transistor has a very low outputimpedance. Then RS3«ZO and Vin(2) can be simplified tothe following:The term Vin(2)1VG3 can be defined as the cross-talkcoupling constant.The worst-case for signal line cross talk occurs whensending and receiving lines are close together but widelyseparated from a ground return path. The lines then havea high characteristic impedance and a low couplingimpedance.For example, if we assume a coupling impedance of50 pF at 150 MHz with a line impedance of approximately2000 then:Vin(2) = 0.62VG3This level is unsatisfactory because none of the very highspeedlogic circuits has a guaranteed noise margin greaterthan one-third of the logic swing. Such potential cross talkcan be avoided by not using the close spacing of conductors.TVSL Zo Zo VRL1Figure 45. Equivalent Cross-Talk NetworkZoZcMutual coupling can be reduced by using coaxial cableor shielded twisted pairs. When mutual inductance andcapacitance are decreased, line capacitance is increased andimposes restrictions on the driver. Coaxial cable combinesvery high mutual impedance with low characteristicimpedance and shielding. It effectively eliminates cross talk,but is necessary in only the noisiest environments. Twistedpairs are adequate for most applications and are typically lessexpensive and easier to use.(f)....oc.Q)£t:c:o"';:CO"~C.c..«Figure 44. Coupling Impedances Involved in Cross Talk3-35

Printed Circuit Card ConductorsSignal interconnections on a two-sided or multilayerprinted circuit card can be grouped into twq generalcategories: microstrip lines and strip lines. The microstripline (Figure 46) consists of a signal conductor separated froma ground plane by a dielectric insulating material. A stripline (Figure 47) consists of a signal conductor within adielectric insulating material and the conductor being centeredbetween two parallel conductor planes. The importantfeatures of these type of printed circuit conductors are thatthe impedances are highly predictable, can be closelycontrolled, and the process is relatively inexpensive becausestandard printed circuit board manufacturing techniques areused. Typical impedances of these types of conductors withrespect to their physical size and relative spacings are shownin Tables 7 and 8.Table 7. Typical Impedance of Microstrip LinesDimensions Line Impedance CapacitanceH (mils) W (mils) ZO(O) per Foot (pF)6 20 35 406 15 40 3515 20 56 3015 15 66 2630 20 80 2030 15 89 1860 20 105 1660 15 114 14100 20 124 13100 15 132 12Table 8. Typical Impedance of Strip LinesDimensionsH'a = H'b =(mils)W(mils)Line ImpedanceZO(O)Capacitanceper Foot (pF)6 20 27 806 15 32 7010 20 34 6710 15 40 5612 20 37 5712 15 43 4820 20 44 4820 15 51 4230 20 55 3930 15 61 35Relative dielectric constant"" 5, and H'a = H'bCross talk on a printed circuit board is also a functionof the mutual reactances and the line parameters whichgovern the line impedance. A microstrip line and a strip lineare, by definition, conductors placed relatively close to aground plane. Therefore, they have at least one inherentproperty which tends to reduce cross talk. In addition, thethickness (H) of the dielectric and the spacing (S) of theconductors can be implemented selectively to reduce theamount of possible cross talk. The effects of these twodimensions on cross talk have been evaluated and are showngraphically in Figure 48. The data shown can be used toestimate the maximum crosstalk which will be encounteredunder the most unfavorable conditions.Relative dielectric constant "" 5TL~~~~~~~~Figure 46. Microstrip Line1TIT4~~~~~Figure 47. Strip LineGROUNDPLANES3-36

0.580.560.520.48~ 0.44Ic0.40~c0.360u 0.32~0.28~0 0.24cJ0.200.160.120.080.040 20 40 60 80 100Spacing, S (mils)Figure 48. Line Spacing VersusCross-Talk Constant120 140Transmission-Line Driving ReflectionsWhen the interconnections used to transfer digitalinformation become long enough so that line propagationdelay is equal to or greater than the pulse transition times,the effects of reflections must be considered. Thesereflections are created because most TTL interconnectionsare not terminated in their characteristic impedance.Reflections lead to reduced noise margins, excessive delays,ringing, and overshoot. Some method must be used toanalyze these reflections. Because neither the gate input noroutput impedance is linear, basic transmission-line equationsare applicable but unwieldy. Transmission-line characteristicsof TTL interconnections can be analyzed by using a simplegraphic technique.Figure 49 shows piecewise linear plots of a gate inputand both (logic-high and logic-low) states of the output fora typical TTL device. The output curves are plotted withpositive slopes. The input is inverted because it is at thereceiving end of a transmission line. The logic-high and logiclowintersections are indicated on the plot. These points arethe steady-state values which will be observed on a losslesstransmission line (Figure 50).Figure 50 shows a typical TTL interconnection usinga twisted-pair cable which, in this example, has acharacteristic impedance of approximately 30 O. To evaluatea logic-high to logic-low' AS transition see Figures 51 and52. The equation -lIZ0 (ZO = 300), which represents thetransmission line, is superimposed on the output characteristiccurves in the Bergeron plot. Since evaluation of a logic-highto logic-low transition is desired, the - lIZ0 line starts atthe point of intersection of the impedance curves of the inputand output for a logic-high state. The slope - lIZ0 thenproceeds toward the logic-low output curve. At time to, thedriver output voltage is determined by the intersection ofVoltage-VFigure 49. TTL Bergeron Diagram30 n TWISTEDPAIR BJ 1Vdrivers Vreceivers-t--t-Figure 50. 'ALS/' AS Driving Twisted Pair-lIZo and the logic-low output curve (1.2 V). Thetransmission-line slope now· becomes lIZ0 andis drawn toward the input curve. At timetl [t(n + 1) - tn = time delay ofline], the receiving gate sees-0.7 V. Now the line slope changes back to -lIZ0 andthe output curve for a logic low is approached. This actioncontinues until the logic-low intersection is reached.Figure 52 plots driver and receiver voltages versus time forthis example.A logic-low to logic-high transition is treated inapproximately the same manner (Figure 53). The Bergeronline - l/Z0 starts at the intersection for a logic low. At timeto, the driver output rises to 2.2 V and, at time tl, thereceiving gate input goes to approximately 4.35 V. Bothoutput and input voltages are plotted in Figure 54.Figures 55 through 58 illustrate 'ALS transitions andare treated in the same manner as the' AS.The scope photographs in Figures 59 through 66 showthe effectiveness of the graphic techniques. In most cases,the calculated and experimental values of voltage steps agreewithin reason. The ringing that appears for the open wireis not immediately obvious. This is because the input andoutput curves in this region lie practically along the positivehorizontal axis. At the scale used for graphic analysis, it isdifficult to go much beyond the first few reflections. Thegraphic analysis is idealized and stray capacitance andinductance are not considered.tJ)....,~o0.Q)a:r:::o.';:CO.20.0.ct3-37

'ASOOvee = 5.0 VTA = 25°e..... ......DRIVING 30-S1 UNTERMINATED LINETRANSITION (1-+0)....... 1~-- ..... 30S1..... ..... ..... ......-4 4~ -50.§.IZwa:a:B -100Figure 51. 'AS - ve Transition Bergeron Diagram»"C"En·D)ro+o·::::s::XJCD"Co...ro+en54~ 3wCl 2~..Jo> o-1-----AJto...TRANSITION (1~)BFigure 52. 'AS -ve Voltage/Time PlotIII3-38

'ASOOvee = 5.0 VTA=25°eDRIVING 30-n UNTERMINATED LINE, TRANSITION (0-+1)VOLTAGE (V)-4 -3 -2 -1~ -50EIZwa:a::::>u -100-150Figure 53. 'AS + ve Transition Bergeron Diagram54~ 3wC,?« 2I- .Jo>o-1----~AIBTRANSITION (0-+1)J'0 I I1 I I I ItoFigure 54. 'AS +ve VoltagelTime Plot...en...o0.Q)a:c:o",t:CO"~C.0.«3-39

6040'ALSOOAVee = 5.0 VTA = 25°eI DRIVING 30.nUNTERMINATED LINETRANSITION (1-0)\\\\'\ -3~n\ \\-4~ -20!...zwa::a:::::I(J -40Figure 55. ' ALS - ve Transition Bergeron Diagram5TRANSITION (1-+0)~ 3wC)4 I-i5 2 l--Jr-o-1r-AlBIg 1I1-...i I I I . ItoIFigure 56. 'ALS -ve Voltage/Time Plot3-40

-4~ -20iI Zwa:a:a -40'A LSOOAvee = 5.0 VTA = 25°CDRIVING 30-n UNTERMINATED LINETRANSITION (0-+11\\\\ll. 1\3O"'n , ,-60Figure 57. ' ALS + ve Transition Bergeron Diagram5TRANSITION (0-+11~ 3w4 l-~ 2I ...Jo>o-1I-I-I-l-AIItoIBI1It2TIMEFigure 58. 'ALS +ve Voltage/Time PlotIII...., fAoCo(J)a:c:o'';:CO.~C.Co

ovovTRANSITION (1 -+ 0)Figure 59. Oscilloscope Photograph of 'ASOOI - veTransition Using 50-Ohm LineTRANSITION (0 -+ 1)Figure 62. Oscilloscope Photograph of 'ASOO + veTransition Using 25-0hm LineovovTRANSITION (0 -+ 1)Figure 60. Oscilloscope Photograph of 'ASOO + veTransition Using 50-Ohm LineTRANSITION (1 -+ 0)Figure 63. Oscilloscope Photograph of ' ALSOOA - veTransition Using 50-Ohm Line»"C"2-C:;"Q)....c;":::l::XJCD"Co....enTRANSITION (1 -+ 0)Figure 61. Oscilloscope Photograph of 'ASOO - veTransition Using 25-0hm Lineov: ! : ill -l 1 -:::::::.:.:: --;.:: I· ~l:···, :·1:,·1::.: t:-::• t • • I ••• : ......... t ..... ! ..... : ...•TRANSITION (0 -+ 1)............. '"-ovFigure 64. Oscilloscope Photograph of ' ALSOOA + veTransition Using 50-Ohm Line3-42

References1. W.C. Elmore and M. Sands, Electronics ExperimentalTechniques, McGraw-Hill Book Co., New York, 30ff.(1949).2. M. Williams and S. Miller, Series 54ALSI74ALS SchottkyTTL Applications B215, Texas Instruments Limited,Bedford, England, August 1982.TRANSITION (1 -+ 0)ovFigure 65. Oscilloscope Photograph of ' ALSOOA - veTransition Using 25-0hm LineAcknowledgmentThis application report is an updated version ofReference 2 with significant contributions by the technicalengineering staff at Texas Instruments and particularly byRock Cozad, Rich Moore, and Bob Strong.TRANSITION (0 -+ 1)Figure 66. Oscilloscope Photograph of ' ALSOOA + veTransition Using 25-0hm Line(J)....,'ōc.Q)a:s:::o.';:;CO.2Q.c.«3-43

3-44

Appendix ANormalized Load FactorsNormalizing output drive capability and input current requirements can be very useful to designers of systems usingtwo or more of the TI TTL series of devices. It provides a set of load factors (input cuurent requirements inTable A-I), which can be summed and compared directly to the fanout capability (see Table A-2) of the output being considered.The load factor values shown are valid for any input rated at one unit load.The loading of these type of outputs can be checked from any column. However, most designs use one of the seriesas the basic building block and, since the tables cover each series individually, the designer has the choice of working fromthe column containing the normalized fanout. As an example, the designers of a system using series' AS as the basic circuitwill probably find that the use of the' ASOO and' AS 1000 columns will suit best because both fanolltand load factors areexpressed for these series of devices.The use of these simple and easy-to-remember numbers was developed within each series to make the verification ofoutput loading a matter of counting the number of inputs connected to a particular output. When mixtures of series are used,a common denominator (normalized factor) becomes useful.USE OF TABLES A-I AND A-2Every possible combination of the seven 54174 TTL families is included in these tables. If, for example, the existingsystem used 74S series logic and it is desired that some of it be replaced by series 74ALS logic, a quick check should bemade. on whether the ' ALS can be supplied with sufficient input current. By taking the 74S row and' ALS, column figuresof 2.5 and 20 are obtained for high- and low-level loads, respectively (see Table A-I). This indic~tes that, for high logiclevels, two and one-half' ALS gates can be driven for each'S series gate removed. However, if more 74S series gates arebeing driven by this' ALS device, the fanout between' ALS and'S series gate is required, you can now use Table A-2.The' ALS row and the'S column are chosen. The figures are 8 for the high-logic level and 4 for the low-logic level.In this case the lowest figure is taken so that the interconnection is reliable for both logic states. So each' ALS gate insertedwill drive 4 's series gates. .Table A-I. Normalized Input CurrentsINPUTINPUT CURRENT NORMALIZEDSERIES I/O CURRENT(rnA) '00 'HOO 'LOO 'LSOO 'SOO 'ASOO 'ALSOOA 'AS1000 'ALS1000A54/7400 HI 0.04 1 0.8 4 2 0.8 2 2 2 254/7400 LO 1.6 1 0.8 8.89 4 0.8 3.2 16 3.2 1654H/74HOO HI 0.05 1.25 1 5 2.5 1 2.5 2.5 2.5 2.554H/74HOO LO 2 1.25 1 11.11 5 1 4 20 4 2054!74LOO HI 0.01 0.25 0.2 1 0.5 0.2 0.5 0:5 0.5 0.554!74LOO LO 0.18 0.11 0.09 1 0.45 0.09 0.36 1.8 0.36 1.854LS/74LSOO HI 0.02 0.5 0.4 2 1 0.4 1 1 1 154LS!74LSOO LO 0.4 0.25 0.2 2.22 1 0.2 0.8 4 0.8 454S/74S00 HI 0.05 1.25 1 5 2.5 1 2.5 2.5 2.5 2.554S/74S00 LO 2 1.25 1 11.11 5 1 4 20 4 2054AS/74ASOO HI 0.02 0.5 0.4 2 1 0.4 1 1 1 154AS/74ASOO LO 0.5 0.31 0.25 2.78 1.25 0.25 1 5 1 554ALS!7 4ALSOOA HI 0.02 0.5 0.4 2 1 0.4 1 1 1 154ALS!7 4ALSOOA LO 0.1 0.06 0.05 0.56 0.25 0.05 0.2 1 0.2 154AS1000 HI 0.02 0.5 0.4 2 1 0.4 1 1 1 154AS1000 LO 0.5 0.31 0.25 2.78 1.25 0.25 1 5 1 554ALS1000A HI 0.02 0.5 0.4 2 1 0.4 1 1 1 154ALS1000A LO 0.1 0.06 0.05 0.56 0.25 0.05 0.2 1 0.2 1tn.....oQ.Q)a:co.';:;CO.saQ.Q.

Table A-I is normally used (in combination with Table A-2) when replacing one logic family with another in an existingsystem.Table A-2 is normally used when originally designing a system which employs several TTL families to optimizeperformance.Table A-2. Fanout Capability (Output Currents Normalized to Input Currents)SERIES541740054/740054H/74HOO54H/74HOO54LOO54LOO74LOO74LOO54LS/74LSOO54LSOO74LSOO54S/74S0054S/74S0054AS/74ASOO54AS/74ASOO54ALS/74ALSOOA54ALSOOA74ALSOOA54AS100054AS100074AS100074AS100054ALS1000A54ALS1000A74ALS1000A74ALS1000AI/OOUTPUT DRIVE NORMALIZEDOUTPUT'00 'HOO 'LOO 'LSOO 'soo 'ASOO 'ALSOOA 'AS1000CURRENT*HI 0.04 0.05 0.01 0.02 0.05 0.02 0.02 0.02(rnA)tLO 1.6 2 0.18 0.4 2 0.5 0.1 0.5HI 0.4 10 8 40 20 8 20 20 20LO 16 10 8 88.89 40 8 32 160 32HI 0.5 12.5 10 50 25 10 25 25 25LO 20 12.5 10 111.11 50 10 40 200 40HI 0.1 2.5 2 10 5 2 5 5 5LO 2 1.25 1 11.11 5 1 4 20 4HI 0.2 5 4 20 10 4 10 10 10LQ 3.6 2.25 1.8 20 9 1.8 7.2 36 7.2HI 0.4 10 8 40 20 8 20 20 20La 4 2.5 2 22.22 10 2 8 40 8La 8 5 4 44.44 20 4 16 80 16HI 1 25 20 100 50 20 50 50 50La 20 12.5 10 111.11 50 10 40 200 40HI 2 50 40 200 100 40 100 100 100La 20 12.5 10 111.11 50 10 40 200 40HI 0.4 10 8 40 20 8 20 20 20La 4 2.5 2 22.22 10 2 8 40 8La 8 5 4 44.44 20 4 16 80 16HI 40 1000 800 4000 2000 800 2000 2000 2000La 40 25 20 222.22 100 20 80 400 80HI 48 1200 960 4800 2400 960 2400 2400 2400La 48 30 24 266.67 120 24 96 480 96HI 1 25 20 100 50 20 50 50 50La 12 7.5 6 66.67 30 6 24 120 24HI 2 65 52 260 130 52 130 130 130La 24 15 12 133.33 60 12 48 240 48'ALS1000A0.020.120160252005201036204080502001002002040802000400240048050120130240"Input Current HItlnput Curent La3-46

Appendix BLetter Symbols, Terms, and DefinitionsThese symbols, terms, and definitions are in accordance with those currently agreed upon by the JEDEC Council ofthe Electronics Industries Association (EIA) for use in the USA and by the International Electrotechnical Commission (1EC)for international use. The definitions are grouped into sections applying to voltages, currents, switching characteristics, andclassification of circuit complexity.VOLTAGESVOHVOLVO(on)High-level input voltageAn input voltage level within the more positive (less negative) of the two ranges of values used to represent thebinary variables. A minimum value is specified which is the least-positive (most-negative) value of high-level inputvoltage for which operation of the logic element within specification limits is guaranteed.Low-level input voltageAn input voltage level within the less positive (more negative) of the two ranges of values used to represent thebinary variables. A maximum value is specified which is the most-positive (least-negative) value of low-level inputvoltage for which operation of the logic element within specification limits is guaranteed.Positive-going threshold voltageThe voltage level at a transition-operated input that causes operation of the logic element according to specificationas the input voltage rises from a level below the negative-going threshold voltage, VT - .Negative-going threshold voltageThe voltage level at a transition-operated input that causes operation of the logic element according to specificationas the input voltage falls from a level above the positive-going threshold voltage, VT + .High-level output voltageThe voltage at an output terminal for a specified output current IOH with input conditions applied that accordingto the product specification will establish· a high level at the output.Low-level output voltageThe voltage at an output terminal for a specified output current IOL with input conditions applied that accordingto the product specification will establish a low level at the output.On-state output voltageThe voltage at an output terminal for a specified output current with input conditions applied that according tothe product specification will cause the output switching element to be in the on state.Note: This characteristic is usually specified only for outputs not having internal pull-up elements.VO(off) Off-state output voltageThe voltage at an output terminal for a specified output current with input conditions applied that according tothe specification will cause the output switching element to be in the off state.CURRENTIIHIlLNote: This characteristic is usually specified only for outputs not having internal pull-up elements.High-level input currentThe current flowing into * an input when a specified high-level voltage is applied to that input.Low-level input currentThe current flowing into * an input when a specified low-level voltage is applied to that input.(I)..,~oa.Q)a:co",t:;C'O"~C.a.«*Current flowing out of a terminal is a negative value.3-47

IOHIO(ofl)lOSICCHICCLlligh-Ievel output currentThe current flowing into* the output with a specified high-level output voltage VOH applied.Note: This parameter is usually specified for open-collector outputs intended to drive other logic circuits.Off-state output currentThe current flowing into* an output with a specified output voltage applied and input conditions applied that accordingto the product specification will cause the output switching element to be in the off state.Note: This parameter is usually specified for open-collector outputs intended to drive devices other than logic circuitsor for three-state outputs.Short-circuit output currentThe current flowing into* an output when that output is short-circuited to ground (or other specified potential)with input conditions applied to establish the output logic level farthest from ground potential (or other specifiedpotential).Supply current, output(s) highThe current flowing into * the Vee supply terminal of a circuit when the reference output(s) is (are) at a high-levelvoltage.Supply current, output(s) lowThe current flowing into * the Vee supply terminal of a circuit when the reference output(s) is (are) at a low-levelvoltage.»"C"Eel"D)r+o·::l:lJCD"C..or+enDYNAMIC CHARACTERISTICSfmaxtHZtLZMaximum clock frequencyThe highest rate at which the clock input of a bistable circuit can be driven through its required sequence whiiemaintaining stable transitions of logic level at the output with input conditions established that should cause a changeof output state with each clock pulse.Output disable time (of a three-state output) from high levelThe time between the specified reference points on the input and output voltage waveforms with the three-stateoutput changing from the defined high level to a high-impedance (off) state.Output disable time (or a three-state output) from low levelThe time between the specified reference points on the input and output voltage waveforms with the three-stateoutput changing from the defined low level to a high-impedance (off) state. /tPLH . Propagation delay time, low-to-high-Ievel outputThe time between the specified reference points on the input and output voltage waveforms with the output changingfrom the defined low level to the defined high level.tTLHtTHLPropagation delay time, high-to-Iow-Ievel outputThe time betWeen the specified reference points on the input and output voltage waveforms with the output changingfrom the defined high level to the defined low level.Transition time, low-to-high-Ievel outputThe time between it specified low-level voltage and a specified high-level voltage on a waveform that is changingfrom the defined low level to the defined high level.Transition time, high-to-Iow-Ievel outputThe time between a specified high-level voltage and a specified low-level voltage on a waveform that is changingfrom the defined high level to the defined low level.Average pulse widthThe time between 50% amplitude points (or other specified reference points) on the leading and trailing edgesof a pulse.*Current flowing out of a terminal is a negative value.3-48

thHold timeThe time interval for which a signal or pulse is retained at a specified input terminal after an active transition occursat another specified input terminal.trelease Release timeThe time interval between the release from a specified input terminal of data intended to be recognized and theoccurrence of an active transition at another specified input terminal.tsutZHtZLNote: When specified, the interval designated "release time" falls within the setup interval and constitutes, ineffect, a negative hold time.Setup timeThe time interval for which a signal is applied and maintained at a specified input terminal before an active transitionoccurs at another specified input terminal.Output enable time (of a three-state output) to high levelThe time between the specified reference points on the input and output voltage waveforms with the three-stateoutput changing from a high-impedance (oft) state to the defined high level.Output enable time (of a three-state output) to low levelThe time between the specified reference points on the input and output voltage waveforms with the three-stateoutput changing from a high-impedance (oft) state to the defined low level.CLASSIFICATION OF CIRCUIT COMPLEXITYGate equivalent circuitA basic unit-of-measure of relative digital-circuit complexity. The number of gate equivalent circuits is that numberof individual logic gates that would have to be interconnected to perform the same function.LSIMSISSILarge-scale integrationA concept whereby a complete major subsystem or system function is fabricated as a single microcircuit. In thiscontext a major subsystem or system, whether logical or linear, is considered to be one that contains 100 or moreequivalent gates or circuitry of similar complexity.Medium-scale integrationA concept whereby a complete subsystem or system function is fabricated as a single microcircuit. The subsystemor system is smaller than for LSI, but whether digital or linear, is considered to be one that contains 12 or moreequivalent gates or circuitry of similar complexity.Small-scale integrationIntegrated circuits of less complexity than medium-scale integration (MSI).*Current flowing out of a terminal is a negative value.tn....~oCo(1)a:co"';:;nJ"~C.Co

3-50

Error Detection and CorrectionUsing SN54/74ALS632A,SN54/74ALS633 through SN54/74ALS635Robert BreuningerContributorsW.T. Greer, Jr., David Mondeel, Jay MaxeyTEXASINSTRUMENTS•U) I.tJ...oQ.Q)a:c:o"+=ico"~Q.Q.«3-51

IMPORTANT NOTICETexas Instruments (TI) reserves the right to make changes in thedevices or the device specifications identified in this publicationwithout notice. TI advises its customers to obtain the late!)t versionof device specifications to verify, before placing orders, that theinformation being relied upon by the customer is current.TI warrants performance of its semiconductor products, including SNJand SMJ devices, to current specifications in accordance with TI'sstandard warranty. Testing and other quality control techniques areutilized to the extent TI deems such testing necessary to support thiswarranty. Unless mandated by government requirements, specifictesting of all parameters of each device is not necessarily performed.In the absence of written agreement to the contrary, TI assumes noliability for TI applications assistance, customer's product design, orinfringement of patents or copyrights of third parties by or arising fromuse of semiconductor devices described herein. Nor does TI warrantor represent that any license, either express or implied, is grantedunder any patent right, copyright, or other intellectual property rightof TI covering or relating to any combination, machine, or process inwhich such semiconductor devices might be or are used.Copyright © 1984, Texas Instruments Incorporated3-52

INTRODUCTIONNEED FOR ERROR CORRECTIONWith memory systems continuing to expand and the expectationof 256K DRAMs in the near future, it hasbecome increasingly important that system designersconsider error detection and correction. Generally, thelarger the chip density, the greater the probability fordevice errors. It is easy to recognize this probability whenone considers that a 32-bit X 64K memory, using 64KDRAMs, equates to approximately 2.1 million bits ofinformation. This expands to 8.4 million bits of informationwhen using 256K DRAMs. For memory sizes larger than1/2 million bits, it is generally considered that errordetection and correction is required to guarantee highreliability.The SN54/74ALS632A, SN54/74ALS633 throughSN54/74ALS635 provide a simple solution to theserequirements in 32-bit machines. In addition, the 'ALS632Aand ALS633 provide the necessary hardware to perform bytewriteoperations which are typically used in the moreadvanced systems. To ensure the integrity of the errordetection and correction circuit itself, diagnostic capabilitieshave been provided in all four devices.The 'ALS632A series devices are not limited to only32-bit systems. They can easily be implemented in 16- or24-bit systems. In the case of 16-bit systems, the additionalmemory needed for holding the check bits can be reducedwhen compared to conventional 16-bit EDAC's.The pin function table and mechanical data for the'ALS632A, ALS633 through 'ALS635 are shownrespectively as Table 1 and Figure LOPERATIONAL DESCRIPTIONWRITE MODEDuring a memory write cycle, the EDAC is requiredto generate a 7-bit check word to accompany the 32-bitdata word before being written into memory. To placethe 'ALS632A, 'ALS633 through 'ALS635 iri the write.mode, simply take Sl and SO low. Output enable controlsOEBO through OEB3 for the 'ALS632A,'ALS633, or OEDBfor the 'ALS634, 'ALS635, must be taken high before thedata word can be applied. Output enable control OECS mustbe taken low to pass the check word to the external bus.The check word will be generated in not more than48 ns* after the data word has been applied. The 'ALS632Aseries EDACs can be made to appear transparent to memory,during the write mode, because typical write times of mostDRAMs are much larger than the propagation delay of datato check word.READ-FLAG-CORRECT OPERATIONDuring a memory read cycle, the function of the'ALS632A series EDACs is to compare the 32-bit data wordagainst the 7 -bit check word previously stored in memory.It will then flag and correct any single-bit error which mayhave occurred. Single bit errors will be detected through theERR flag and double bit errors will be detected through theMERR flag. Figure 2 shows a typical timing diagram of theread-flag-correct operation.When SO is taken high, the EDAC will internallybegin the correction process, although it should be notedthat the error flags are enabled while in the read mode. Formany applications, the simplest operation can be obtainedby always executing the correction cycle, regardless if asingle-bit error has occurred.IMPORTANT TIMING CONSIDERATIONS FOR READFLAG-CORRECT MODEThe most· frequently asked question for an EDAC ishow fast can a correction cycle be executed. Before SO canbe taken high, the data and check word must be set up atlea,st 10 ns*. In addition, the data and check word must beheld for at least 15 ns* after SO goes high. This ensures thedata and check word is saved in the EDAC's input latches.After the hold time has been satisfied, the source which isdriving the data bus can be placed in high impedance andthe EDAC's output drivers can be enabled. This isaccomplished by taking OEBO through OEB3 (,ALS632A,'ALS633) or OEDB ('ALS634, 'ALS635) low. .If the minimum data set up time is used as a reference,and the output drivers are enabled after the minimum datahold time, then correction will be accompliShed in notmore than 58 ns*.READ MODIFY-WRITE OPERATIONS .The'ALS632A and 'ALS633 contain the necessary 3hardware to perform byte-write operations. The 'ALS634and 'ALS635 are not capable of byte-write operationsbecause they do not contain an output data latch orindividual byte controls. When performing a read-modifywritefunction, typically the user would first want toperform the read-flag-correct cycle as discussed before, andshown in Figure 2. This ensures that corrected data is usedat the start of the modity-write operation.The corrected data is then latched into the outputdata latch by taking LEDBO from low to high. Uponcompleting this, modifying any byte or bytes is easilyaccomplished by taking the appropriate byte control OEBOthrough OEB3 high. This allows the user to place themodified byte or bytes back onto the data bus whileretaining the other byte or bytes. An example of a read-...(/).....oc.Q)a:c:o"';:CO"~C.c.«"These times are based on SN74ALS632A data.3-53

ceramic packages - side-braze (JD suffix)This is a hermetically sealed ceramic package with a metal cap and side-brazed tin-plated leads.'ALS632A, ALs633 ••• JD PACKAGE(TOP VIEW)'ALS634, 'ALS635 •••• JD PACKAGE(TOP VIEW)LEOBO Vce MERR VCCMERR S1 ERR S1. ERR SO OBO SOOBO OB31 OB1 OB31OB1 OB30 OB2 OB30OB2 47 OB29 OB3 OB29OB3 46 OB28 OB4 OB2SOB4 45 OB27 OB5 OB27OBS 44 OB26 OEOB OB26OEBO 10 43 OEB3 OB6 OB25OB6 11 42 OB25 bB7 OB24OB7 12 41 OB24 GNO GNOGNO 13 40 GNO OB8 OB23OBB 14 39 OB23 OB9 OB22OB9 15 OB22 OB10 OB210EB1 16 OEB2 OB11 OB20OB10 17 OB21 OB12 OB19OB11 18 OB20 OB13 OB1SOB12 19 OB19 OB14 19 30 OB17OB13 20 OB18 OB15 20 29 OB16OB14 21 OB17 CB6 21 28 CBOOB15 22 OB16 CBS 22 27 CB1CB6 23 CBO CB4 23 26 CB2CBS 24 CB1 OECB 24 25 CB3CB4 25 CB2OECB 26 27 CB3f.'i

Table I. Pin Function for 'ALS632A, 'ALS633 through 'ALS635PIN NAMESl, SODBa through DB310Es0 through OEB3(ALS632A, 'ALS633)OEDa(ALS634, ALS635)LEDBOCSO through CS6OECSERRMERRDESCRIPTIONSelects the operating mode of the EDACSl SO MODE OPERATIONL L WRITE Input dataword and output checkwordH L READ & FLAG Input dataword and output error flagsH H CORRECT Latched input data and checkword/output correctedData and error syndrome codeL H DIAGNOSTIC Input various datawords against latchedcheckword/output valid error flagsI/O port for entering or outputing dataThree state control for the data I/O port. A high allows data to be entered, andlow outputs the data. Each pin controls a data I/O ports (or one byte). OEBOcontrols DBa through DB7, OEBl controls DBa through DB15, OEB2 controls DB16 throughOB23, and OEB3 controls DB24 through DB31.Three state control for the data 1/0 port. When low allows data to outputed and a high allowsdata to be entered.Controls the dataword output latch. When low, the data output latch is transparent. When high, thelatch stores whatever data was setup at its inputs when the last low to high transistion occured on the pin.I/O Port for entering or outputing the checkword. It is also used to output the syndrome error codeduring the error correction mode.Three state control for the checkword I/O port. A high allows data to be entered and a lowallows either the checkword or syndrome code (depending on EDAC mode) to be outputed.Single error output flag, a low indicates at least a single bit error.Multiple error output flag, when low indicates two or more errors presentI4----'---READ---t ..... I~I__---------CORRECT-----------...... ,I I I4---th(81~Iw-,I I I~I --------------------------------------~I~ ________ _SI------;14==========~~:or:r~:tio;.n===========;---------------------------I:-tsU(1I--+r-thl91---+:~tdiS~DBOTHRUD~I--------K:==~IN~P~U~T~D~A~TA~W~OR~D~====~~2Z~Ic:::==~~~O~UT~P~U~T~CO~R~R~E~CT~E~D~D~A~T~A~W~O~R~D~~2Z2Z~----i4--ten--+tII : ~IDEBO THRU 0Eii3 ______________________________________ ~~tsu(1J~th(91~~tdisiCBOTHRUCB6-------1c:==~IN~P~U~T~CH~E~C~K!W~O~R~D::::~~ZZZZ~====::x:==~O~U~T~PU~T~S~Y~ND~R~O~M~E~C§O~D~E====~2ZZZ~----: t+-ten---i! iI4--tpd~ERR f$ffdl~t~UDW$#/4(,.....------V-A-L-ID-=E=R=R -FL-A-G-------~WA%YMm;J~ tpd .,MeRii ~!~~AJ:§Wff##ff4r------V-AL-I-D=M=ER=R~F-LA-G------~~(Jv'A'dD'?0jmodify-write for byte 0 is shown in Figure 3. Since thecheck word is no longer valid for the modified data word, anew one is easily generated by taking SO and Sllow. Afterthe appropriate propagation delay, the new check word willbe available.Figure 2. Read-Flag-Correct Timing DiagramIMPORTANT TIMING CONSIDERATIONS FOR READMODIFY WRITE OPERATIONSLEDBO should not be brought from low to high until45 ns* after SO goes high. This will ensure that correcteddata is latched into the data output latches. On the otherhand, LEDBO should be brought high no later than 0 ns*•t/)+Ja..oCoQ)a:c:o"';:CO(.)C.Co«3-55

efore SO and SI goes low. Again, this is to ensure that thecorrected data is stored into the data output latches. Alsoof importance is the new check word will be available nolater than 48 ns* after SO and S I goes low.DIAGNOSTIC MODE OPERATIONThe purpose of the diagnostic mode is to provide theuser with the capability of easily .detecting when the EDACor memory is failing. There are several possibilities as tohow a user might employ this feature, but Figure 4 shows a .typical timing diagram of some diagnostics which can beperformed with these devices. Generally, the user wouldfirst place the EDAC in the read mode (SO = L, SI = H),then apply a valid check word and data word. A valid checkword is one in which the user knows what the associateddata word. The user would next place the EDAC into thediagnostic mode by taking SO high, and SI low. This latchesthe valid check word into its input latches but leaves thedata input latches transparent. To ve~ify that the validcheck word was latched properly, OECS can be taken lowcausing the valid check word to be placed back onto thebus. Since the data input latches remain transparent, thisallows the user to apply various diagnostic data wordsagainst the valid check word. A diagnostic data word isone in which either a single or double bit error exists. Ineither case, the error flags should respond. The output datalatch can be verified by taking LEDBO high and confirmingthe stored diagnostic data word is the same. This is madepossible because error correction is disabled while in thediagnostic mode (SO = H, SI = L). Taking SI high andLEDBO low will verify that the EDAC will correct the dataword. Also, the error syndrome code can be verified bytaking OECS low. It should be noted that only the 'ALS632Aand 'ALS633 are capable of this pass through verificationof the diagnostic data word. The 'ALS634 and 'ALS635do not have the output data latch required to perform thisfunction.16-BIT SYSTEMS USING THE ALS632A SERIES EDACsThe 'ALS632A series EDACs can reduce the memorysize required in 16-bit systems where conventional 16-bitEDACs (6 check bits, 16 data bits) are presently used.Figure 5 shows the typical system architecture for the16-bit EDAC. In this system, 88 devices would be requiredfor the 22-bit X 256K memory array, assuming 64K DRAMsare used. It is easy to see that 27.3%, or 24 devices, areSo)14--thIS)--+!'1 ,.1I -------------------;1Sl-.J : IIIOBOTHRU DB7 ---< INPUTDBS THRU DB15J+--READ _14 CORRECT _'" WRITEI OUTPUT CORRECTED DATA WORD IDA+ WORD ~ »») ( INPUT MODIFIED BYTE 0INPUT DATA WORDIOUTPUT CORRECTED DATA WORDIDB16 THRU DB23INPUT DATA WORDOUTPUT CORRECTED DATA WORDDB24 THRU DB31INPUT DATA WORDOUTPUT CORRECTED DATA WORDOEBILEDBO "l"'~~ ......11~ ______________________ ~:------------~r-1~ __________________ ~+:----------------~r-I~ ____________________ ~I----------~ri4--tsu(2)---+I"jf-tsu(3)";~.....,~~~~~ ...... ~.....,~~~~~ ...... ~.....,~~~~~~~ W/#IM%II/I/////1//4: ~I.-t..--.l :OECB--------------~I 1 r-------~ _________________________________ ~I-------------~--~JCBO THRU CB6 INPUT CHECK WORD OUTPUT SYNDROME CODE OUTPUT CHECK WORD\~ ________ ~V~A~LI~D~ER~R~F~L~AG~ _______ _J7\~_____V~A~L~ID~M~E~RR~FL~A~G ____J7Figure 3. Read-Modify-Write Operation3-56

equired for storing the check bits. When using the'ALS632Aseries EDACs, the memory required for the check bits canbe reduced to 17.9%, or only 14 devices. This reduces thetotal number of DRAMs required by 10 devices. Figure 6shows the architecture when using the 32·bit EDAC. Thefour 'LS646s are used to group two 16·bit data words intoone 32-bit data word. In addition, this type of system canbe used in byte-write operations where the other systemcannot.soSIDBO THRU DB31r'suIS'l .~------------------~I------~IINPUT VALID DATA WORDIt+-'h(101~I I ,INPUT DIAGNOSTIC DATA WORDOUTPUT DIAGNOSTICDATA WORDOEBO _______ -!' ____________________ ...,It-____ --t ________ -;i I 'd;s~!-__________________ ~i----------~r-----I ''"17I--1o:.I--~.II4-.- .... 1-.... 141: j+-'Pd-.tTHRU! I, IICEil I iLEDBO ________ ~:--------------------~i--___!~I--I~------~i~------------~~I--------____________ __i : i+-+-'h(121---1t+-'SU(61+'h(111~ : i.--'Pd4CBOTHRUCB6OUTPUT VALID CHECK WORDOUTPUT SYNDROME CODEi'~~~~~~~U~~'~------~:~----~------~'---------------------------------'d-;S~~~I:: Ii+--'pd-+\I I .~'Pd~ ______________________________ _ERR --1--- \ VERIFY PROPER OPERATION OF ERR FLAG I VERIFY PROPER OPERATION OF ERR FLAG,FLAG SHOULD BE LOW__-+-__ ~--I '-___ .2'!;.A.!!.~~~ !.E.!!I~~ ____ JWITH A DIAGNOSTIC DATA WORD WITH ASINGLE ERROR__ ~~ __.!I/4--.p d-.t_________________________________MERR _________--1 \.. ~:F~ j!£~~ ~6~~E~ ~~~R~::~ j '--___ V_E_R..;.I~;...~T;...P~;...~;.;PD;...ErA...;8;...~..;.~R;;.;s~...;~C;.;I?,;...~;...~A..;..F W;...M O;;.;E~.;.;;~..;.~;...~:..;.:;..;.A;.;F~;.;~..;..3_~~_EO_~_kR_D O;...B~_L_O_W ____L16-BITCPUFigure 4. Diagnostic Mode Timing Diagram'LS630~ I 1).... '6 ...l/L-IY-A/"- '"/ ~~16 "Figure S. 16-Bit System using Conventional 16-Bit EDACMEMORY22-BIT WIDE B Y 256K DEEPMEMORY FORCHECK-BITS6 X4 (64K DRAMs)NORMAL 16-BITMEMORY16 X 4 (64K DRAMs)TOTAL MEMORY: 88 DEVICES..... enoa.Q)ex:£:o",tjCO.saQ.a.«3-57

'LS646'ALS632ASERIESMEMORY3S-BIT WIDE BY 256K DEEPMEMORY FORCHECK·BITS7 X 2 (64K DRAMs)16-BITCPU'LS64632·BITMEMORY32 X 2 (64K DRAMs)TOTAL MEMORY: 78 DEVICESFigure 6. 16-Bit System using 32·Bit EDAC3-58Texas Instruments reserves the right to make changes at any time in order to improve design and to supply the best product possible.Texas Instruments assumes no responsibility for infringement of patents or rights of others based on Texas Instruments applications assistance or productspecifications, since TI does not possess full access to data concerning the use or applications of customer's products. TI also assumes no responsibilityfor customer product designs.

MEMORY MAPPING USING SN54/74LS610 THRU SN54/74LS613AuthorThomas J. TysonCon tribu torsDeene Ogden, Jim Gallia and Dennis FraileyLow Power Schottky Applications GroupINTRODUCTIONMicroprocessors, due to the advent of high density semiconductormemories (Le., 64K or larger), are being usedmore and more in systems featuring memory structureslarger than 64K bytes. The majority of the microprocessorsin use or available today have a 16-bit address bus, with amaximum addressing capability of 64K words. Due to thislimitation, some sort of memory mapping is necessary toadapt these microprocessors to applications where large.memory structures are required.The memory mappers (SN54/74LS610 throughSN54/74LS613) from TI were designed to alleviate thisaddressing limitation. These devices employ a paged memorymapping technique in expanding the system memory addressbus by 8 bits, thus effectively increasing the systemaddressing capability by a factor of 2 8 or 256. For microprocessorswith a 16-bit address bus (such as the Z-80, the8085 and the 6800), this results in an increase in themaximum addressing capability from 64K bytes to 16Mbytes and for the TMS9900 (which has a IS-bit addressbus), the result is an increase from 32K words to 8M words(word = 2 bytes).In the mapping operation, the four MSBs of themicroprocessor address word are used to access one of thesixteen 12-bit registers of the memory mapper's 16 X 12-bitRAM array. Each mapper register is capable of holding a12-bit address which will be termed the page address andwill be used as the 12 MSBs of the memory address bus.The remaining 12 bits (11 in the case of the TMS9900) ofthe microprocessor address bus will be transferred directlyto memory from the microprocessor and will be used toaddress the memory locations within each page. (SeeFigure 1)The memory will be organized into 2 x pages (where xequals the number of bits of the page address) with 2 n - 4words or bytes (where n is the bit length of the microprocessoraddress bus) per page. Once loaded, the mappercan access only 16 pages or 64K bytes (32K words in theTMS9900 case). In order to access more pages, the memorymapper RAM array must be reloaded with 16 new pageaddresses. This is done by the microprocessor via the databus with the mapper in the WRITE mode. (A more detaileddescription of the modes of operation will be given later inthis report.)FUNCTIONAL DESCRIPTIONA functional block diagram of the SN54/74LS61Omemory mapper, which consists mainly of: a 4-bit 2-to-lmultiplexer, a 16 X 12-bit RAM array, a 12-bit 2-to-lmultiplexer, 24 3-state buffers, control logic and in the caseof 'LS610 and 'LS611, a 12-bit transparent latch, as shownin Figure 2. Table I lists the functional differences betweenthe 'LS61O, 'LS611, 'LS612, and 'LS613. Table II lists thefunction of each pin.Depending on the state of the input control signals(i.e., CS,IIR/W, STROBE, MM, and ME), the mapper can beoperated in three basic modes of operation, I/O (READor WRITE), MAP and PASS. An explanation of each modeand the control signals necessary to achieve that mode ofoperation is given below: (Refer to Table III)Input/Output ModeIn this mode a page address can be loaded eitherinto a mapper register or can be read from a memorymapper register depending on the state of the R/W (READ/WRITE) input. This input signal controls either the READor WRITE function of the I/O Mode.WRITE ModeOne of the sixteen 12-bit registers is loaded with apage address via the DO-Dll I/O ports from the microprocessor.The address of the selected register is inputtedvia the RSO-RS3 inputs and is usually the four LSBs of themicroprocessor address word. The chip select (CS), thestrobe (STROBE) and R/W controls should all be low......ena..oC.Q)a:c:o.~CO.2C.c.«3-59

TMS9900ADDRESSBUSMEMORYMAPPERREGISTERFILEMEMORYADDRESSBUS4·MSBs4,,..MAO-MA316 X 12RAMARRAY121,MOO-M01111·MSBsI, 11..Figure 1. Mapping OperationMMcMOO-M07 LOW4cs1 "'0-3'»'C"2-c:;Q)r+C)":::s::xJCD'Cor+ "'"CJ). D (0·11)12DIN16 X 12RAMARRAYViiDOUT12ADDRFigure 2. Logic Diagram of the Memory Mapper 'LS61 03-60

Table I. Device ComparisonMap Outputs MapDevice Latched Output TypeSN54/74LS610 Yes 3-StateSN54/74LS611 Yes Open~ollectorSN54/74LS612 No 3-StateSN54/74LS613 No Open~ollector, READ ModeThe contents of one of the sixteen 12-bit registers isread from the mapper via the DO-Dll I/O ports_ As in theWRITE mode, the mapper register is selected by the addresson the RSO-RS3 inputs. Again chip select (CS) should below, while the R/W should be kept high.MAP ModeThe contents of one of the sixteen 12-bit memorymapper registers is outputted to the system address bus viathe MOO-MOll outputs. The address on MAO-MA3 selectsthe mapper register and is usually the four MSBs of themicroprocessor address word. The chip select (CS) mustbe inactive (high), the map mode (MM) control and themap enable (ME) must both be active (low). The n-4LSBs, where n equals the microprocessor address bit length,of the microprocessor address bus will be transferred directlyto memory from the microprocessor, white the remaining12 MSBs of the system address bus will be driven onto thebus by the memory mapper.Table II. Pin FunctionsPin Pin Name Functional Description7-12 DO thru 011 I/O connections to data and control bus used for reading from and writing to29-34 the map register selected by RSO-RS3 when CS is low. Mode controlled by RtW.(DO corresponds to MOO and is the most significant bit.)36,38,1,3 RSO thru RS3 Register select inputs for I/O operations. (RS3 is the least significant bit.)6 RNi Read or write control used in I/O operations to select the condition of the databus. When high, the data bus outputs are active for reading the map register.When low, the data bus is used to write in~o the register.5 'STFiOBE Strobe input used to enter data into the selected map register during I/Ooperations.4 Cs Chip select input. A low input level selects the memory mapper (assuming morethan one used) for an I/O operation.35,37,39,2 MAO thru MA3 Map address inputs to select one of 16 map registers when in map mode (MM lowand CS high). (MA3 is the least significant bit.)14-19 MOO thru MOll Map outputs. Present the map register contents to the system memory address22-27 bus in the map mode. In the pass mode, these outputs provide the map addressdata on M08-MOll and low levels on MOO-M07. (MOll is the leastsignificant bit.)13 MM Map mode input. When low, 12 bits of data are transferred from the selectedmap register to the map outputs. When high (pass mode), the four bits presenton the map address inputs are passed to the map outputs.21 ME Map enable for the map outputs. A low level allows the outputs to be active whilea high input level puts the outputs at high impedance.28 C Latch enable input for the 'LS610 and 'LS611 (no internal connection for 'LS612and 'LS613). A high level will transparently pass data to the map outputs. A lowlevel will latch the outputs.40,20 VCC' GNO Power supply (5 V) and network ground (substrate) pins....(/).....oCoQ)a::t:o.';:CO.sac.Co

Table III. Modes of OperationMAPPER 1/0INPUTS WRITE (LOAD) READ (VERIFY) MAP PASSCs Active (Low) Active (Low) Inactive (High) Inactive (High)STfi'5B'E Active (Low) Don't Care Don't Care Don't CareR!W Low High Don't Care Don't CareMM Don't Care Don't Care Active (Low) Inactive (High)ME Inactive (High) Inactive (High) Active ActiveRSO-RS3 Address of Address of Don't Care Don't CareSelected Register Selected RegisterMAO-MA3 Don't Care Don't Care Address of Address ofSelected Register Selected RegisterMOO-MOll High Impedance High Impedance Valid Address Valid Address00-011 Register contents Register contents Input Mode Input Modeto be loaded (input) to be read (output)»"'C"E..0"0)r+0":::s:lJCD"'Co...r+enPASS ModeThe four LSBs (M08-MOlI) of the memory mapperaddress bus (MOO-MOll) will be the same as the addresson the MAO-MA3 input bus, while the remaining eightMSBs. of the memory mapper address bus will all be low.The chip select (CS) and the map mode (MM) should boththe inactive (high); map enable (ME) should be active. Inother words, the address on the system address bus will bethe same as the address outputted by the microprocessor,and the memory mapper becomes transparent to the system.SYSTEMS INTEGRATIONThe flexibility of the memory mapper is such that itcan be used with microprocessors that have either an 8-bitor· a 16-bit data bus. In order to use the memory mapperto its fullest potential (Le., expand the address bus by eightbits) with an 8-bit microprocessor, the 12-bit page addressmust be multiplexed into the mapper via the 8-bit data bus.This means that the time it normally takes to load or readthe memory mapper will be at least doubled and extraexternal circuitry will be necessary. If the requirement ofthe system is such that the address bus needs to be increasedby only four bits, then there is no need for multiplexing inthe page address. Of course this means that the address busis expanded to only 20 bits resulting in a I-megabyteaddressing capability. Next in this report, we wi1llook attwo 8-bit systems utilizing the 'LS612 memory mapper.TMS9995-Based SystemFigure 3 shows a TMS9995-based system using the'LS612 to expand the address bus by four bits. TheTMS9995 is an 8-bit microprocessor with a 16-bit addressbus. This system employs the Programmable SystemInterface (TMS990 1) to control the operation of the mapper.The control of the mapper is software programmable viathe I/O ports of the TMS9901. Since the mapper registersare viewed as part of the logical memory space, an addressdecode (ADO) of the 12 MSBs is gated with a CRU bit toselect the mapper for a READ or WRITE operation. Thespecific mapper register is then selected by the four LSBs ofthe microprocessor address bus (AI5-AI2) via the RSO-RS3inputs of the mapper. Table IV shows the state of the threecontrol signals PO, PI and ADO and the correspondingmode of operation of the mapper. When placed in the I/Omode, the READ or WRITE operation is then controlledby memory signals from the microprocessor (Le., WE/CRUCLK, MEMEN, and DB IN). On POWER-UP andRESET, the I/O ports of the '9901 are put into the inputmode. The pull-up resistors Rl and R2 will ensure themapper is placed in the pass mode during POWER-UP andRESET. The resultant address bus is 20 bits wide, andSA19 is the LSB.l-80-Based SystemFigure 4 shows another 8-bit (l-80-based) systemusing the TI memory mapper. In this case, the control ofthe mapper is implemented by two flip-flops feeding MMand CS. These flip-flops are programmed by the l-80 andare addressed by the data bus, 00-01. Table V shows thenecessary states of DO and 01 to set the mapper in itsproper mode of· operation. Again during POWER-UP orRESET, the flip-flops are both cleared by RST, which issupplied by the system and which puts the mapper in thepass mode.Table IV. TMS9900j'LS61O Control SignalsMEMORY MAPPERCONTROL SIGNALSMODE OF OPERATION P1 PO ADOMAP L H LPASS H H LI/O H L L3-62

VCC(---.-...... CRU,-----.. ClKCRU......-------+----1 IN CRUOUTCRUINA15-AO1/6'lS04114'lS08()A15TMS9901PSIcsAD1ADDRESSDECODEA9-AO, 1015 ... ,SO-S4A14-A10,R2PO~-__ ---------~P1~~----------~• R1( VCCADOADDRESSDECODEA11-AO16 1 1---,1--i~ __ -+ _____ "'----:f-::ol---

A12· / ..MAO-MA3'41/6 'LS04~D1'01in -.- J 1/4 1/2'LSOS'LS74ADOrVCCXRsTb---

-------------------~g~~~--------------_M~~~~----------~~~UTMS9901PSIcs SO-54 PO( .~A14-A105AD1(ADDRESSDECODEP1~------~------------------------'R1 : 1KR2: 1KADDRESSDECODE1/6'lS04ADO~ VCC114'lSOOCRU CRU CRUClK OUT IN•7.. A9-A3A10-AO11 .. ""15 I15/ 8 .. _ 4 .. A14-A11A14-AO ~----~,~----------~--------~----~~---4~--~--~I-f-----~M RS3-RSO, ,MM(cs14~ A3-AOMA3-MAO16 ..12,r00-011 M-----,f---------------~----~~------------~~------------~ 00-011I,.DBIN ~----------------~--~------_+------------------------------~~WE ~----------~~--~--~------_+------------------------------~~ "RIWSTROBEMEMEN ~------..,TMS9900Another point worth noting is that in all three of thepreviously mentioned systems, the ME input was alwaysconnected to ground_ This caused the mapper addressbuffers to be enabled during all modes of operation of themapper_ This is only a problem during the I/O mode where,when loading the mapper register, other memory locationsare also being written into_ The method used to avoiddestroying data already in memory was to put the mapperinto the pass mode during the I/O operation_ This wasaccomplished simply by pulling MM input high, thusm:lking the system address equal to the microprocessoraddress.16 .. 1-- 1~~ 1~ ...00-015 SA22-SA12 SA11-SA10MEMORY8MEGAWORDSFigure 5. TMS9900 with Memory Mapperr--------t M011-MOOSN54n4lS612Multimapper SystemsIn a system employing a single memory mapper, themaximum active addressing capability is only 16 pages, ifincreased addressing capabilities are needed, the mappermust be reloaded_ To avoid this procedure, another mappermay be added to the system_ This will not increase theoverall addressing capability of the system, but it willdouble the amount of active pages and will also affordtwice the active addressing· capability _ Even though thecontrol of two mappers is a little more detailed than thecontrol of one, the same basic methods employed in thesystems with one mapper can be used here_•... en-oc.(1)a:c:o"';:;CO"~C.c.«3-65

TIMINGThe subject of how the mapper affects the criticaltiming parameters of the memory READ/WRITE cyclesand what changes, if any, are needed to accommodate themapper, have not been discussed in this report. First,looking at the I/O mode of operation where the mapperregisters are either loaded or read from, it is seen that themapper registers can be regarded as standard commonI/O, static RAMs, with maximum access times (RS to validMO, TA = 25°C, CL = 50 pF, Vee = 5 V) of 75 ns. Oncethe I/O mode is set (CS = low), the only two signalsnecessary to read or write into the mapper are STROBEand R/W. As shown in the previously mentioned system,these signals were supplied directly from the microprocessorwith no wait states necessary to perform eitherfunction. This will be the case with most microprocessors.In the MAP and PASS mode, the main concern isthe maximum access time (MA to MO). This access time isspecified at a maximum of 70 ns, which, depending on thetiming of the microprocessor and the memory used, mayormay not cause any problems. In the Z-80-based system, nowait states were introduced by the mapper because thememory control signals become active 95 ns after themicroprocessor address bus became valid. This gives theaddress bus sufficient time to settle down.In conclusion, it can be said that for most microprocessorsand memory available at the time of this writing,the operation of the mapper does not adversely affect thememory cycle timing and is flexible enough to be used withalmost all microprocessors.SUMMARYThe possible uses of the memory mapper and thevarious techniques that can be employed to control itsoperation are numerous and only some examples wereshown in this report. Some of the other possible applicationsof the mapper include: (1) achieving system addressingcapability greater than 16 megabytes is accomplished byreducing the number of mapper registers used by a factorof 2, thus increasing the size of each page by the samefactor of 2 without affecting the total amount of pages;(2) being used in systems employing DMA; (3) memoryprotection which can be accomplished by sacrificing oneor two bits of the page address, and gating these bits withthe memory control signals.Another technique that may be employed incontrolling the modes of operation of the mapper is to usePROMs.»'C'2.C:;"Q)r+0":::l::cCD'Co...r+t/)3-66Texas Instruments reserves the right to make changes at any time in order to improve design and to supply the best product possible.Texas Instruments assumes no responsibility for infringement of patents or rights of others based on Texas Instruments applications assistance or productspecifications, since TI does not possess full access to data concerning the use or applications of customer's products. TI also assumes no responsibilityfor customer product designs.

Bit .. Slice Processor Applications. 8-Bit FamilyFrank Laczko, Bob Myers, Richard Nawrocki,Rick Noblitt, and Sally TowlenVLSI Systems Engineering214/9954720TEXASINSTRUMENTS...f/)+'"oc.Q)a:co0';:coo~C.c.«3-67

IMPORTANT NOTICETexas Instruments (TI) reserves the right to make changes in thedevices or the device specifications identified in t,his publicationwithout notice. TI advises its customers to obtain the latest versionof device specifications to verify, before placing orders, that theinformation being relied upon by the customer is current.In the absence of written agreement to the contrary, TI assumes noliability for TI applications assistance, customer's product design, orinfringement of patents or copyrights of third parties by or arising fromuse of semiconductor devices described herein. Nor does TI warrantor represent that any license, either express or implied, is grantedunder any patent right, copyright, or other intellectual property rightof TI covering or relating to any combination, machine, or process inwhich such semiconductor devices might be or are used.Copyright © 1985. Texa!; Instruments Incorporated3-68

ContentsTitleSection 1IntroductionINTRODUCTION ............................................. '................................. 3-73Section 22910 Microprogram Controller Emulation Using the ' AS890 Microse~uencer2910 MICROPROGRAM CONTROLLER EMULATION USING THE 'AS890 MICRO SEQUENCER ....... 3-75Emulator Configuration ................................................................... :.. . 3-75Microinstruction Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-752910 Emulation Differences .......... ,. . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. .. . 3-75Loop Counts ............................................................... : . . . . . . . . . . . . . . 3-75Register Loading .......................................................................... 3-76Stack Full Indication ............. , ................... ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76Data Path Widths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76Section 3Minimum Cycle Time Delay Calculations for a 16-Bit SystemMINIMUM CYCLE TIME DELAY CALCULATIONS FOR A 16-BIT SySTEM........................ 3-9316-Bit Computer System Design ... : . . . . . . .. . . . . . . . . ... . . . . . . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . .. ... . 3-93Benchmark I: Comparison of Am2903A/291OA with 'AS888-1I'AS890-1 ........................... 3-94Benchmark II: Comparison of Am2901C/291OA with 'AS888-1I'AS890-1........................... 3-94Summary of Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-94Section 432-Bit CPU Design with the ' AS8881' AS89032-BIT CPU DESIGN WITH THE 'AS8881' AS890 ................................................. . 3-101Designing a 32-Bit System .................................................................... . 3-101Construction of the ALU ................................................................... . 3-101Construction of the CCU ..........................................'......................... . 3-103Tracing Through a 32-Bit Computer ............................................................. . 3-104Defining the Macrocode Instruction Format ...................................................... . 3-107Tracing. a 'Macrocode Instruction ......................................... '.' .................... . 3-107System Enhancements: ....................................................................... . 3-109Timing and System Throughput ......... : ..................................................... . 3-111Fetch Analysis .............................................................................. . 3-111Multiplication Analysis ....................................................................... . 3-111Section 5An A~aptive Clock Generator to Increase ' AS888 System SpeedAN ADAPTIVE CLOCK GENERA TOR TO INCREASE 'AS888 SYSTEM SPEED ..................... .Circuit Description .......................................................................... . 3-113 a:PROM Program ............................................................................ . 3-113 C0"';:;CO"~C.Q.«Page3-113..., tn0Q.Q)3-69

Section 6Floating-Point System Design Using the ' AS888/' AS890FLOATING-POINT SYSTEM DESIGN USING THE' AS888/' AS890 ................................. .Step 1: Choose a Floating-Point Number System ................................................. .Step 2: Choose an Algorithm for Sin(x) ........................................................ .Step 3: Make 'AS888 Register Assignments ..................................................... .Step 4: Substitute Registers for Variables in the Algorithm ........................................ .Step 5: Decompose Steps in the Algorithm into Simple Operations .................................. .Step 6: Translate into 'AS888/890 Instructions; Identify Subroutines ................................. .Step 7: Expand Subroutines into' AS888/890 Operations .......................................... .Floating-Point Multiplication ................................................................ .Floating-Point Addition .................... " ...... " ............................... " ..... .Step 8: Evaluate Trade-Offs and Block Diagram the Hardware ..................................... .Step 9: Define Microinstruction Fields During Detailed Hardware Design ............................ .Step 10: Assemble the Microprogram .......................................................... .List of Illustrations3-1253-1253-126. 3-1263-1273-1273-1283-1293-1293-1313-1333-1343-134Figure2-1 2910 Emulator Block Diagram .................... '" ................................. , ... .3-1 16-Bit Computer System ....................................................... : ......... .3-2 Am2903-Based 16-Bit Computer System ................................................... .3-3 'AS888-Based 16-Bit Computer System .................................................... .3-4 ALU Path for Multiplication and Division in the Am2903A System ............................. .3-5 ALU Path for Multiplication and Division in the 'AS888 System .........'...................... .3-6 Am2901C-Based 16-Bit Computer System .................................................. .3-7 Modified Design of Am290 1 C-Based System ................................................ .4-1 System Design Approach ................................................................ .4-2 CCU Block Diagram ..................................................'.................. .4-3 ALU Block Diagram .................................................................... .4-4 Cascaded' AS888 Packages .............................................................. .5-1 Adaptive Clock Generator Circuit ......................................................... .5-2 Adaptive Clock Generator Timing Diagram ................................................. .5-3 Propagation Delay Without Carry and Without Shift ......................................... .5-4 Propagation Delay Without Carry and With Shift ............................................ .5-5 Propagation Delay With Carry and Without Shift ............................................ .5-6 Propagation Delay With Carry and With Shift ............................................... .5~ 7 PROM Data .........................'.................................................. .6-1 Block Diagram of Floating-Point Processor ....................................'............. .TItlePage3-763-933-973-983-983-993-993-1003-1013-1023-1023-1033-1143-1153-1183-1193-1203-1213-1243-134List of ProgramsProgram2-1 Logic Equations Used to Generate Emulator PAL 1 .......................................... .2-2 Expanded Product Terms, Symbol Table and Fuse Plot for Emulator PAL 1 : .................... .2-3 Simulation Results for Emulator PAL 1 .................................................... .2-4 JEDEC Printout for Emulator PAL 1 ............................................... " ..... .2-5 Logic Equations Used to Generate Emulator PAL 2 .......................................... .2-6 Expanded Product Terms, Symbol Table and Fuse Plot for Emulator PAL 2 ..................... .2-7 Simulation Results for Emulator PAL 2 .................................................... .2-8 JEDEC Printout for Emulator PAL 2 ...................................................... .5-1 BASIC Program to Generate PROM Data .................................................. .TitlePage3-783-793-823-833-843-853-883-913-1223-70

Table2-12-22-33-13-23-33-43-53-63-73-83-93-104-14-24-34-44-54-64-74-84-94-104-115-15-25-76-1List of TablesTitleTypical Switching Characteristics ......................................................... ., AS890 Encodings for Am2910 Instructions ................................................. .Effect of Table 2-2 Encodings on ' AS890 Control Signals ..................................... .Am2903AI Am2910A Timings for Addition ................................................. ., AS888-1!' AS890-1 Timings for Addition ........................... ; ...................... .Am2903AIAm291OA Timings for Addition with Shift ........................................ ., AS888-1!' AS890-1 Timings for Addition with Shift ......................................... .Am2903AIAm291OA Timings for Multiplication ............................................. .Am2903AIAm291OA Timings for Division ................................................. ., AS888-1!' AS890-1 Timings for Multiplication and Division ................................... .Am2901C/Am291OA Timings for Addition ................................................. .Am2901C/Am291OA Timings for Addition with Shift ........................................ .Summary of Results .................................................................... .Microcode Definition ................................................................... .Functional Listing of Fetch .............................................................. .Assembler Listing of Fetch .............................................................. .Microcode Listing of Fetch .............................................................. .Possible Instruction Formats ............................................................. .Functional Listing of Multiply ............................................................ .Assembler Code of Multiply ............................................................. .Microcode Listing of Multiply ............................................................ .Critical Delay Path Analysis ............................................................. .Fetch Timing Comparison ............................................................... .Multiply Timing Comparison ............................................................. ., AS888-1 Timing Characteristics .......................................................... .Shift and Carry as a Function of I7-IO ..................................................... .PROM Data ........................................................................... .Floating Point Sin(x) Microprogram ....................................................... .Page3-753-773-773-943-943-953-953-953-953-963-963-963-963-1053-1063-1063-1073-1073-1073-1083-1093-1103-1103-1103-1153-1163-1233-135...,...tnoc.Q)a:c:o"';::;CO"~Q.c.«3-71

3-72

Section 1IntroductionBit-slice technology has gained widespread acceptanceamong CPU designers over the past several years as a meansof increasing system speed and reducing the discrete logicneeded for CPU construction. TI's recent entries on themarket, the SN74AS888 8-bit processor slice and itscompanion microsequencer, the SN74AS890, increaseprocessing throughput per unit area to an extent never beforerealized in bit-slice systems, making them well suited to theconstruction of high-speed systems with flexible instructionsets.This is the first in a series of application booksaddressed to users ofTI's bit-slice products. It discusses waysto take advantage of the 'AS888/ 'AS890's increased speedin the areas of CPU design and floating point processing,compares, their performance with similar products, andpresents a means of achieving optimum speed by adding anadaptive clock circuit to an 'AS888/ 'AS890 system. Alsoincluded is a 2910 emulator, which allows users to takeadvantage of the 'AS890's increased speed and greatlyexpanded addressing range, while still retaining existing 2910software. Brief abstracts of the papers in this volume aregiven below.Section 2, "2910 Microprogram Controller Emulationusing the 'AS890 Microsequencer," converts the 16instructions of the 2910 into 'AS890 commands, usingprogrammable array logic (PALs) for fast emulation. Byusing the emulator, accessible microcode store can bequadrupled from 4,096 to 16,384 memory locations, andadvantage can be takcn of the 'AS890's deeper stack.Section 3, "Minimum Cycle Time Delay Calculationsfor a 16-Bit System," examines some timings for systemsusing TI's 'AS888-1!'AS890-1, AMD's Am2901C/291OA,and AMD's Am2903A/291OA. Four cases are considered:addition, addition followed by a shift of the result, unsignedinteger mUltiplication and unsigned integer division.Section 4, "32-Bit CPU Design with the'AS888/ 'AS890," takes a look at constructing a centralprocessing unit by cascading four 'AS888s to form a 32-bitALU and the 'AS890 sequencer to address a control storecontaining the system microcode. Microcode and assemblycode are given for an instruction fetch routine and forunsigned multiplications.Section 5, "An Adaptive Clock Generator to Increase, AS888 System Speed, " uses an adaptive circuit to generateclock pulses for an 'AS888-based system. The clock cyclelength is optimally matched to the propagation delay of the'AS888 for each individual instruction, further increasingthe speed of the system. The circuit is linked to the 'AS888with a PROM that decodes 888 instructions into cyclelengths. A BASIC program calculates instruction lengths andgenerates a file that can be transmitted to a Data 110 PROMprogrammer.Section 6, "Floating Point Design using the'AS888/'AS890," provides a model for floating point systemdesign, illustrating the step by step development of a utilityto compute sin(x). By developing a sin(x) algorithm, amicroprogram is generated and hardware requirements areidentified in an interactive manner.The application notes in this volume werc prepared bythe following members of VLSI Systems Engineering:Bob Myers (Sections 3 and 4)Richard Nawrocki (Section 2)Rick Noblitt (Sections 5 and 6)Please contact the authors at 214/995-4720 if you need •additional information. '...., en~oc.Q)a:co",tjCO"~C.c.

3-74

Section 22910 Microprogram Controller Emulation using the 'AS890 MicrosequencerThe 'AS890 microsequencer, with its powerfulinstruction set, can be microprogrammed to emulate thepopular 2910 microprogram controller. By converting the16 instructions of the 2910 into the appropriate 'AS890commands, 2910 users can both quadruple accessiblemicrocode store from 4,096 to 16,384 memory locations andtake advantage of the 'AS890's deeper stack, while retainingexisting microprograms and preserving prior investments insoftware without loss of system performance. ProgrammableRead Only Memory (PROM) can be used to implement thesystem, or TI's Programmable Array Logic PAL® can beselected for faster emulation.EMULATOR CONFIGURATIONThe DRB inputs of the 'AS890 are used as the 2910emulator's D (direct data) inputs. JSRP and JRP (2910instructions 5 and 7) conditionally select the counter/register,requiring the counter/register contents to be available throughthe Y-output multiplexer. The 'AS890 does not directlysupport this function, but it can be accomplished by enablingeither the DRA or DRB ports as an output and selecting theappropriate path through the Y -multiplexer.JSRP and JRP also require that direct data input andexisting register/counter contents be available at the Ymultiplexer concurrently. The emulator uses direct data portDRA and register/counter A for this purpose. Two '74AS244buffers are used to isolate DRA from DRB so thatregister/counter A can be loaded from the Direct Data inputand DRA can be used to send the register/counter's contentsto the Y -multiplexer.Figure 2-1 shows the configuration of the 2910emulator. To provide fast propagation delays, twoTIBPAL16L8-15s, with a maximum propagation delay of15 ns, are used for the control PALs. Because theTIBPAL16L8-15 will only accommodate seven productSET-UP AND HOLD TIMESTable' 2-1. Typical Switching Characteristicsterms and eight were required for the condition code inputto the 'AS890, it is driven by two outputs of the control PAL.These outputs are selectively enabled using the CCEN input(see Programs 2-1 and 2-5 for detailed PAL equations).Typical switching delays for the 2910 emulator aresummarized in Table 2-1.MICROINSTRUCTION CONVERSIONTable 2-2 lists Y-multiplexer, stack and register controlencodings that can be used to convert the 2910 instructionset into 'AS890 microinstructions. The effect of theseencodings on the Y -multiplexer, stack and register controlsis shown in Table 2-3. Data from Table 2-2 was used as inputto a universal program logic compiler to produce theemulator's two control PALs. Files generated for each PALby the compiler include:1. a logic description file2. a listing of expanded product terms and fusemap3. simulation results4. a JEDEC file.These are reproduced at the end of this application note.The CUPLTM software used to develop the PALs is availablefrom Texas Instruments or from Assisted Technology, Inc.,San Jose, CA.2910 EMULATION DIFFERENCESThe architecture of the ' AS890 does not lend itself toa complete emulation of the 2910 controller. Differences arenoted below.Loop CountsThe 2910 register/counter is tested for a zero valueprior to decrementing and branching on conditional loops.The counter is usually loaded with a value that is one lessCOMBINATIONAL DELAYSFROMPL,MAPINPUT Ts Th Y VECT FULLD .... R (Inst. = 5,7) 15 0 DO-D13 (lnst. = 5,7) 15D .... R (lnst. f. 5,7) 8 0 DO-D13 (lnst. f. 5,7) 8D .... Pc (lnst. = 5,7) 28 0 10-13 (lnst. = 5,7,9) 27 10D .... Pc (lnst. f. 5,7) 20 0 10-13 (lnst. f. 5,7,9) 22 1013-10 36 0 CC 22CC 36 0 CCEN 22CCEN 36 0 CP 18 25CI 12 0 CP (I = 8,9,F & CNTR = 2) 24 25RLD 36 0 OE 8TO....en...oa.Q)a:co.~CO.2Q.a.«3-75

D-5TIBPAL16L8-15DRBINTRBOEVOERAOESN74AS890ZERONCCCB3-BOOSELTIBPAL16L8-15t-___ R_C-=2=--_RC_O=--___ -i RC2-RCO CKINCv1/674AS04CICPvFigure 2-1. 2910 Emulator Block Diagramthan the desired loop count. The 'AS890 tests for a one priorto decrementing. Therefore, the 2910 emulator requires thatthe actual loop count, rather than loop count minus one, beloaded into the register/counter.Three of the 2910 instructions (RFCT, RPCT, andTWB) execute once and terminate the counter decrementwhen a zero is found in the register/counter. The emulatorrequires a one in the register/counter to execute theseinstructions and terminate the counter decrement. Loadinga zero into the register/counter before decrementing willcause the emulator to loop 16,384 times.Register LoadingUsing the 2910's register load (RLD) input during aJSRP or JRP instruction allows external data to be input tothe register/counter while the current value in theregister/counter is output on the Y -bus. This is not the casewith the 'AS890, where an external value placed on DRAfor input to the register/counter will also be sent to the Y-multiplexer outputs. A register load using the emulator musttherefore be implemented independently of the JSRP or JRPinstructions.Stack Full IndicationThe 'AS890 stack is nine levels deep, compared to the2910's five-level stack. The 2910 signals that all five levelsof the stack are used by setting FULL low. The emulator'sFULL signal is set to zero when its eighth stack location isused, indicating that only one location remains available. Alow value will also appear at the FULL output when a stackPOP is to be executed and the stack is empty.Data Path WidthsBecause the 'AS890 supports 14-bit data paths insteadof the 2910's 12-bit paths, the number of address locationsthat can be accessed by the emulator can be expanded from4,096 to 16,634 locations.PAL is a registered trademark of Monolithic Memories Inc.3-76

Table 2-2. 'AS890 Encodings for Am2910 InstructionsCCEN = LOW and CC = HIGH CCEN = HIGH or CC = LOW13-10 MNEMONIC NAME CCOUT RC S MUX CCOUT RC S MUX0 JZ JUMP ZERO H LLL LLL HHH H LLL LLL HHH, CJS COND JSB PL H LLL HLH HHH L LLL HLH HHH2 JMAP JUMP MAP H LLL HHH HLL H LLL HHH HLL3 CJP COND JUMP PL H LLL HHH HHH L LLL HHH HHH4 PUSH PUSH/COND LD CNTR H LLL HHL HHH H LHL HHL HHH5 JSRP COND JSB R/PL L LLL HHL HLL H LLL HHL HLL6 CJV COND JUMP VECTOR H LLL HHH HHH L LLL HHH HHH7 JRP COND JUMP R/PL L LLL HHH HLL H LLL HHH HLL8 RFCT RPT LOOP, CNTR *" 0 L LLH LHL LLH L LLH LHL LLH9 RPCT RPT LOOP, CNTR *" 0 L LLH HHH HLL L LLH HHH HLLA CRTN COND RTN H LLL LHH LHH L LLL LHH LHHB CJPP COND JUMP PL & POP H LLL LHH HHH L LLL LHH HHHC LDCT LD CNTR 7 CONTINUE H LHL HHH HHH H LHL HHH HHHD LOOP TEST END LOOP L LLL LHL LHH H LLL LHL LHHE CONT CONTINUE H LLL HHH HHH H LLL HHH HHHF. TWB -THREE-WAY BRANCH L LLH LHL LHH H LLH LHL LHHENABLEPLPLMAPPLPLPLVECTPLPLPLPLPLPLPLPLPLTable 2-3. Effect of Table 2-2 Encodings on 'AS890 Control SignalsCCEN = LOW and CC = HIGH CCEN = HIGH or CC = LOW13-10 MNEMONIC NAME ZERO CCOUT RC S MUX CCOUT RC S MUX0 JZ JUMP ZERO H Hold Reset 0 H Hold Reset 01 CJS COND JSB PL H Hold Hold MPC L Hold Push DRB2 JMAP JUMP MAP H Hold Hold DRB H Hold Hold DRB3 CJP COND JUMP PL H Hold Hold MPC L Hold Hold DRB4 PUSH PUSH/COND LD CNTR H Hold Push MPC H LoadA Push MPC5 JSRP COND JSB R/PL L Hold Push DRA H Hold Push DRB6 CJV COND JUMP VECTOR H Hold Hold MPC L Hold Hold DRB7 JRP COND JUMP R/PL L Hold Hold DRA H Hold Hold DRB8 RFCT RPT LOOP, CNTR *" 09 RPCT RPT LOOP, CNTR *" 0L L DecA Hold STK L DecA Hold STKH L DecA Pop MPC L DecA Pop MPCL L DecA Hold DRA L DecA Hold DRAH L DecA Hold MPC L DecA Hold MPCA CRTN COND RTN H Hold Hold MPC L Hold Pop STKB CJPP COND JUMP PL & POP H Hold Hold MPC L Hold Pop DRBC LDCT LD CNTR 7 CONTINUE H LoadA Hold MPC H LoadA Hold MPCD LOOP TEST END LOOP L Hold Hold STK H Hold Pop MPCE CO NT CONTINUE H Hold Hold MPC H Hold Hold MPCL L DecA Hold STK H DecA Pop MPCF TWB THREE-WAY BRANCHH L DecA Pop DRB H Hold Pop MPCENABLEPLPLMAPPLPLPLVECTPLPLPLPLPLPLPLPLPLPLPLPL(J).....a..oC.Q)a:c::o0';:;COo~C.c.

Program 2-1. Logic Equations Used to Generate Emulator PAL 1•CUPl VERSION 2.02A COPYRIGHT (c) 1983.84.85 ASSISTED TECHNOLOGY.SOURCE FILE: B:2910EM1 :2 :3:4:5:6:7:8:9:10:11:12:13:14:15:16:17:18:19:20:21:22:23:24:25:26:27:28:29:30:31:32:33:34:35:36:37:38:39:40:41:42:43:44:45:46:47:48:49:50:51:52:53:54:55:56:PARTNONAMEDATEREVDESIGNERCOMPANYASSEMBLYLOCATIONDEVICE: p16L82910EM ;'74AS890/2910 EMULATOR PAL 104/04/85 ;01 ;RICHARD D. NAWROCKITEXAS INSTRUMENTS00001 ;U100 :INC. -- LISTING/******************************************************************//* *//* THIS DEVICE GENERATES CONTROL SIGNALS FOR THE '74AS890 *//* E~ULATION OF THE 2910 MICROPROGRAM CONTROLLER. *//* *//* ALLOWABLE TARGET DEVICE TYPES: PAL16l8A *//******************************************************************//** INPUTS **/PIN [1. .4] = [10 .. 3] /* 2910 INSTRUCTION CODEPIN 5 = RlD /* 2910 REGISTER LOAD/** OUTPUTS **/PIN 19 RAOE . /* 74AS890 ORA OUTPUT ENABLEPIN [18 .. 16] [MUXO .. 2]: /* 74AS890 MUX_Y CONTROLPIN [15 .. 13] [SO •• 2] /* 74AS890 STACK CONTROLPIN 12 EN244 /* 74AS244 OUTPUT ENABLES/** DECLARATIONS AND INTERMEDIATE VARIABLE DEFINITIONS **/FIELD INSTRUCTIONFIELD STACKFIELD LMUX/** LOGIC EQUATIONS[13 .. 0][S2 .. 0][MUX2 .. 0]**/!RAOE INSTRUCTION:[5.71 & RLD ;!E~244STACKY_MUXINSTRUCTION:[0 .. 4.6.8 .. F] # (INSTRUCTION:[5.7] & !RLD)INSTRUCTION:1 & 'H'~# INSTRUCTION:[2.3.6.7.9.C.E] & 'H'7# INSTRUCTION:[4.5] & 'H'6# INSTRUCTION:[8.D.Fl & 'H'2# INSTRUCTION: [A.Bl & 'H'3 ;INSTRUCTION:[0,1,3.4,6.B.C.E] & 'H'7# INSTRUCTION:[2.5.7.9] & 'H'4# INSTRUCTION:8 & 'H'1# INSTRUCTION: [A.D.F] & 'H'3 ;*/*/*/*/*/*/JEDEC FUSE CHECKSUM (7103)JEDEC TRANSMIT CHECKSUM(259E)3-78

Program 2-2. Expanded Product Terms, Symbol Table and Fuse Plot for Emulator PAL 1CUPlDEVICEPARTNONAMEREVISIONDATEDESIGNERCOMPANYASSEMBLYlOCATION2.D2Ap16L8 DlIB-c-18-52910EM'74AS890/291D EMULATOR PAL 10104/04/85RICHARD D. NAWROCKITEXAS INSTRUMENTS00001UIOOEXPANDED PRODUCT TERMSEN-244 -)13# 112 & 113# 110 & 12 & 113# 10 & 12 & 113 & IRlDINSTRUCTION -)13 ,12 ,I! ,10MUXQ-)IO & 12 & 113# 110 & 11 & 112 & 113# 10 & III & 112 & 13MUXI -)10 & 12 & 113# III & 112 & 13# 110 & 11 & 112 & 113MUX2 -)110 & 112 & 13# 10 & 12 & 13RAOE -)10 & 12 & 113 & RlDSO -)10 & I I! & 12# 110 & III & 113# 10 & 12 & 13# 110 & III & 112Sl -)II! & 112 & 113S2 -)I! &! 12 & 13# 110 & III & 112# 10 & 12 & 13STACK -)S2 ,Sl ,SOLMUX -)MUX2 ,MUXI ,MUXDEN-244.0E -)1MUXD.OE -)1MUXl.OE -)1MUX2.0E -)1RAOE.OE -)1SO.OE -)1Sl.OE -)1S2.0E -)1f/)....-oc.(1)a:c:o.';:CO.20.c.

Program 2-2. Expanded Product Terms, Symbol Table and Fuse Plot for Emulator PAL 1 (Continued)SYMBOL TABLEPOL NAME EXT PIN TYPE USED MAXEN-244 12 V 4 710 1 VIl 2 V12 3 V13 4 V1 NSTRUCTI ON 0 FMUXO 18 V 3 7MUXI 17 V 3 7MUX2 16 V 2 7RAOE 19 V 1 7RLD 5 VSO 15 V 4 7Sl 14 V 1 7S2 13 V 3 7STACK 0 FY_MUX 0 FEN-244 OE 12 D 1 1MUXO OE 18 D 1 1MUXI OE 17 D 1 1MUX2 OE 16 D 1 1RAOE OE 19 D 1 1SO OE 15 D 1 1S1 OE 14 D 1 1S2 OE 13 D 1 1LEGEND D DEFAULT VAR F FIELD 1 INTERMEDIATE VARU UNDEFINED V VAR X EXTENDED VARN NODE M EXTENDED NODElEI ===============================================================================FUSE PLClT=============================================================================::=» PIN #191j 0000 --------------------------------~ 0032 --x-x----x--x------------------O· 0064 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx~ 0096 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxr+ 0128 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxS· 0160 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx~ 0192 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx~ 0224 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx{g P6~5~1~ _______________________________o 0288 --x-x----x----------------------~ 0320 x--x-x---x----------------------o 0352 -xx--x--x-----------------------0384 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0416 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0448 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0480 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx3-80PIN #170512 --------------------------------0544 --x-x----x----------------------0576 -x---x--x-----------------------0608 x--x-x---x-~--------------------0640 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0672 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0704 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0736 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxPIN #160768 --------------------------------0800 ---x-x--x-----------------------0832 --x-x---x-----------------------0864 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0896 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0928 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0960 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0992 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

Program 2-2. Expanded Product Terms, Symbol Table and Fuse Plot for Emulator PAL 1 (Continued)PIN #151024 --------------------------------1056 -xx-x---------------------------1088 -x-x-----x----------------------1120 --x-x---x-----------------------1152 -x-x-x-----~--------------------1184 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1216 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1248 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxPIN #lLt1280 --------------------------------1312 -x---x---x----------------------1344 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1376 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1408 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1Lt40 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1472 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1504 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxPIN #131536 --------------------------------1568 x----x--x-----------------------1600 -x-x-x---------------------~----1632 --x-x---x-----------------------1664 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1696 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1728 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1760 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxPIN #121792 ------------------------~-------1824 --------x-----------------------1856 -----x---x-----------~----------1888 ---xx----x----------------------1920 --x-x----x---x------------------1952 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1984 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx2016 xxxxxxx~xxxxxxxxxxxxxxxxxxxxxxxxLEGEND X FUSE NOT BLOWNFUSE BLOWNfJ)+J~oc.Q)a::s::o"';:;CO"~C.c.«3-81

12345678Program 2-3. Simulation Results for Emulator PAL 1NAMEDATEREVDESIGNERCOMPANYASSEMBLYLOCATION'74AS890/2910 EMULATOR PAL 1;04/04/85;01 ,RICHARD D. NAWROCKITEXAS INSTRUMENTS00001 ;UI00 ;9 /***********************************************************/10 /* THIS DEVICE GENERATES CONTROL SIGNALS FOR THE */11 /* '74AS890 EMULATOR OF THE 2910 MICROPROGRAM SEQUENCER. */12 /***********************************************************/1314 ORDER:15 13, %2, 12, %2, 11, %2, 10, %2,16 RLD, %2, RAOE, %2, EN-244, %2,17 MUX2, %2, MUXl, %2, MUXO, %2,18 S2, %2, S1, %2, SO ;19l>"C"CrrD)r+O·::s:tJCD"Cor+ "'"enSIMULATION RESULTS===============================================================================EENNI I3 2R M M MR A 2 U U U I L 0 X X X S S SODE 4 2 102 1 0INSTRUCTION 00001: 0 0 0 0 1 H L H H H L L L0002: 0 O' 0 0 0 H L H H H L L LINSTRUCTION 10003: 0 0 0 1 1 H L H H H H L H0004: 0 0 0 1 0 H L H H H H L HINSTRUCTION 20005: 0 0 1 0 1 H L H L L H H H0006: 0 0 1 0 0 H L H L L H H HINSTRUCTION 30007: 0 0 1 1 1 H L H H H H H H0008: 0 0 1 1 0 H L H H H H H HINSTRUCTION 40009: 0 1 0 0 1 H L H H H H H L0010: a 1 0 0 0 H L H H H H H LI NSTRUCTI ON 50011: 0 1 0 1 1 L H H L L H H L0012: 0 1 0 1 0 H L H L L H H LI NSTRUCTI ON 60013: 0 1 1 0 1 H L H H H H H H0014: 0 1 1 0 0 H L H H H H H HI NSTRUCTI ON 70015: 0 1 1 IlL H H L L H H H0016: 0 1 1 1 0 H L H L L H H HI NSTRUCTI ON 80017: 1 0 0 0 1 H L L L H L H L0018: 1 0 0 0 0 H L L L H L H LI NSTRUCTI ON 90019: 1 0 0 1 1 H L H L L H H H0020: 1 0 0 'I 0 H L H L L H H HI NSTRUCTI ON A0021: 1 0 1 0 1 H L L H H L H H0022: 1 0 1 0 0 H L L H H L H HI NSTRUCTI ON B0023: 1 0 1 1 1 H L H H H L H H0024: 1 0 1 1 0 H L H H H L H HINSTRUCTION C0025: 1 1 0 0 1 H L H H H H H H0026: 1 1 0 0 0 H L H H H H H HINSTRUCTION D0027: 1 1 0 1 1 H L L H H L H L0028: 1 1 0 1 0 H L L H H L H LI I3 2R M M MR A 2 U U U I L 0 4 X X X S S SODE 421 0 2 1 0INSTRUCTION E0029: 1 1 1 0 1 H L H H H H H H0030: 1 1 1 0 0 H L H H H H H HI NSTRUCTI ON F0031: 1 1 1 1 1 H L L H H L H L0032: 1 1 1 1 a H L L H H L H L3-82

Program 2-4. JEDEe Printout for Emulator PAL 1CUPLDEVICEPARTNONAMEREVISIONDATEDESIGNERCOMPANYASSEMBLYLOCATION*QP20*QF2048*GO*FO2.02Ap16L8 DLIB-c718-52910EM'74AS890/2910 EMULATOR PAL 10104/04/85RICHARD D. NAWROCKITEXAS INSTRUMENTS00001UI00*LOOOO 11111111111111111111111111111111*L0032 11010111101101111111111111111111*L0256 11111111111111111111111111111111*L0288 11010111101111111111111111111111*L0320 01101011101111111111111111111111*L0352 10011011011111111111111111111111*L0512 11111111111111111111111111111111*L0544 11010111101111111111111111111111*L0576 10111011011111111111111111111111*L0608 01101011101111111111111111111111*L0768 11111111111111111111111111111111*L0800 11101011011111111111111111111111*L0832 11010111011111111111111111111111*LI024 11111111111111111111111111111111*LI056 10010111111111111111111111111111*L1088 10101111101111111111111111111111*Ll120 11010111011111111111111111111111*L1152 10101011111111111111111111111111*L1280 11111111111111111111111111111111*L1312 10111011101111111111111111111111*L1536 11111111111111111111111111111111*L1568 01111011011111111111111111111111*L1600 10101011111111111111111111111111*L1632 11010111011111111111111111111111*L1792 11111111111111111111111111111111*L1824 11111111011111111111111111111111*L1856 11111011101111111111111111111111*L1888 11100111101111111111111111111111*L1920 11010111101110111111111111111111*C7103*VOOOI 00001XXXXNXLLLLHHHHN*V0002 OOOOOXXXXNXLLLLHHHHN*V0003 10001XXXXNXLHLHHHHHN*V0004 10000XXXXNXLHLHHHHHN*V0005 01001XXXXNXLHHHHLLHN*V0006 01000XXXXNXLHHHHLLHN*V0007 11001XXXXNXLHHHHHHHN*V0008 11000XXXXNXLHHHHHHHN*V0009 00101XXXXNXLHHLHHHHN*VOOI0 00100XXXXNXLHHLHHHHN*VOOll 10101XXXXNXHHHLHLLLN*V0012 10100XXXXNXLHHLHLLHN*V0013 01101XXXXNXLHHHHHHHN*Y0014 01100XXXXNXLHHHHHHHN*V0015 11101XXXXNXHHHHHLLLN*Y0016 11100XXXXNXLHHHHLLHN*V0017 000llXXXXNXLLHLLLHHN*Y0018 00010XXXXNXLLHLLLHHN*Y0019 10011XXXXNXLHHHHLLHN*Y0020 10010XXXXNXLHHHHLLHN*Y0021 01011XXXXNXLLHHLHHHN*Y0022 01010XXXXNXLLHHLHHHN*Y0023 11011XXXXNXLLHHHHHHN*Y0024 11010XXXXNXLLHHHHHHN*V0025 00111XXXXNXLHHHHHHHN*Y0026 00110XXXXNXLHHHHHHHN*V0027 10111XXXXNXLLHLLHHHN*Y0028 10110XXXXNXLLHLLHHHN*V0029 01111XXXXNXLHHHHHHHN*Y0030 01110XXXXNXLHHHHHHHN*V0031 11111XXXXNXLLHLLHHHN*Y0032 11110XXXXNXLLHLLHHHN*0757II(/).....,...oc.Q)a::t:o"';:COCJa.c.«3-83

IIProgram 2-5. Logic Equations Used to Generate Emulator PAL 2CUPL VERSION 2.02A COPYRIGHT (c) 1983,84,85 ASSISTED TECHNOLOGY,SOURCE FILE: B:2910EM11 :2:3:4:5:6:7:8:9:10:11:12:13:14:15:16:17:18:19:20:21:22:23:24:25:26:27:28:29:30:31:32:33:34:35:36:37:38:39:40:41:42:43:44:45:46:47:48:49:50:51:52:53:54:55:56:57:58:59:60:61:PARTNONAMEDATEREVDESIGNERCOMPANYASSEMBLYLOCATIONDEVICE: p16L82910EMl ;'74AS890/2910 EMULATOR PAL 204/04/85 ;01 ;RICHARD D. NAWROCKITEXAS INSTRUMENTS00001 ;UI0l ;INC. -- LISTING/*******************************************************************//* THIS DEVICE GENERATES CONTROL SIGNALS FOR THE '74AS890 *//* EMULATION OF THE 2910 MICROPROGRAM CONTROLLER. *//* *//* ALLOWABLE TARGET DEVICE TYPES: PAL16L8 , *//*******************************************************************//** INPUTS **/PIN [1 .. 4) [ 10 .. 3) /* 2910 INSTRUCTION CODE */PIN 5 RLD /* 2910 REGISTER LOAD */PIN 6 CC /* 2910 CONDITION CODE */PIN 7 CCEN /* 2910 CONDITION CODE ENABLE *//** OUTPUTS **/PIN 19 = CCOUTO /* 74AS890 CONDITION CODE (1 OF 2) */PIN 18 = ccoun /* 74AS890 CONDITION CODE (2 OF 2) */PIN [17 •. 15) [RC2.. 0)PIN 14 PL /* 2910 PIPELINE MAP OUTPUTPIN 13 MAP /* 2910 PROM MAP OUTPUTPIN 12 = VECT /* 2910 VECTOR MAP OUTPUT/** DECLARATIONS AND INTERMEDIATE VARIABLE DEFINITIONS **/FIELD INSTRUCTION = [13 .. 0)FIELD COUNTER [RC2 .. 01/** LOGIC EQUATIONS **/IPL INSTRUCTION:[O,1.3 .. 5,7 .. F)I MAPINSTRUCTION:2IVEeT = INSTRUCTION:6COUNTER = 'H'2 & INSTRUCTION:C# ('H'2 & INSTRUCTION:4 & (CCEN # ICC»# 'H' 2 & IRLD# 'H'l & RLD & INSTRUCTION:[8,9,F) ;CC_OUTO.OE = CCEN ;CC_OUTl.0E = ICCEN ;ICC_OUTO = INSTRUCTION:[1,3,6,8 .. B)ICC_OUTlINSTRUCTION:[l,3,6,8 .. B) & ICC# INSTRUCTION:[5,7,D,F) & CC# INSTRUCTION:[8,91 ;/* 74AS890 REGISTER/COUNTER CONTROL*/*/*/*/JEDEC FUSE CHECKSUM (791A)JEDEC TRANSMIT CHECKSUM (3521)3-84

Program 2-6. Expanded Product Terms, Symbol Table and Fuse Plot for Emulator PAL 2CUPlDEVICEPARTNONAMEREVISIONDATEDESIGNERCOMPANYASSEMBLYlOCATION2.02Ap16L8 DlIB-c-18-52910EMI'74AS890/2910 EMULATOR PAL 20104/04/85RICHARD D. NAWROCKITEXAS INSTRUMENTS00001UI0lCCOUTO -)!I2 & 13# 10 &! 12 &! 13# !IO & 11 & 12 & !I3CC_OUTO.OE -)CCENCCOUT! -)! CC &! 12 & 13#!I! & !I2 & 13# CC & 10 & 12# ICC & 10 & !I2 & !I3# ICC & !IO & 11 & 12 & !I3CCOUT!.OE -)!CCENCOUNTER -)RC2 • RCI ,RCOINSTRUCTION -)13 , 12 ,I! • 10MAP -)!IO & I! & !I2 & !I3Pl -)13# ! I! &! 13# 10 & II & !I3RCO -)!ID & Il# ! Il & 12# Il &! 12# ! 13# !RlDRC1 -)10 & RlD# ! 12 & RlD# 11 & RlD# !CCEN & CC & !13 & RLDRC2 -)1VECT -)!IO & 11 & 12 & !I3MAP.OE1-)PL. OE -)1EXPANDED PRODUCT TERMSRCO.OE-)1RCl.OE -)1RC2.0E -)1VECT.oE -)1111t/)~10.oCoQ)a:co.~«lUa.Co«3-85

Program 2-6. Expanded Product Terms, Symbol Table and Fuse Plot for Emulator PAL 2 (Continued)SYMBOL TABLEPOLNAMEEXTPINTYPEUSEDMAXCCENCCCCOUTOCCOUTOCCOUllCCOUllCOUNTER10Il1213INSTRUCTIONMAPPLRCORCIRC2RLDVECTMAPPLRCORCIRC2VECTOEOEOEOEOEOEOEOE76191918180123401314151617512131415161712VVXVXFVVVFVVVVVVVDDDDDD31511354111111117171777777111111LEGEND D DEFAULT VAR F FIELD I INTERMEDIATE VARU UNDEFINED V VAR X EXTENDED VARN NODE M EXTENDED NODEFUSE PLOT•PIN #190000 --------------------X-----------0032 -----X--X--------------.---------0064 --x--x---x----------------------0096 x--xx----x----------------------0128 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0160 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxl> 0192 xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xx0224 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"C PIN #18__ 0256 ---------------------x----------(5' 0288 -----x--x--------x--------------Q) 0320 -x---x--x-----------------------~ 0352 --x-x-----------x---------------g' g~~~ ;=~;;~==:~=======~==============0448 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx~ 0480 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxCD PIN #17"C 0512 --------------------------------() 0544 --------------------------------~ 0576 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxen 0608 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0640 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0672 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0704 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0736 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxPIN #160768 --------------------------------0800 --x---------x-------------------0832 -----x------x-------------------0864 x-----------x-------------------0896 ---------x--x---x----x----------0928 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0960 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0992 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXPIN #151024 --------------------------------1056 x--x----------------------------1088 -x--x-----------------~---------1120 x----x--------------------------1152 ---------x----------------------1184 -------------x------------------1216 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1248 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXPIN #141280 --------------------------------1312 --------x-----------------------1344 -x-------x----------------------1376 x-x------x----------------------1408 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1440 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1472 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1504 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx3-86

PIN #13Program 2-6. Expanded Product Terms, Symbol Table and Fuse Plot for Emulator PAL 2 (Continued)1536 --------------------------------1568 x--x-x---x----------------------1600 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1632 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1664 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1696 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1728 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1760 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxPIN #121792 --------------------------------1824 x--xx----x----------------------1856 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1888 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1920 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1952 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1984 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx2016 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxLEGEND x FUSE NOT BLOWNFUSE BLOWNtn.....oa.Q)a:c:o"';::CO"~C.a.

12345678910111213Program 2-7. Simulation Results for Emulator PAL 2NAMEDATEREVDESIGNERCOMPANYASSEMBLYLOCATION'74AS890/2910 EMULATOR PAL 204/04/85 ;01 •RICHARD D. NAWROCKITEXAS INSTRUMENTS00001 ;UI01 ;/***********************************************************//* THIS DEVICE GENERATES CONTROL SIGNALS FOR THE *//* '74AS890 EMULATOR OF THE 2910 MICROPROGRAM SEQUENCER. *//***********************************************************/14 ORDER:15 13.1617181920%2 , 12. %2. I L %2. 10, %2.CC. %2. CCEN, %2. RLD, %2,PL. %2, MAP, %2. VECT, %2.CC_OUTI. %2. CC_OUTO, %2.RC2, %2, RCl, %2. RCO ;=========~============================================ =========================SIMULATION RESULTS===============================================================================C C0001000200030004000500060007000800090010OOll001200130014001500160017001800190020002100220023002400250026002700280029003000310032V 0 0C R M E U U R R RI I ICELPACTTCCC3 2 0 C N D L P T 1 021 0INSTRUCTION 000001 OIL H H L L L001 0 0 L H 0 0 a OIL H H L L L0.0 0 0 0 L H. H H Z L H lo 0 0 0 1 IlL H H Z H L L L0 1 1 0 H 001 1 L o 0 0 0 0 1 0 L H H Z H L H LINSTRUCTION 000 OIL L 000 1 1 0 0 H H H Z H 000 100 1 H Z L 000 1 0 0 0 L H L Z H 00011 IlL H H Z L 00011 1 0 L H H Z H 00010 IlL L 00010 1 0 L H H Z L L H LINSTRUCTION 21 L o 0 1 0 1 0 0 H L H H Z L H L100 1 L 1 0 0 0 0 H Z H 0 101 1 L 01 0 1 0 H 0 100 1 L L L Lo 0 100 1 0 H L H Z H L H LI NSTRUCTI ON 3o 0 1 1 1 OIL H H H Z L L L001 1 1 0 0 L H H H Z L H Lo 0 1 100 1 L H H L Z L L Lo 0 1 100 0 L H H L Z L H L001 1 1 IlL H H Z L L L Lo 0 1 1 1 1 0 L H H Z L L H Lo 0 1 101 1 L H H Z L L L L001 101 0 L H H Z L L H L3-88

Program 2-7. Simulation Results for Emulator PAL 2 (Continued)C CC CC V 0 0C R M E U U R R RI I I I C E L P A C T T C C C3 2 1 0 C N D L P T 1 0 2 1 0I NSTRUCTI ON 40033 0 1 0 0 1 0 1 L H H H Z L L L0034 0 1 0 0 1 0 0 L H H H Z L H L0035 0 1 0 0 0 0 1 L H H H Z L H L0036 0 1 0 0 0 0 0 L H H H Z L H L0037 0 1 0 0 1 1 1 L H H Z H L H L0038 o . 1 0 0 1 1 0 L H H Z H L H L0039 0 1 0 0 0 1 1 L H H Z H L H L0040 0 1 0 0 0 1 0 L H H Z H L H LI NSTRUCTI ON 50041 0 1 0 1 1 0 1 L H H L Z L L L0042 0 1 0 1 1 0 0 L H H L Z L H L0043 0 1 0 1 0 0 1 L H H H Z L L L0044 0 1 0 1 0 0 0 L H H H Z L H L0045 0 1 0 1 1 1 1 L H H Z H L L L0046 0 1 0 1 1 1 0 L H H Z H L H L0047 0 1 0 1 0 1 1 L H H Z H L L L0048 0 1 0 1 0 1 0 L H H Z H L H LI NSTRUCTI ON 60049 0 1 1 0 1 0 1 H H L H Z L L L0050 0 1 1 0 1 0 0 H H L H Z L H L0051 0 1 1 0 0 0 1 H H L L Z L L L0052 0 1 1 0 0 0 0 H H L L Z L H L0053 0 1 1 0 1 1 1 H H L Z L L L L0054 0 1 1 0 1 1 0 H H L Z L L H L0055 0 1 1 0 0 1 1 H H L Z L L L L0056 0 1 1 0 0 1 0 H H L Z L L H LINSTRUCTION 70057 0 1 1 1 1 0 1 L H H L Z L L L0058 0 1 1 1 1 0 0 L H H L Z L H L0059 0 1 1 1 0 0 1 L H H H Z L L L0060 0 1 1 1 0 0 0 L H H H Z L H L0061 0 1 1 1 1 1 1 L H H Z H L L L0062 0 1 1 1 1 1 0 L H H Z H L H L0063 0 1 1 1 0 1 1 L H H Z H L L L0064 0 1 1 1 0 1 0 L H H Z H L H LINSTRUCTION 80065 1 0 0 0 1 0 1 L H H L Z L L H0066 1 0 0 0 1 0 0 L H H L Z L H L0067 1 0 0 0 0 0 1 L H H L Z L L H0068 1 0 0 0 0 0 0 L H H L Z L H L0069 1 o· 1 L H H Z L L L H0070 1 0 0 0 1 1 0 L H H Z L L H L0071 1 0 0 0 0 1 1 L H H Z L L L H0072 1 0 0 0 0 1 0 L H H Z L L H L enINSTRUCTION 90073 1 0 0 1 1 0 1 L H H L Z L L H 00074 1 0 0 1 1 0 0 L H H L Z L H L 0.0075 1 0 0 1 0 0 1 L H H L Z L L H Q)0076 1 0 0 1 0 0 0 L H H L Z L H L a::0077 1 0 0 1 1 1 1 L H H Z L L L H0078 1 0 0 1 1 1 0 L H H Z L L H L t:0079 1 0 0 1 0 1 1 L H H Z L L L H 00080 1 0 0 1 0 1 0 L H H Z L L H L .+:iINSTRUCTION ACO0081 1 0 1 0 1 0 1 L H H H Z L L L .20082 1 0 1 0 1 0 0 L H H H Z L H L Q.0083 1 0 1 0 0 0 1 L H H L Z L L L0084 1 0 1 0 0 0 0 L H H L Z L H L 0.0085 1 0 1 0 1 1 1 L H H Z L L L L

Program 2-7. Simulation Results for Emulator PAL 2 (Continued)l>"C"ErrQ)....25":::::J::0~"C0....enC CC CC V 0 0C R M E U U R R RI I I I C E L P A C T T C C C3 2 1 0 C N D L P T 1 0 2 1 0I NSTRUCTI ON B0089 1 0 1 1 1 0 1 L H H H Z L L L0090 1 0 1 1 1 0 0 L H H H Z L H L0091 1 0 1 1 0 0 1 L H H L Z L L L0092 1 0 1 1 0 0 0 L H H L Z L H L0093 1 0 1 1 1 1 1 L H H Z L L L L0094 1 0 1 1 1 1 0 L H H Z L L H L0095 1 0 1 1 0 1 1 L H H Z L L L L0096 1 0 1 1 0 1 0 L H H Z L L H LINSTRUCTION C0097 1 1 0 0 1 0 1 L H H H Z L H L0098 1 1 0 0 1 0 0 L H H H Z L H L0099 1 1 0 0 0 0 1 L H H H Z L H L0100 1 1 0 0 0 0 0 L H H H Z L H L0101 1 1 0 0 1 1 1 L H H Z H L H L0102 1 1 0 0 1 1 0 L H H Z H L H L0103 1 1 0 0 0 1 1 L H H Z H L H L0104 1 1 0 0 0 1 0 L H H Z H L H LINSTRUCTION D0105 1 1 0 1 1 0 1 L H H L Z L L L0106 1 1 0 1 1 0 0 L H H L Z L H L0107 1 1 0 1 0 0 1 L H H H Z L L L0108 1 1 0 1 0 0 0 L H H H Z L H L0109 1 1 0 1 1 1 1 L H H Z H L L L0110 1 1 0 1 1 1 0 L H H Z H L H L01ll 1 1 0 1 0 1 1 L H H Z H L L L0112 1 1 0 1 0 1 0 L H H Z H L H LI NSTRUCTI ON E0113 1 1 1 0 1 0 1 L H H H Z L L L0114 1 1 1 0 1 0 0 L H H H Z L H L0115 1 1 1 0 0 0 1 L H H H Z L L L0116 1 1 1 0 0 0 0 L H H H Z L H L0117 1 1 1 0 1 1 1 L H H Z H L L L0118 '1 1 1 0 1 1 0 L H H Z H L H L0119 1 1 1 0 0 1 1 L H H Z H L L L0120 1 1 1 0 0 1 0 L H H Z H L H LINSTRUCTION F0121 1 1 1 1 1 0 1 L H H L Z L L H0122 1 1 1 1 1 0 0 L H H L Z L H L0123 1 1 1 1 0 0 1 L H H H Z L L H0124 1 1 1 1 0 0 0 L .H H H Z L H L0125 1 1 1 1 1 1 1 L H H Z H L L H0126 1 1 1 1 1 1 0 L H H H L H L0127 1 1 1 1 0 1 1 L H H Z H L L H0128 1 1 1 1 0 1 0 L H H Z H L H L3-90

Program 2-8. JEDEC Printout for Emulator PAL 2CUPLDEVICEPARTNONAMEREVISIONDATEDESIGNERCOMPANYASSEMBLYLOCATION*QP20*QF2048*GO*FO2.02Ap16L8 DLIB-c-18-52910EM1'74AS890/2910 EMULATOR PAL 20104/04/85RICHARD D. NAWROCKITEXAS INSTRUMENTS00001U101*LOOOO 11111111111111111111011111111111*L0032 11111011011111111111111111111111*L0064 11011011101111111111111111111111*L0096 01100111101111111111111111111111*L0256 11111111111111111111101111111111*L0288 11111011011111111011111111111111*L0320 10111011011111111111111111111111*L0352 11010111111111110111111111111111*L0384 11011011101111111011111111111111*L0416 01100111101111111011111111111111*L0512 11111111111111111111111111111111*L0544 11111111111111111111111111111111*L0768 11111111111111111111111111111111*L0800 11011111111101111111111111111111*L0832 11111011111101111111111111111111*L0864 01111111111101111111111111111111*L0896 11111111101101110111101111111111*LI024 11111111111111111111111111111111*LI056 01101111111111111111111111111111*LI088 10110111111111111111111111111111*L1120 01111011111111111111111111111111*L1152 11111111101111111111111111111111*L1184 11111111111110111111111111111111*L1280 11111111111111111111111111111111*L1312 11111111011111111111111111111111*L1344 10111111101111111111111111111111*L1376 01011111101111111111111111111111*L1536 11111111111111111111111111111111*L1568 01101011101111111111111111111111*L1792 11111111111111111111111111111111. *L1824 01100111101111111111111111111111*C791A*VOOOI 0000110XXNXHHLLLLHZN*V0002 0000010XXNXHHLLHLHZN*V0003 0000100XXNXHHLLLLHZN*V0004 OOOOOOOXXNXHHLLHLHZN*V0005 0000111XXNXHHLLLLZHN*V0006 0000011XXNXHHLLHLZHN*V0007 0000101XXNXHHLLLLZHN*V0008 0000001XXNXHHLLHLZHN*V0009 1000110XXNXHHLLLLHZN*VOOI0 1000010XXNXHHLLHLHZN*V0011 1000100XXNXHHLLLLLZN*V0012 1000000XXNXHHLLHLLZN*V0013 1000111XXNXHHLLLLZLN*V0014 1000011XXNXHHLLHLZLN*V0015 1000101XXNXHHLLLLZLN*V0016 1000001XXNXHHLLHLZLN*V0017 0100110XXNXHLHLLLHZN*V0018 0100010XXNXHLHLHLHZN*V0019 0100100XXNXHLHLLLHZN*V0020 0100000XXNXHLHLHLHZN*V0021 0100111XXNXHLHLLLZHN*V0022 0100011XXNXHLHLHLZHN*V0023 0100101XXNXHLHLLLZHN*V0024 0100001XXNXHLHLHLZHN*V0025 1100110XXNXHHLLLLHZN*V0026 1100010XXNXHHLLHLHZN*V0027 1100100XXNXHHLLLLLZN•til.......,oa.Q)a:co.~CO.~C.a.«3-91

Program 2-8. JEDEC Printout for Emulator PAL 2 (Continued)*V0028 1100000XXNXHHLLHLLZN*V0029 1100lllXXNXHHLLLLZLN*V0030 11000llXXNXHHLLHLZLN*V0031 1100lOlXXNXHHLLLLZLN*V0032 110000lXXNXHHLLHLZLN*V0033 OOlOllOXXNXHHLLLLHZN*V0034 OOlOOlOXXNXHHLLHLHZN*V0035 OOlOlOOXXNXHHLLHLHZN*V0036 OOlOOOOXXNXHHLLHLHZN*V0037 OOlOlllXXNXHHLLHLZHN*V0038 OOlOOllXXNXHHLLHLZHN*V0039 OOlOlOlXXNXHHLLHLZHN*V0040 OOlOOOlXXNXHHLLHLZHN*V0041 lOlOllOXXNXHHLLLLLZN*V0042 lOlOOlOXXNXHHLLHLLZN*V0043 lOlOlOOXXNXHHLLLLHZN*V0044 lOlOOOOXXNXHHLLHLHZN*V0045 lOlOlllXXNXHHLLLLZHN*V0046 lOlOOllXXNXHHLLHLZHN*V0047 lOlOlOlXXNXHHLLLLZHN*V0048 lOlOOOlXXNXHHLLHLZHN*V0049 OllOllOXXNXLHHLLLHZN*V0050 OllOOlOXXNXLHHLHLHZN*V0051 OllOlOOXXNXLHHLLLLZN*V0052 OllOOOOXXNXLHHLHLLZN*V0053 OllOlllXXNXLHHLLLZLN*V0054 OllOOllXXNXLHHLHLZLN*V0055 OllOlOlXXNXLHHLLLZLN*V0056 OllOOOlXXNXLHHLHLZLN*V0057 1110llOXXNXHHLLLLLZN*V0058 11100lOXXNXHHLLHLLZN*V0059 1110lOOXXNXHHLLLLHZN*V0060 1110000XXNXHHLLHLHZN*V0061 1110lllXXNXHHLLLLZHN*V0062 11100llXXNXHHLLHLZHN*V0063 1110lOlXXNXHHLLLLZHN*V0064 111000lXXNXHHLLHLZHN*V0065 OOOlllOXXNXHHLHLLLZN*Y0066 OOOlOlOXXNXHHLLHLLZN*Y0067 OOOllOOXXNXHHLHLLLZN*V0068 OOOlOOOXXNXHHLLHLLZN*V0069 OOOllllXXNXHHLHLLZLN*Y0070 OOOlOllXXNXHHLLHLZLN*Y0071 OOOllOlXXNXHHLHLLZLN*Y0072 OOOlOOlXXNXHHLLHLZLN*Y0073 lOOlllOXXNXHHLHLLLZN*V0074 lOOlOlOXXNXHHLLHLLZNI*V0075 lOOllOOXXNXHHLHLLLZN*Y0076 lOOlOOOXXNXHHLLHLLZN*Y0077 lOOllllXXNXHHLHLLZLN*Y0078 lOOlOllXXNXHHLLHLZLN*Y0079 lOOllOlXXNXHHLHLLZLN~ *Y0080 lOOlOOlXXNXHHLLHLZLN~ *V0081 OlOlllOXXNXHHLLLLHZN~ *Y0082 OlOlOlOXXNXHHLLHLHZN__ *Y0083 OlOllOOXXNXHHLLLLLZNc;" *Y0084 OlOlOOOXXNXHHLLHLLZNQ) *Y0085 OlOllllXXNXHHLLLLZLN~ *V0086 OlOlOllXXNXHHLLHLZLN(5" *V0087 OlOllOlXXNXHHLLLLZLN:l *Y0088 OlOlOOlXXNXHHLLHLZLN*V0089 110lllOXXNXHHLLLLHZN~ *Y0090 110lOlOXXNXHHLLHLHZNCD *Y0091 110llOOXXNXHHLLLLLZN1j *Y0092 110lOOOXXNXHHLLHLLZN() *Y0093 110llllXXNXHHLLLLZLN~ *Y0094 110lOllXXNXHHLLHLZLNen *Y0095 110llOlXXNXHHLLLLZLN*V0096 110lOOlXXNXHHLLHLZLN*Y0097 OOllllOXXNXHHLLHLHZN*Y0098 OOllOlOXXNXHHLLHLHZN*V0099 OOlllOOXXNXHHLLHLHZN*YOIOO OOllOOOXXNXHHLLHLHZN*YOIOI OOlllllXXNXHHLLHLZHN*YOI02 OOllOllXXNXHHLLHLZHN*VOI03 OOlllOlXXNXHHLLHLZHN*YOI04 OOllOOlXXNXHHLLHLZHN*VOI05 lOllllOXXNXHHLLLLLZN*YOI06 lOllOlOXXNXHHLLHLLZN*YOI07 lOlllOOXXNXHHLLLLHZN*YOI08 lOllOOOXXNXHHLLHLHZN*YOI09 lOlllllXXNXHHLLLLZHN*YOIIO lOllOllXXNXHHLLHLZHN*YOlll lOlllOlXXNXHHLLLLZHN*YOl12 lOllOOlXXNXHHLLHLZHN*YOl13 OlllllOXXNXHHLLLLHZN*YOl14 OlllOlOXXNXHHLLHLHZN*VOl15 OllllOOXXNXHHLLLLHZN*YOl16 OlllOOOXXNXHHLLHLHZN*VOl17 OllllllXXNXHHLLLLZHN*YOl18 OlllOllXXNXHHLLHLZHN*VOl19 OllllOlXXNXHHLLLLZHN*V0120 OlllOOlXXNXHHLLHLZHN*Y0121 1111110XXNXHHLHLLLZN*Y0122 11110lOXXNXHHLLHLLZN*Y0123 1111100XXNXHHLHLLHZN*V0124 1111000XXNXHHLLHLHZN*Y0125 lllllllXXNXHHLHLLZHN*Y0126 11110llXXNXHHLLHLZHN*V0127 111110lXXNXHHLHLLZHN*V0128 111100lXXNXHHLLHLZHN*A1283-92

Section 3Minimum Cycle Time Delay Calculations for a 16-Bit SystemThis article examines some timings for a typical 16-bitcomputer system using a bit-slice processor andmicro sequencer. Comparative data for systems using TI's'AS888-lI'AS890-1, AMD's Am2901C/291OA, and AMD'sAm2903A/291OA are presented. Timing calculations arebased on data from TI SN74AS888/890 family data sheetsand from the AMD2900 Family Bipolar MicroprocessorLogic and Interface 1985 Data Book.16-BIT COMPUTER SYSTEM DESIGNFigure 3-1 shows a basic design for a 16-bit computersystem. The computer control unit (CCU), shown on the leftside of the dotted line, executes microcode from themicroprogrl!!)1 memory (also known as the control store).A one-level pipeline design is used to speed data processing,allowing the address and contents of the next instruction tobe fetched' while the current instruction is being executed.The arithmetic logic unit, consisting of the bit-slice processorchips and any other logic needed to process the data, is shownon the right side of the figure.This section compares the time required to perform thefollowing functions, using TI's SN74AS888-1/890-1,AMD's Am2901C/291OA and AMD's Am2903A1291OA bitsliceproducts:1. addition2. addition with a shift3. unsigned integer mUltiplication4. unsigned integer division.Cases 3 and 4 are not included in the Am2901 C/ Am2910Adiscussion, since the Am2901C does not incorporate internalmUltiplication or division algorithms.IMICROPROGRAMMEMORYr-p PIPELINE REGISTERI-lr16·BIT ALUJMUX~ClK,SEQUENCERI-I4H DATAREGISTER1JI STATUSREGISTERI en+"'...oc.Q)a::c:o'';:;CO(.)C.c.

»Benchmark I: Comparison of Am2903A/2910Awith ' AS888-lI' AS890-1Design of a 16-bit system that is Am2903A-based ispresented in Figure 3-2. The same system implemented withthe 'AS888-1 and 'AS890-1 is shown in Figure 3-3. Thesesystems are used to calculate timings for the four casesdiscussed in this section. Timings for the control path aregiven in the first test case and remain constant for theremaining three cases.Tables 3-1 and 3-2 contain timing results for additionusing the two chip sets; Tables 3-3 and 3-4 analyze the addwith shift combination. It can be seen that the TI system runs36 % faster for addition and 32 % faster for addition followedby a shift of the result.Figures 3-4 and 3-5 show the ALU data paths used formultiplication and division by the two systems. Tables 3-5,3-6 and 3-7 display timings for the critical path calculationsfor these operations. Increases in speed using the TI partsare even more significant here, where mUltiplication is fasterby 42 % and division faster by 37 % .Benchmark II: Comparison of Am2901C/2910Awith ' AS888-lI' AS890-1The same 16-bit system can be constructed withAm2901C slices. Since the Am2901C has a smallerinstruction set than the Am2903A or the 'AS888-1,multiplication and division must be emulated using externaladd with shift hardware and bit testing. For this reason, thecomparison for this benchmark is restricted to the cases ofaddition and addition with shift.The basic system for these two cases using theAm2901C is shown in Figure 3-6; timing calculations forthe control and data paths are listed in Table 3-8. These canbe compared directly with the 'AS888 design and calculationsshown previously in Figure 3-3 and Table 3-2. Addition is13% faster using the AS888-1.To implement the shift function, two multiplexers andan exclusive-OR gate are needed. A modified design is shownin Figure 3-7, along with timing calculations in Table 3-9.A comparison of these with Figure 3-3 and data in Table3-4 shows that the TI system performs an addition with shift25% faster than the Am2901C equivalent."'C SUMMARY OF RESULTS"2.. Table 3-10 summarizes the timings of the various casesC:;" implemented with the TI and AMD parts. It can be seen thata the TI 'AS888-l/ 'AS890-1 system runs faster than the othersS· in all cases. Addition using the TI parts can be performed::l 26% faster than with the system using the Am2901C and::D 36% faster than that using the Am2903A. Addition with aCD"'Co""'Ir+enshift is 25% faster on the TI system than the Am2901Csystem and 32 % faster than the Am2903C. An even widervariance occurs with the more complicated algorithms:multiplication is 42 % faster using the TI chip; division is37% faster.Table 3-1. Am2903A/Am2910A Timings for AdditionTIMECOMPONENT DATA PATH INS)Data LoopPipeline register Clock to output 9Am2903A A, B toG,P 52Am2902A GO, PO to Cn+ z 7Am2903A Cn to Cn +4, OVR, Z, Y 35Am2903A Setup time 5Control LoopTotal for data loop10BPipeline register Clock to output 9MUX Select to output 13Am2910A CC to output 30PROM Access time 20Pipeline register Setup time 2Totai for control loop 74Critical path for Am2903 addition10BTable 3-2. 'AS888-1/'AS890-1 Timings for AdditionTIMECOMPONENT DATA PATH INS)Data LoopPipeline register Clock to output 9'ASBBS-1 A, B to Cn+8 30'ASSSS-1 Cn to Cn +8' OVR, Z, Y 27Register Setup time 2Control LoopTotal for data loop 68Pipeline register Clock to output 9MUX Select to output 13'AS890-1 CC to output 25PROM Access time 20Pipeline register Setup time 2Total Control Loop 69Critical 'path for 'AS8S8 addition 693-94

Table 3-3. Am2903A/Am2910A Timings forAddition with ShiftTable 3-5. Am2903A/Am2910A Timingsfor MultiplicationCOMPONENTDATA PATHTIMEINS)TIMECOMPONENT DATA PATH INS)Data LoopPipeline registerAm2903AAm2902AAm2903AAm2903AAm2903AClock to outputA, B toG,PGO, PO to Cn + zCn to Cn +4, SIOOSIO(n) shift to YRAM setupTotal for data loop952723235119Data LoopAm2918 Clock to output 27Am2903A 18-10 toG,P 71Am2902A GO, PO to Cn + z 7Am2903A Cn to Cn + 4, SIOO 23Am2903A SIOln) shift to Y 23Total for data loop 151Control LoopPipeline registerMUXAm2910APROMPipeline registerClock to output9Select to output13CC to output30Access time20Setup time2Total for control loop 74Control LoopPipeline register Clock to output 9MUX Select to output 13Am2910A CC to output 30PROM Access time 20Pipeline register Setup time 2Total for control loop 74Critical path for AM2903 additionwith shift119Critical path for Am2903 multiplication 151Table 3-4. 'AS888-1I'AS890-1 Timingsfor Addition with ShiftTable 3-6. Am2903AI Am2910A Timings for DivisionTIMECOMPONENT DATA PATH INS)Data LoopPipeline register Clock to output 9'AS888-1 A, B to Cn +8 30'AS888-1 Cn to Cn + 8, SIOO 25'AS888-1 SIO(n) shift to Y 14'AS888-1 Register file setup time 2Total for data loop 80TIMECOMPONENT DATA PATH (NS)Data LoopAm2918 Clock to output 27Am2903A 18-IOtoG,P 50Am2902A GO, PO to Cn+ z 7Am2903A Cn to,Cn +4, SIOO 32Am2903A SIO(n) shift to Y 23Total for data loop 139Control LoopPipeline register Clock to output 9MUX Select to output 13'AS890-1 CC to output 25PROM Access time 20Pipeline register Setup time 2Total for control loop 69Critical path for 'ASS88 addition with shift 80Control LoopPipeline register Clock to output 9MUX Select to output 13Am2910A CC to output 30PROM Access time 20Pipeline register Setup time 2Total for control loop 74Critical path for Am2903 division 139tJ).....-oc.Q)a:r:::o.+=iCO.2C.c.«3-95

Table 3-7. 'AS888-l/'AS890-1 Timings forMultiplication and DivisionTIMECOMPONENT DATA PATH (NS)Data Loop'AS888-1 Clock to Cn + 8 46'AS888-1 C n to SIO 25'AS888-1 SIO(n) shift to Y 14'AS888-1 Register file setup time 2Control LoopTotal for data loop 87Pipeline register Clock to output 9MUX Select to output 13'AS890-1 CC to output 25PROM Access time 20Pipeline register Setup time 2Critical path for 'AS888 multi'plicationTotal Control Loop 69or division 87Table 3-8. Am2901C/Am2910A Timings for AdditionTable 3-9. Am2901C/Am2910A Timings forAddition with ShiftTIMECOMPONENT DATA PATH (NS)Data LoopPipeline register Clock to output 9Am2901C A, B toG,P 37Am2~02A GO, PO to Cn+ z 7Am2901C C n to F3, OVR 22XOR and MUX 21Am2901C RAM3 setup 12Control LoopTotal for data loop 108Pipeline register Clock to output 9MUX Select to output 13Am2910A CC to output 30PROM Access time 20Pipeline register Setup time 2Critical path for Am2903 additionTotal for control loop 74with shift 108TIMECOMPONENT DATA PATH (NS)Data LoopPipeline register Clock to output 9Am2901C A, B toG,P 37Am2902A GO, PO to Cn + z 7Am2901C Cn to Cn +4, OVR, F3,F = 0, Y 25Register Setup time 2Total for data loop 80Control LoopPipeline register Clock to output 9MUX Select to output 13Am2910A CC to output 30PROM Access time 20Pipeline register Setup time 2Total for control loop 74Critical path for Am2901 C addition 80Table 3-10. Summary of ResultsCALCULATED TIMINGSDATA PATHS CONTROL PATHS SYSTEM CLOCKOperation Am2901C Am2903A 'ASS8S-1 Am2901C Am2903A 'ASS88-1 Am2901C Am2903A 'ASS88-1Addition 80 108 68 74 74 69 80 108 69Addition with Shift 108 119 80 74 74 69 108 119 80Multiplication - 151 87 - 74 69 - 151 87Division - 139 87 - 74 69 - 139 873-96

MICROPROGRAMMEMORYwcD......ClKApplication ReportsFigure 3-2. Am2903-Based 16-Bit Computer System

->MICROPROGRAM'AS888'AS888MEMORY (LSP) (MSP)cn +81 I CnPIPELINE REGISTERI-.-..r 4---I.~MUXI'-'AS890MICROSEQUENCER'---441IDATA REGISTER1~.1STATUS REGIST~R 11CLK»"C"En'0)r+0'~::xJCD"Co...r+enCLK/"Figure 3-3. 'AS888-Based 16-Bit Computer System--+Am2918r----tAm2903A

eLK >---------~----------------~r_------------------~'AS888(MSP)'AS888(LSP)en ...-----i en + 8SIOO r----iSI07Out15_8Figure 3-5 •. ALU Path for Multiplication and Division in the 'AS888 SystemMICROPROGRAMMEMORY1I•Am2901Cr-->PIPELINEREGISTER(LSP)Am2901C Am2901CA 1\ ALr---J. J.l t J..---:J L.-MUX ~:=- l.~I I~ Am2902Am2910A '---SEQUENCERI IIAm2901C(MSP)A~IJCLK+~~+r DATA REGISTER I1Figure 3-6. Am2901C-Based 16-Bit Computer System•STATUSREGISTERI..... en...o~Q)a:co".;:.CO"~c..~«3-99

Cf-'os~JodaMuo!~e:l!ldd"MICROPROGRAMMEMORYuXClKFigure 3-7. Modified Design of Am2901C-Based System

Section 432-Bit CPU Design With the l\S888/l\S890Microprogramming and bit slice technology have madepossible the development of powerful systems using flexibleinstructions sets and wide address/data buses to access morethan one gigaword of physical main memory. This sectiondiscusses one design approach to such a system, using'AS888 bit slice and 'AS890 micro sequencer components.A structured approach to system design, such as thatillustrated in Figure 4-1, is recommended in developingcustom bit-slice designs. The product specification gives astarting point or basis for the project. In this example, four'AS888 bit slices are used to implement the 32-bit arithmeticportion of the CPU, and an 'AS890 microsequencer is usedfor ALU and system control. A group of PROMs stores themicroinstructions; a writable control store could also beimplemented using additional control logic and componentsto load and modify the microprogram memory. The systemis designed to access more than one gigaword of memory.Since speed is a concern, carry look-ahead rather thanripple-through logic is recommended. If ripple-through logicwere used, t~e system clock would need to be slowed downto allow the propagation of the carry bits through the various'AS888 stages. By using carry look-ahead, the amount oftime needed for the data to stabilize is greatly reduced byanticipating the carry across the 'AS888 packages.So that the scratchpad area can be used for addresscalculations and mathematical computations, the 'AS888'sinternal register file is dedicated for system functions. Toprovide the system user with a'macrolevel equivalent ofregister locations, a 16-word external register file is alsoincluded. Access to the external register file is undermicroprogram control, allowing address selection to comefrom the microcode itself or from one of the three operandfields of the instruction register.PROMs eliminate the use of main memory as a sourcefor constants used in initialization or table look-up functions.Accessing main memory for table values would require timeand slow system throughput; by placing fixed values in fastPROMs, access time is kept to a minimum and systemthroughput is not altered.Control, data and address buses shared by the systemare accessed by three-state registers. The control registersupplies the non-CPU part of a computer system with controlsignals. The data bus allows the ALU to supply data for therest of the system and can also be a source of data for theALU; this is accomplished by using three-state registers todrive the bidirectional data bus, along with registers to samplethe bus. The address bus uses one of the external registerfile locations to maintain a program counter, thus allowinga 32-bit address bus capable of addressing about 4 gigawords[..--__ -,/ PRODUCT SPECIFICATION0-BLOCK DIAGRAM/MACRO INSTRUCTION FORMATSoICROMAP FOR DATA PATH CONTROL

14MICROPROGRAMMEMORY.--____-:.;M.:.:-IC:,:-R:.,:O---:C:.,:O:.:-N:,:-T.:-,;RO..,L=--::-BU:,;S:..-_______• TO FIGURE 4-3'AS888 STATUSTO c.,L.:.-..;~~-!.j (ON LSPITO~ ___.., R~~kS;ER1232 DATA BUS32 ADDRESS BUSCONTROL BUSFigure 4-2. CCU Block DiagramTO FIGURE 4-3TO FIGURE 4-3TO FIGURE 4-3...FROM FIGURE 4-2/ MICRO CONTROL BUS32 B BUS32 A BUS'AS888 STATUS4C > n1 321 1 132'AS888(4) II~ PROMALUI (SEE FIGURE 4-4)I32TRANSFERREGISTER74AS37314112 r 1-0F-2 SIS-WORD lTO REGISTER "- SELECTOR I 4 I REGISTER FILEFILES / 12 18 I 74ASI57(1) 74AS870(BIt4 32I3232 32FROM FIGURE 4-2/"32 DATA BUSFROM FIGURE 4-2 / 32 ADDRESS BUSr---r321 -321 32JDATA-INDATA-OUTMEMORYREGISTER REGISTER ADDRESS REGISTER74AS373(4) 74AS373(4) 74AS373(4)·1 rII I32 32 - 32Y BUS1FROM FIGURE 4-2 )>------.,C,..."O""'N""TR=-O=-L"""'B""U.,..,S,....---------------------:-----------Figure 4-3. ALU Block Diagram3-102

,132J'32B BUSA·BUS'" f- J~~r'" ~ I~ '"1f- j _... _t--=Z;.=E.:.;.R0=-t__-I ZE~~S888 t~ ZE~~S888~ -£ +5VpppjZE~~S888 CD _ ZE~~S888C n+ S SSF r--- SSF - SSF r-- SSF - r--.......;;..;..::...+-_-i'c.nn++ls ~f- _cn+s ~- _cn+s Cnl- _cn+s Cn_fr--SI07 SIOO SI07 SIOO SI07 Si60 SI07 SIOO _r 0107 0100 0107 0100 0107 0100 0107 ~OIQO lI~_..:;G:..;-P..J G P G P G P'-----t---t--t-----1llllI~~t::: i= «~ c~o zcIU 0UII74AS182LOOK·AHEADCARRY GENERATOR~~_~II~I I~~I ____ ~IP/OVRGINr--+--t---+-----I-------JI~n'32V·BUSFigure 4-4. Cascaded 1\S888 Packagesand QIOO terminals are connected to the SI07 and QI07terminals of adjacent packages, and the least significantpackage's signals are connected to the most-significantpackage's. Optionally, the SN74ALS240 inverting gates canbe connected to the S100-S107 terminals and the byte inputsto implement byte and bit controL Another chip, theSN74AS182 look-ahead carry generator, provides a ripplecarryfunction, to help system throughput.The design includes a 16-word register file, theSN74AS870 (see Figure 4-3). This allows the user to access16 working areas for temporary data storage or addresscalculations such as indexing. In this design example, the'AS888's internal register file is not accessible directly bythe user; it is reserved for microcode operations, such asaddress computation and temporary storage for arithmeticoperations. Addressing the register files is permitted throughthe microprogram or from the macrocode instruction registerunder microcode control. The transfer register connected tothe 'AS888's Y and DB buses allows for feedback into the'AS888 under microprogram control. Since the constantPROMs and the external register file share the A bus, theycannot be accessed at the same time. The transfer registerenables data from the external register file to be transmittedto the B bus, making possible the addition of operands fromthe constant PROMs and the external register file, forexample.Constant PROMs are also included to simplify theprogramming and operation of the ALU by supplying fixeddata for various operations, such as:1. Clearing the system register files forinitialization. This brings the system up to aknown state.2. Supplying a correction value to the offset in abranch instruction,i.e., converting a 16-bitoffset to a true 32-bit address.3. Table look-up for fixed mathematicaloperations, such as computing sines andcosines.Construction of the CCUSequencing and branching operations at speedscompatible with the 'AS888 are supplied by the 'AS890, amicroprogrammed controller working as a powerfulmicroseqtiencer. Features of the 'AS890 include:I. Stack capability. The 9-word stack can beaccessed by using a stack pointer or a readpointer; the latter is designed for nondestructivedumping of the stack contents.2. Register/counter facility. Two registers, DRAand DRB, can be used for latching data fromthe external data buses or as counters for loops.en~a..oC.Q)ex:co'';:CO.2C.c.«3-103

A ZERO signal is generated when thedecremented counter reaches a zero value.3. Interrupt control. A register for temporarilyholding the return address is supplied; uponentering the interrupt routine, the contents ofthe return register must be pushed onto the stackfor later use.4. Next address generation. The Y outputmultiplexer offers a selection of same orincremented address, address from DRA orDRB buses, address from stack, or aconcatenation of DRAI3-DRA4 and B3-BO.A microprogram memory/pipeline register supplies themicrosequencer and the rest of the system with instructions(see Figure 4-2). The memory might consist of ROMs, orit could be a writable-control store with support logic to allowloading or updating of the control store. For a generalpurpose machine with a fixed instruction set, ROMs wouldbe more economic.Some 'AS890 instructions are influenced by the CCinput. Many are variations of branch and jump instructions.To form and supply CC, a register can be used to latch thestate of the 'AS888 and supply inputs to a PAL for decoding,based upon the microcode's needs. Combinatorial logic inthe PAL allows multiple or single events to be selected orprovides a fixed value of "1" or "0" for forced conditions.To supply the micro sequencer with the proper addressof the microcode-equivalent version of the macrocodeinstruction, an instruction register and mapping PROM areneeded. Under microprogram control, the instruction registersamples the data bus to get the macrocode instruction. Theopcode portion is passed to the mapping PROM to form anaddress to the microcode routine. When the microcode isready to jump to the routine, it turns off the Y bus outputof the 'AS890 and enables the output of the mapping PROM.An optional means of altering the address uses B3-BO inputsof the 'AS890 to implement an N-way branch routine. Inthis method, the ten most significant address bits of DRAor DRA are concatenated with the B3-BO bits to supply anaddress.'Control information is supplied to the rest of the systemvia the control register and bus. By setting various bits withinthe control register, information can be passed to other,subsystems, such as memory and 110 peripherals. Bit 0 couldrepresent the read/write control line while bit 1 could selectmemory or 110 for the read/write. Bit 2 might function toenable interrupts and bit 3 to indicate when the system shouldenter a "wait" state for slow memory. The remaining controlbits can be programmed by the system designer to indicateadditional condition states of the "macrosystem'.Addressing of the register files, both 'AS888 internaland 'AS870 external, is done through the use of two l-of-2selector banks. The first bank selects address source; thisdesign offers a choice for operand processing of fixed valuesfrom the microcode or values from the macroinstructionlatched in the instruction register. The second bank selectsthe first or second operand as an address source for port 0of the external register file; port 1 uses the third operandas an address source. It should be noted that the designpresented in Figure 4-2 is a one-level pipeline that isinstruction-data based. The address and contents of the nextinstruction are being fetched while the current instructionis being executed. Tracing through the data flow, thefollowing can be observed:1. The pipeline register contains the currentinstruction being executed2. The ALU has just executed its instruction, andhas the current status ready at its output pins3. The status register that is attached to the ALUcontains the previous instruction's resultingstatus4. The contents of the next microprogram wordare being fetched at the same time that thecurrent instruction is being executed.TRACING THROUGH A 32-BIT COMPUTERWith the 'AS888 and 'AS890 as foundation chips, thetypical 32-bit supermini of Figures 4-2 and 4-3 can now befunctionally traced. First, note that the data of the mainprogram is handled separately from that of the microcodeeachon its own bus. The system is initialized by setting the'"clear" signal high-this causes a forced jump to thebeginning of the microcode memory. Instructions carried outby the microcode at this point might run system diagnostics,clear all registers throughout the 'AS888-based system, andset up the initial macrocode program address. In this design,the first program address to fetch an instruction from mainmemory comes from a fixed value in the microcode memory;it is possible to allow the address to be retrieved from apermanent location in main memory or from either a frontpanel or console, by modifying the microcode programslightly.Table 4-1 illustrates the microcode format for thisdesign. Note that it contains control signals for all chipsinvolved in the design. Some of these, such asTRANS LATCH and MARLATCH, are used with the systemclock to provide controlled loading of the various holdingregisters. Others supply necessary addressing information,directing input from either the main data bus or from themicrocode word itself.The FETCH routine is shown in functional, assemblerand microcoded forms in Tables 4-2,4-3 and 4-4. First, theprogram counter is read from the external register file andstored into the memory address register. After the programcounter is placed on the address bus, the program counteris updated and stored while the data from memory is allowedto settle down to a stable condition. The data is then latchedin both the instruction register and data-in register.The opcode field of the instruction register is passedthrough the mapping PROM to convert the opcode to anequivalent microcode routine address. When YOE is forcedhigh by the microcode, the 'AS890 is three-stated from theY bus and the mapping PROM's output is taken out of thethree-state mode to supply an address to the control store(microprogram memory); a forced jump is made to themicrocode routine to perform the instruction.3-104

Table 4-1. Microcode DefinitionMICROCODE0-1314-2728-3031-3334-36FIELD37383940414243-50515253545556-575859606162-6970-7172-757677-808182838485868788-99100101102-105106-109110-113114115116117118119120121122123-126PIN NAME INPUT TO FUNCTIONDRA13-DRAO 'AS890 Used for next-address branchesDRB13-DRBO 'AS890 Used for loading counterRC2-RCO :A.S890 Register/counter controlsS2-S0 'AS890 Stack controlMUX2-MUXO 'AS890 MUX control of Y output busINT 'AS890 Interrupt controlRAOE :A.S890 Enables ORA outputRBOE 'AS890 Enables ORB outputOSEL :A.S890 Mux control for ORA sourceINC 'AS890 Incrementer controlYOE 'AS890 Enables Y output bus17-10 'AS888 Instruction inputsOEA :A.S888 DA bus enableĒA 'AS888 ALU input operand selectOEB 'AS888 DB bus enableOEY 'AS888 Y bus output enableSELY 'AS888 Y bus selectEB1-EBO 'AS888 ALU input operand selectsWE 'AS888 Register file write enableMAP PROM Enables mapping PROM to 'AS890 Y busTR Latch Latches data bus to instruction registerCR Latch Latches control data to busCTRL7-CTRLO Latch Data for control latchBSEL 1-BSELO Multiplexer Selects data for 'AS890B3-BO Multiplexer Microcode data to switchCONDCD Latch Controls latch of 'AS888 statusSELC3-SELCO . PAL Selects combination of 'AS888 statusDTALATCHI Latch Controls latching of data-inDTAIN Latch Enables data-in output to busDTALATCHO Latch Controls latching of data-outDTAOUT Latch Enables data-out output to DB busMAR LATCH Latch Controls latching of addressMAR Latch Enables MAR output to address busCONSTPROM PROM Enables PROM to DA busA11-AO PROM Address of constant in PROMSWITCH2 Multiplexer Selects microcode or Instruction Register dataSWITCH1 Multiplexer Selects microcode or Instruction Register dataA3-AO Multiplexer Register file address ('AS888)B3-BO Multiplexer Register file address ('AS888)C3-CO Multiplexer Register file address ('AS888)REGUWR Register File Port 0 write enableREGLWR Register File Port 1 write enableREGU Register File Chip enable on port 0REGL Register File Chip enable on port 1TRANSLATCH Latch Controls latch between Y and DB busTRANS Latch Enables output to DB busSELCN2 Multiplexer Supplies carry input to 'AS888SELCN1 Multiplexer Supplies carry input to 'AS888REGUB Multiplexer Selects address for external register fileBYTE3 - BYTEO Three-state Enables data for byte/bit operations....en-oa.Q)a:I:o.+:;CO.2c..a.«3-105

Table 4-2. Functional Listing of FetchFETCH:MAR = PC, Enable MAR outputPC = PC + 1IR = DIR = data bus, Disable' AS890 Y bus,Enable mapping PROM to Y busTable 4-3. Assembler Listing of FetchFETCH: OP890 ..,111,10;INC;OP888 NOp,GROUP5,10 ..,1111;OEY;SELY;CR;CTRL 00000011;SELC 01;MARLATCH;MAR;SWITCH OO;REGL;TRANSLATCHOP890 ..,111,10;INC;OP888 PASS,INCS,OO ..,1111;OEB;OEY;SELC 01;MAR;REGLWR;REGL;TRANS;SELCN 01OP890 ..,111,10;OP888 NOP,GROUP5,10;MAP;IR;SELC 01DTALATCHI;MARSet 'AS890 for continuePerform NOP and read external register 15Enable Y bus outputGenerate external control bus signalsSelect fixed CC value to 'AS890Latch value on Y bus and enable outputSelect address source and enable portLatch Y bus for transfer to B busSet 'AS890 for continueIncrement program counterEnable Y bus outputSelect fixed CC value to 'AS890Output address to address busUpdate program counter in register fileEnable transfer latch output to B busSelect carry input to LSP to be "1"Set' AS890 for continuePerform NOPEnable mapping PROM to 'AS890 Y busLatch data bus to get macrolevel codeSelect fixed CC value to 'AS890Put data bus also in data registerOutput address to address busKey to Table 4-3OP888 a,b,c,d,e.fwhere:upper bits of instruction, 17-14b lower bits of instruction, 13-10value of EB1-EBOdA address of register filesB address of register filesC address of register filesOP890 V,W,x,y,Zwhere:v = DRA value, 14-bitsw ORB value, 14-bitsx = RC2-RCOS2-S0MUX2-MUXOAfter the routine is complete, a jump is made back tothe FETCH routine by using the next-address supplied bythe microprogram. It is up to the system designer/programmer to make sure that all system housekeeping isperformed, so that nothing causes a fatal endless loop.DEFINING THE MACROCODEINSTRUCTION FORMATSince this is a 32-bit design, a variety of instructionformats are available. The size of the opcode along with thetypes of addressing used, will affect both system size andperformance. The formats shown in Table 4-5 will be usedfor discussion.All Table 4-5 formats have an opcode field of 11 bitsand source/destination fields of 7 bits; the first three bits ofthe latter designate the address type, and the remaining fourbits are used for register access. The opcode length allows2,048 macrocoded instructions to be mapped to equivalentmicrocoded routines. The address fields can specify any ofthe following modes: register, relative, autoincrement/autodecrement, indexed, absolute, and deferred. The offsetused in the Type 0 instruction can be used for branch-basedinstructions, for an offset range of ± 32727.TRACING A MACROCODE INSTRUCTIONMicrocode for a Type 3 multiplication instruction isshown in Table 4-6, using the following assumptions:1. Code for retrieving the operands will not beshown. Jumps will be made to routines that willplace the temporary operands into internalregister locations 2 and 3 of the 'AS888, afterbeing fetched from main memory.3-106

Table 4-4. Microcode Listing of FetchDRAO0)(DRB13-:::I0 :::EDRBO ua:: 0 NN en )(u N :::Ia:: en :::E~~W.JI ~~~~00000000000000 00000000000000 000 111 o 1 0 1 1 1 0 10 111 11111 1 1 1 0 1 1 0 11 1 0100000000000000 00000000000000 000 1 11 o 1 0 1 1 1 0 10 11 1 1 0 1 00 11000001 11100000000000000 00000000000000 000 1 11 o 1 0 1 1 1 00 1 111 11111 o 1 1 1 1 1 01 00 117-10r~~eII>~_O~

Table 4-7. Assembler Code of Multiply• »"C'E.c:;"Q)r+0'::s:aCD"Cor+ ""enUMULl3:OPS90 SOURCE1",110.1,10;INC;YOE;OPSSS NOP;GROUP5;Perform a subroutine branchIncrement address and enable Y busTell 'ASSSS to do nothing during jumpSELC 0001;Set CC to "1". to set up 'ASS90 continueMARMaintain address on main address bussOPS90 SOURCE2.00000000100000.110.110.110; Perform subroutine branch and load BcounterINC;YOE;OPSSS NOP.GROUP5;SELC 0001;MAROPS90 ... 111.110;INC;YOE;OP888 CLEAR.GROUP5 .... 1001;WE;SELC 0001;MAROPS90 LOOP. .. lll.ll0;INC;YOE;OP88S LOADMQ.INCS ... 0010;Increment microaddress and enable Y busTell 'ASSSS to do nothing during jumpSet CC to "1" to set up 'ASS90 continueMaintain address on main address busPerform a continue instructionIncrement microaddress and enable Y busZero out register file accumulatorEnable writing to register fileSet CC to "1" to set up 'ASS90 continueMaintain address on main address bussPerform a continue instructionIncrement microaddress and enable Y busLoad MQ register with S + Cn. from externalregister fileMARMaintain address on main address busLOOP:OPS90 LOOP..l0l.l11.100;INC;YOE;OPSSS UMULI.GROUP4.01.0011 .. 1001;WE;MAROPS90 ... 111.110;INC;YOE;OP88S PASS.INCS .... l000;WE;MAROP890 STORPSW ... ll0.ll0;INC;YOE;OPSSS NOP.GROUP5;SELC 0001;MAROP890 FETCH ... lll;INC;YOE;OPSSS NOP.GROUP5;SELC 0001Decrement B and loop til ZERO = 1Increment microaddress and enable Y busPerform unsigned multiply on accumulatorUpdate register file accumulatorMaintain address on main address busPerform a continue instructionIncrement microaddress and enable Y busPut S + Cn in temporary register fileAllow updating of register fileMaintain address on main address busPerform a subroutine branchIncrement microaddress and enable Y busTell 'ASS8S to do nothing during jumpSet CC to "1" for set up 'ASS90 continueMaintain address on main address busPerform a branch to FETCH routineIncrement microaddress and enable Y busTell 'ASSSS to do nothing during jumpSet CC to "1" for 'AS890 continueKey to Table 4-7.OPS88 a.b.c.d.e.fwhere:OP890 V.W.X.y.Zwhere:a = upper bits of instruction. 17-14 v ORA value. 14-bitsb lower bits of instruction. 13-10 w ORB value. 14-bitsvalue of EB1-EBOx RC2-RCOd A address of register filesY S2-S0e = B address of register filesC address of register filesMUX2-MUXO3-108

Table 4-8. Microcode Listing of Multiply0xDRA13- DRB13- ::::l0 :E 17-10DRAO DRBO ua: 0NN II) x IWIW~ OOw W 1« 11ll>~_OU N ::::l1~~~~~!2wl«WWWIllIllI~a: II) :E OwOOIl)WW00000000001100 00000000000000 000 1 1 0 1 1 0 1 1 1 0 1 0 1 1 1 11111 1 1 1 1 000 1 1 1 100000000010000 00000000100000 1 1 0 1 1 0 1 1 0 1 1 1 0 1 0 1 1 1 11111 1 1 1 1 000 1 1 1 100000000000000 00000000000000 000 1 1 1 1 1 0 1 1 1 0 1 0 1 1 1 1 0000 1 1 100000 1 1 100001000001000 00000000000000 000 1 1 1 1 1 0 1 1 1 0 1 0 1 1 1 00 1 00 1 1 1 0000 1 1 1 100001000001000 00000000000000 1 0 1 1 1 1 1 00 1 1 1 0 1 0 1 1010000 1 1 1 000 1 0 1 1 100000000000000 00000000000000 000 1 11 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 000 1 0 1 1 100000000010100 00000000000000 000 1 1 0 1 1 0 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1000 1 1 1 100000000011000 00000000000000 000 1 1 0 1 1 0 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 000 1 1 1 100000000000011 00000000000000 000 1 11 000 11 1 0 1 0 11 111 1 11 1 11 1 000 1 1111~1~15CTRL7-CTRLOTable 4-8. Microcode Listing of Multiply (Continued)0 0...IUW ~II)II)WJ: J: U a: Al1-AO NII)~2~~:3 1=J:~~~!i!!z~II~I~ ~« «1« 0lii~*0 M 0 0 0...I::L a:a:~ ~W III U «u...I««~~(!lII) MW§ M ~ M a:a:WWWIII III II) oooo:E:Eu II) « III u ~~II)II)a:1_ 0 ~~ ~J:~:E § J:00000000 00 0000 1 000 1 1 1 1 1 1 0 1 000000000000 00 o 0 0 0 0000 o 000 1 1 1 1 1 1 000 1 100000000 00 0000 1 000 1 1 1 1 1 1 0 1 000000000000 00 0000 0000 0000 1 1 1 1 1 1 000 1 100000000 00 0000 1 000 1 1 1 1 1 1 0 1 000000000000 00 o 000 0000 1 00 1 1 1 1 1 1 1 000 1 100000000 00 0000 0 000 1 1 1 1 1 1 0 1 000000000000 00 0000 00 1 0 0000 1 1 0 1 1 1 000 1 100000000 00 0000 0 000 1 1 1 1 1 1 0 1 000000000000 00 00 1 1 0000 1 0 0 1 1 0 1 o 1 1 000 1 100000000 00 0000 0 000 1 1 1 1 1 1 0 1 000000000000 00 0000 0000 1 000 1 0 1 o 1 1 000 1 100000000 00 0000 0 000 1 1 1 1 1 1 0 1 000000000000 00 000 0 0000 o 0 0 0 1 1 1 1 1 1 000 1 100000000 00 0000 1 000 1 1 1 1 1 1 0 1 000000000000 00 0000 0000 0000 1 1 1 1 1 1 000 1 100000000 00 0000 1 000 1 1 1 11 111 000000000000 00 0000 0000 o 000 1 1 1 1 1 1 000 1 1:3II~I~1111111111111111112. A jump to a routine to store the product in thedestination will be handled similarly.3. Multiplication will be unsigned; the result willbe placed in two temporary locations of the'AS888.4. An update to the program status word, whichthe user can access at the macrocode level, mustalso be performed but is not shown.Assembler code is shown in Table 4-7; a microcodelisting is given in Table 4-8. The first two lines of microcodeare subroutine jumps to opcode fetching routines, which storethe operands in register fIles 2 and 3 in the 'AS888. The nexttwo instructions load up the 'AS890 with a counter'constantfor the multiply loop, load the MQ register of the 'AS888with the multiplier and clear the register that is temporarilyused for the accumulator.A loop is then entered to perform the multiplyinstruction 32 times to form the product, with themultiplicand coming from the internal register fIle of the'AS888. Upon exiting the loop, the MQ register is storedin a temporary register location in the 'AS888. The MQregister now contains the least significant bits of the resultand the temporary accumulator the most significant bits. Asubroutine jump is made to the program status word updateroutine; this will take the status flags of the last multiplicationiteration and change the macrolevel status word. The nextsubroutine jump is to a destination routine, which is followedby a branch to the FETCH routine to get the nextmacroinstruction to be executed.SYSTEM ENHANCEMENTSThe above example provides a broad overview of 32-bitsystem design using the 'AS888 and 'AS890. Certainadditional options may enhance system performance. Theseinclude:1_ Status latching. The design does not take intoaccount changes that need to be examined at themicrolevel while retaining macrolevel statusinformation. One solution would be to includeanother register in parallel to the status latch...U)+oJoc.Q)a:c:::o.~ca.2c..c.c:t:3-109

and provide control to choose between the twoto form the condition code value.2. Interrupts. To efficiently use a computersystem, interrupts are used to alter programflow in the case of I/O programming and realtimeapplications (involving hardware timers).To include this capability, external hardwaremust be included and the microcode modifiedaccordingly.3. Control store. One way of implementingmicroprogram memory is to use a ROM-baseddesign. It is becoming more common to designa writable control store, a completely RAMbasedor part RAM, part ROM storage system,that can be altered by system operation, suchas initialization from a floppy disk subsystem,or by the user to optimize or implement newmacrolevel instructions .. The cost ofimplementation must be weighed with the risksinvolved in changing instructions which maynot be supported by other sites.4. Instruction word definitions. Changing theinstruction word definitions will have an effecton both system design and performance.Removing Type 3 instructions from the design,for example, will have an effect on bothhardware and software: the external register fileaddressing must be changed and the l-of-2. selector removed. Likewise, changing theopcode length may restrict the instructionaddress capability and also cause either anincrease or decrease in the microcode size.5. Dynamic memory access (DMA). The abovesystem does not support dynamic memoryaccess. To include this function requires achange in the address output control, along withsupport circuitry for the type of DMA selected.Some error detection and correction logic formain memory might also be included.6. Computer control unit. The design presentedhere shows a one-level pipeline architecture thatis instruction-data based. System throughputmay be increased by converting to a pipelineof greater depth, or using another variety ofone-level pipeline, such as instruction-addressbased or address-data based. Care must be takenwhen increasing the size of the pipeline,especially when handling branch/jumpsituations. The reader is advised to carefullyresearch this area before implementing anydesign.Table 4-9. Critical Delay Path AnalysisCONTROL LOOPDATA LOOPTIMETIMECOMPONENT DATA PATH INS) COMPONENT DATA PATH INS)EIl>"C~.oQ)r+o·::::s:xlCD"Co"'" r+fJ)Pipeline register Clock to output 9 'AS888-1 Clock to C n 46MUX Select to output 13 'AS182 Cn to Cn + z 5'AS890-1 CC to output 25 'AS888-1 C n to SIO 25PROM Access time 20 'AS888-1 SIO to Y 14Pipeline register Setup time 2- -69 90Table 4-10. Fetch Timing Comparison'AS888FETCH 32-BIT Z8001 8086-1 80286 68000LData width 32 16 16 16 16No. of cycles 4 3 4 4 4Clock rate 11.11 MHz 4 MHz 10 MHz 10 MHz 8 MHzTotal time 360 ns 750 ns 400 ns 400 ns 600 nsTable 4-11. Multiply Timing Comparison'AS888'AS888MULTIPLY 32-BIT 16-BIT Z8001 8086-1 80286 68000LSize 32 x 32 16 x 16 16 x 16 16 x 16 16 x 16 16 x 16No. of cycles 35 19 70 128 21 :574Clock rate 11.11 MHz 10.98 MHz 4 MHz 10 MHz 10 MHz 8 MHzTotal time 3.150 IlS 1. 729 Ils 17.51ls 12.81ls 2.1 Ils :s 9.25 Ils3-110

TIMING AND SYSTEM THROUGHPUTA critical path analysis was undertaken to determinethe maximum clock rate for the proposed system. The longestdelay path is the multiplication data path, which involves theinternal register file and the shift function of the 'AS888.Table 4-9 contains the critical delay calculations for both theALU and CCU. Since both portions of the system must besatisfied, a clock rate of 90 ns was selected for the followingcomparisons.FETCH ANALYSISMost microprocessors perform an instruction fetch ina pipeline mode; the next instruction is fetched while thecurrent instruction is executing. The fetch code shown earlierrequires a minimum of four cycles: three to issue the codeand one to break the pipeline for processing the batch. Thisresults in a total time of 360 ns, based on a 90 ns cycle time.Fetch times for the representative microprocessors have beenestimated from data books and are shown in Table 4-10; waitstates for slow memory are not included. As can be seen fromthe table, the 'AS888 design example is estimated to rurl from1.1 to 2.1 times faster than the 16-bit microprocessors.MULTIPLICATION ANALYSISThis analysis assumes that multiplication is unsignedinteger and register to register based. No account is takenof time needed for instruction fetch or operand fetch or store.The basic loop for the multiply takes 35 cycles: 2 foraccumulator and multiplier setup, 32 for actual multiply loopand 1 to store the least significant bits in an internal registerfile. Given a cycle time of90 ns, a 32 by 32 bit multiplicationcan be implemented in 2.275 microseconds. A 16-bit multiplyrequires 16 iterations of the inner loop; both timings areincluded in Table 4-11 for comparison. Values for the 16-bitmultiplies of the representative microprocessors have beenestimated from data books.As shown in Table 4-11, the 16 by 16 multiply canbe performed with the 'AS888 at a faster rate than the 16-bitmicroprocessors. Even comparing the 32 by 32 multiply ofthc application design, one can see that the 'AS888 basedsystem has a better macroinstruction execution speed. Usingthe 'AS888 and 'AS890 in a system design will allow highthroughput and a flexible architecture....U)~oc.Q)a:s::::::o".;:CO.~0..c.

lEIl>'0'2..crDo)r+o·;:,:0CD'0o"""Ir+tJ)3-112

Section 5An Adaptive Clock Generator To Increase ' AS888 System Speed, AS888-l instructions execute within 50 to 90 ns; overhalf execute in less than 60 ns. It is therefore possible toenhance the speed of an 'AS888 system using an adaptiveclock generator that spaces clock pulses according to the timerequired to complete each operation. The advantage of usingthis circuit is that the system can process each instructionin almost exactly the time it takes the desired results to reachsteady-state. The alternative is to use a periodic 90 ns clockand waste use of 'AS888 "idle time." Just how fast thesystem will run with the adaptive clock is a function of thestatistical distribution of microinstructions within any givenmicroprogram.The time required for an 'AS888 instruction dependson whether shift, carry, register file read, ZERO status testand/or N status test are used. These operations requirevarying lengths of time to execute, depending on the numberof 'AS888 internal delays involved. Whether shift and/orcarry are used is determined by the 'AS888 instruction field.ALU source operands can originate from the register file orthe DA and DB buses; this is determined by the state of theEA and EBl-EBO inputs. Whether or not ZERO or N statusare tested depends on other system signals, such as a statusselect field in the microinstruction to select ALU status duringconditional branching. Depending on the system architecture,the pipelining scheme used and the flexibility of themicroprogram, the designer may wish to ensure that testZERO and test N signals be made available during the cyclein which ZERO or N are generated in order to better matchclock pulse spacing to processing delay. By also providinga register file read signal, the clock spacing will be optimallymatched to the processing delay.CIRCUIT DESCRIPTIONA diagram of the adaptive clock circuit is given inFigure 5-1. The circuit consists of a PROM decoder and aprogrammable oscillator. The PROM contains a table ofcycle length codes as a function of the 'AS888 instructionfield, register file read (RFRD), ZERO test (ZTST) and Ntest (NTST). These signals are connected to the PROMaddress inputs from the control store outputs as shown. Ifthe RFRD, ZTST and NTST signals are not available, theseinputs can be tied high, or a smaller PROM can be used.The cycle length codes residing in PROM are used toselect one of nine delays in the programmable delay lineoscillator. The selected delay provides the phase shiftrequired for oscillation. Two progammable delay lines (DataDelay Devices PDU-1613-5) are needed; they must bealternately switched into the feedback loop so that each hastime to empty. The programmable delay lines establish thetiming from leading edge to leading edge of the clock foran overall error of only ±3.5 ns. The delays for variousfixed-length delay lines are indicated by the numbers in thenumbered boxes in Figure 5-1.Timing for this circuit is shown in Figure 5-2. RSTinitializes the circuit. When RST releases, the open collectoroutput of U4a provides an initial rising edge from which allsuccessive rising edges are regenerated. Toggle flip-flop U3aswitches between the two halves of the oscillator. LatchesU6a and U6b are alternately enabled by the Q and Q outputsofU3b. In this manner only one delay line at a time is selectedto receive a pulse. U3a generates OEI and OE2 which selectthe available delay line for output. The pulse width regulationis also initiated by U3a. TQ and TQ serve as references foredge detectors U5a-U5d. The fixed delay lines shape OCl,CLRl, OC2, and CLR2. The output control OCI (or OC2)on U6a (or U6b) turns off several nanoseconds after a risingtransition in TQ (or TQ) has occurred thereby holding Ql(or Q2) high. This stretches the on-time of the pulse to nearly50 ns. U6a (or U6b) is cleared 10 ns later. After another10 ns the output control turns on again, allowing the Q whichwas just cleared to establish the falling edge of the stretchedpulse. This stretched pulse then enters the selected delay line,U7 (or U8), exiting at a time established by the cycle lengthcode. The delay line output enable, OEl (or OE2) switchesin the delay line before its pulse is ready to exit. In thismanner, the width of the previous pulse is regulated to within20 to 30 ns.PROM PROGRAMThe cycle lengths are defined by analyzing thepropagation delays from the i\S888 data sheet given in Table5-1. Variations in cycle lengths depend on whether shift, carry,register file read, ZERO test or N test are used. The algorithmfor determining cycle length is flowcharted in Figures5-3-5-6. Total cycle length is found by adding up all thecontributing delays for each possible case. Sums less than50 ns must be adjusted to 50 ns since this is the minimumclock cycle length specified in the data sheet. Sevennanoseconds is used as the propagation time for G/P to Cn;this assumes an i\S182 lookahead carry generator is used withthe i\S888. Each total delay is rounded up to the nearestinteger multiple of 5 ns, which gives nine possible outcomes.Use of the shifters or carry is inherent in eachinstruction as shown in Table 5-2. Cycle length codes canbe generated by looking up Table 5-2 for each instruction,performing the algorithm in Figures 5-3-5-6, and encodingIItn....,"" oc.(1)a:r::::o•.i=CO.2c..c.«3-113

C:J.p.SlJodaM UO!lR:l!ldd" IIRST) • •P~Q1Q 1--------11 INU7OUTOUT1U1: 'AS374U2: TBP166AU3: 'ASB73U4: 'S05U5: 'AD1BOBU6: 'ASB73U7: PDU-1613-5UB: PDU-1613-5oGOE110EADDRU6bUB0OC21-OCI a21~ I'NaUTIOUT2 I CLOCKFROMCONTROLSTORE--17-10U1U22K x BPROM4;' NC0QW_ G2Q GCLRZTST*NTST*RFRD**Tie high ifnot available.4+5VFigure 5-1. Adaptive Clock Generator Circuit

• -H---i-~CU

each of the nine possible time delays with a number fromo to 8. A BASIC program which follows this procedure andgenerates the PROM data in Data 110 hex-ASCII format isshown in Program 5-1. Program lines 147-149 look up carryand shift for each instruction. Once carry and shift are known,the program solves the total delay algorithm in Figures5-3-5-6 for all cases of ZTST, NTST, and RFRD as shownin program lines 163-184. At this point the actual time toprocess the microinstruction for the given conditions issolved. The time values are then encoded from 0 to 8 inprogram lines 188-195. The output is listed in Figure 5-7.Table 5-2. Shift and Carry as a Function of 17-10INSTRUCTION BITS 113-101HEX CODEGROUP 1 INSTRUCTIONSMNEMONIC CARRY SHIFT01 ADD'"2 SUBR'"3 SUBS'"4 INCS'"5 INCNS'"6 INCR'"7 INCNR'"B9 XORABCDANDORNANDNOR\ E ANDNRFINSTRUCTION BITS 117-141HEX CODEGROUP 2 INSTRUCTIONSMNEMONIC CARRY SHIFT0 SRA1 SRAD'"2 SRL'"3 SRLD'"4 SLA'"5 SLAD'"6 SLC'"7 SLCD'"8 SRC'"9 SRCDABCDEFMQSRAMQSRLMQSLLMQSLCLOADMQPASS'"'"'"'"'"'"3-116

Table 5-2. Shift and Carry as a Function of 17-10 (Continued)INSTRUCTION BITS (17-10)HEX CODEGROUP 3 INSTRUCTIONSMNEMONICCARRY08 SET1 ,.,.18 SETa28 TB138 TBO48 ABS ,.,.58 SMTC ,.,.68 ADDI ,.,.78 SUBI ,.,.88 BADD ,.,.98 BSUBS ,.,.A8 BSUBR ,.,.B8 BINCS ,.,.C8 BINCNS ,.,.D8E8F8BXORBANDBORGROUP 4 INSTRUCTIONS00 CRC10 SEL ,.,.20 SNORM ,.,.30 DNORM40 DIVRF ,.,.50 SDIVQF ,.,.60 SMUll ,.,.70 SMULT ,.,.80 SDIVIN90 SDIVIS ,.,.AO SDIVI ,.,.BO UDIVIS ,.,.CO UDIVI ,.,.DO UMULI ,.,.EO SDIVIT ,.,.Fa UDIVIT ,.,.OF1F2F3F4F5F6FGROUP 5 INSTRUCTIONSCLRCLRCLRCLRCLRCLRCLR7F BCDBIN ,.,.8F EX3BC ,.,.9F EX3C ,.,.AF SDIVO ,.,.BFCLRCFCLRDF BINEX3 ,.,.EFFFCLRNOPSHIFT,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,....., ena..oCoQ)a:c:o.~co(.)Q.Co«3-117

II»"'C"2-DA/DB-Z (46)50 nsDA/DB-+N (41)C;'Q) 50 ns....0'N N:J:JJCD"'C....0""'IA/B-+Y (44) DA/DB-+Y (36)en 50 ns 50 ns3-118Figure 5-3. Propagation Delay Without Carry and Without Shift

A/B-SIO/OIO (48) DA/DB-SIO/QIO (40)SIO/QIO-Z (20) SIO/QIO-Z (20)(68) (60)70 ns 60 nsen+oJA/B-SIO/QIO (48) DA/DB-SIO/QIO (40) a...SIO/QIO-N (18) SIO/QIO-N (18) 0(66) (58) CoQ)70 ns 60 ns a:N N t:0"';::;ctSA/B-SIO/QIO (48)"~DA/DB-SIO/QIO (40)SIO/Q10-Y (14) SIO/Q10-Y (14) C.(62) (54) Co65 ns 55 ns

CARRYUSED

CARRYUSEDSHIFTUSEDNAlB-alP (36)a/P-Cn (7)Cn-SIO/OIO (25)SIO/OIO-Z (20)(B8)90 nsAlB-alP (36)a/P-Cn (7)Cn-SIO/OIO (25)SIO/OIO-N (18)(86)90 nsA/B-G/P (36)a/P-Cn (7)Cn-SIO/OIO (25)SIO/OIO-Y (14)(82)85 nsNDA/DB-a/P (24)a/P-Cn (7)Cn-SIO/OIO (25)SIO/OIO-Z (20)(76)80 ns•tJ)DA/DB-a/P (24) .....a/P-Cn (7) Cn-SIO/OIO (25) 0SIO/OIO-N (18) C.(74)(1)75 ns a::r:::0"';:;ctSDA/DB-a/P (24) CJG/P-Cn (7)a.Cn-SIO/OIO (25)C.SIO/OIO-Y (14)(70)cd:70 nsFigure 5-6. Propagation Delay With Carry and With Shift3-121

EI148 '100 '************************************************************************101 CLS :''It102 PRINT" 'AS888-1 ADAPTIVE CLOCK GENERATOR ":'*103 PRINT" PROM DATA GENERATION PROGRAM ":'*-104 PRINT" MAY 24, 1985 ": '*105 . : '*106 '************************************************************************107 '108 DEFINT A-Z109 DIM TABLE(4096)110 'III ' DEFINE TRANSMISSION CONTROL CHARACTERS112113 STX$=CHR$(2)114 ETX$=CHR$(3)115 CR$=CHR$(13)+CHR$(10)116 TX$=STX$117 BS$=CHR$(8)118 '119 ' INPUT USER'S PROM DATA FILE NAME AND OPEN THE FILE120121 PRINT: INPUT "PROM DATA OUTPUT FILE NAME";OF$ : PRINT122 OPEN "O",#l,OF$ : PRINT "WRITING CYCLE LENGTH CODES TO ";OF$;" ... " PRINT123 '124 ' SET UP DATA I/O PROGRAMMER FOR HEX-ASCII (COMMA) FORMAT125126 PRINT #1,"53A"127 '128 ' FOR EACH 'AS888 INSTRUCTION (BITS 17-10), DETERMINE IF129 ' SHIFT AND/OR CARRY ARE USED130131 FOR 1714 = 0 TO 15132 FOR 1310 = 0 TO 15133 '134 ' DEFINE THE 8-BIT INSTRUCTION FIELD AND IDENTIFY WHICH GROUP(s)135 ' THE INSTRUCTION BELONGS TO136 '137138139140141142143 '144 '1710 = 1714 * 16 + 1310GROUP 1 (13100) AND (13108)GROUP2 GROUP 1GROUP3 (1310 8)GROUP4 (1310 0)GROUPS (1310 = 15)AND

167 IF NOT CARRY AND SHIFT AND NOT RF AND NOT Z AND NOT N THEN TIME = 55168 IF NOT CARRY AND SHIFT AND RF AND Z THEN TIME = 70169 IF NOT CARRY AND SHIFT AND RF AND NOT Z AND N THEN TIME = 70170 IF NOT CARRY AND SHIFT AND RF AND NOT Z AND NOT N THEN TIME = 65171 '172 IF CARRY AND NOT SHIFT AND RF AND Z THEN TIME = 60173 IF CARRY AND NOT SHIFT AND RF AND NOT Z AND N THEN TIME = 55174 IF CARRY AND NOT SHIFT AND RF AND NOT Z AND NOT N THEN TIME = 55175 IF CARRY AND NOT SHIFT AND NOT RF AND Z THEN TIME = 70176 IF CARRY AND NOT SHIFT AND NOT RFAND NOT Z AND N THEN TIME = 65177 IF CARRY AND NOT SHIFT AND NOT RF AND NOT Z AND NOT N THEN TIME = 65178 '179 IF180 IF181 IF182 IF183 IF184 IF185 'CARRY ANDCARRY ANDCARRY ANDCARRY ANDCARRY ANDCARRY AND186 : ENCODE THE TIME DELAYS AS FOLLOWS187188 IF TIME = 50 THEN CODE = 0189 IF. TIME = 55 THEN CODE = 1190 IF TIME = 60 THEN CODE = 2191 IF TIME = 65 THEN CODE = 3192 IF TIME = 70 THEN CODE = 4193 IF TIME = 75 THEN CODE = 5194 IF TIME = 80 THEN CODE = 6SHIFT AND RF AND Z THEN TIME = 80SHIFT AND RF AND NOT Z AND N THEN TIME = 75SHIFT AND RF AND NOT Z AND NOT N THEN TIME = 70SHIFT AND NOT RF AND Z THEN TIME = 90SHIFT AND NOT RF AND NOT Z AND N THEN TIME = 90SHIFT AND NOT RF AND NOT Z AND NOT N THEN TIME = 85195 IF TIME = 85 THEN CODE = 7196 IF TIME = 90 THEN CODE = 8197 '198 ' WRITE THE SELECT CODE TO THE OUTPUT FILE199 ' IN DATA 1/0 HEX ASCII (COMMA) FORMAT200 '201 IF ADDR=4095 THEN TX$=ETX$202 IF ADDR/16=INT(ADDR/16) THEN PRINT #1,TX$;"$A";RIGHT$("000"+HEX$(ADDR).4);"."; ELSE PRINT #1,".";203 PRINT #l."O";RIGHT$(STR$(CODE).l);204 ADDR=ADDR+l205 TX$=ETX$+CR$+STX$206 NEXT:NEXT:NEXT207 PRINT STRING$(14.8);INTCI00*ADDR/4096);"%";TAB(6);" COMPLETE";208 NEXT:NEXT209 CLOSE l:PRINT"PROM DATA FILE ";OF$;" IS READY.":SYSTEM210 '211 ' END212 'Program 5-1. BASIC Program to Generate PROM Data (Continued)•U)........oc.0)a:s::::o.+:;CO.2C.c.«3-123

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Section 6Floating-Point System Design Using the 1\S888/1\S890Bit-slice processor architecture addresses the problemof optimizing system performance while allowing the userto balance hardware complexity against software flexibility.Bit-slice systems usually operate at or near the speed of themost primitive of programmable processors, the PROM statesequencer. Of course, bit-slice architecture incorporatescircuitry dedicated not only to sequencing, but also dataprocessing (ALU) operations. In keeping with the trend ofthese programmable devices to track the speed of fast discretehardware, the ' AS888 8-bit slice ALU and ' AS890microsequencer have been produced in Advanced Schottkybipolar technology. In addition to sheer speed, thecomponents feature greater density (2 micron geometry) forgreater functionality (more special purpose circuitry onboard). The impact will be faster, more powerful systemsin applications which previously pushed the limits of bit-sliceprocessors.Consider an application in which bit-slice architecturehas dominated for years: CPU design. The microprogrammedCPU itself spans a spectrum of uses rangingfrom general purpose minicomputers to compact airbornecomputers. A specific example which illustrates variousfacets of design using the' AS888 and' AS890 is a CPU witha floating-point utility to compute sin(x).The design process can be subject to many influences,including personal preference, available development tools,peculiarities of the application, and constraints from the user,customer or manufacturing environment. No hard and fastdesign rules could be applied universally, but most designerswill start with a specific plan in mind.The goal of this example is to produce the hardware andmicroprogram which will implement the sin(x) function infloating-point arithmetic. Before the microprogram can beassembled, the hardware must be defined since the fields ofthe microinstruction are dedicated to specific hardware oncethe microinstruction register is hardwired to the devices itcontrols. Since the final architecture chosen depends on tradeoffsbetween implementing certain operations in hardwareor software, critical applications will require that a cursoryanalysis of the software be made before the hardware is castin concrete. Attempting to develop microcode for a tentativearchitecture will force the issue on which operations are bettersuited for hardware. Before the architecture or themicroprogram requirements can be known, the algorithmswhich describe the application processes must be defined.Once an algorithm is formulated it can be broken down intooperations involving variable and constant quantities. Thevariables can be assigned to registers and then the algorithmcan be translated into a microprogram. The following stepsillustrate the plan for this CPU design example incorporatinga floating-point sin(x) utility:Step I: Choose a floating-point number systemStep 2: Choose an algorithm for approximatingsin(x)Step 3: Make' AS888 register assignmentsStep 4: Substitute registers for variables in thealgorith~Step 5: Decompose steps of the algorithm intosimple operationsStep 6: Translate into 'AS888/890 operations;identify subroutinesStep 7: Expand subroutines into 'AS888/890operationsStep 8: Evaluate trade-offs and block diagram thehardwareStep 9: Define microinstruction fields duringdetailed hardware designStep 10: Assemble the microprogramSTEP 1: CHOOSE A FWATING-POINT NUMBER SYSTEMAn IEEE floating-point format will be chosen for this example for portability of data and software. It is important tonote that the IEEE defines many standards in arithmetic processing, but for simplicity this example will encompass onlynumber format. Furthermore, while several formats are IEEE compatible, only the basic single-precision format will beconsidered.The IEEE basic single-precision format is defined as a 32-bit representation in which the component fields are a I-bitsign s, an 8-bit biased exponent e and a 23-bit fraction f which are assembled in the following order:e31 of..., rn...oc.(1)a:c:o',t:CU.2a.c.«The quantity is evaluated as ( - I)S 2 e - 127 (1f). Not-a-number, zero and infinity have special representations. Theone preceding the binary point is implied and is called the implicit one or implicit bit. It coincides with the fact that thedigits are normalized (left justified). .3-125

STEP 2: CHOOSE AN ALGORITHM FOR Sin (x)Many algorithms are discussed in the literature for approximating useful quantities like sin(x). Literature research isa good place to start to familiarize oneself with various algorithms and trade-offs for a particular application. Computer simulationis also useful to compare algorithms for speed and accuracy. R.F. Ruckdeschel in BASIC Scientific Subroutines, Vol. 1 (BYTE,McGraw-Hili Publications Co., New York, N.Y., 1981, pp. 159-191) discusses trade-offs and provides a simulation inBASIC for a sin(x) algorithm. An adaptation of this material has been chosen for this example:A) Reduce angle range to first quadrant. (0 :s x :s 7r/2)6B) Compute sin(x):::: k Anx2n - I. The coefficients are:n=OCoefficientDecimalAO 1.000000Al -0.1666667A2 0.008333333A3 -0.0001984127A4 0.000002755760A5 - 0.00000002507060A6 0.0000000001641060The algorithm can be implemented in the following steps:A) Reduce angle range to first quadrant. (0 :s x :s 7r/2)1) SIGN = SGN(x)2) ABSX = Ilxll3) XNEW = ABSX - 27r X INT(ABSX/27r)4) If XNEW > 7r then SIGN = - SIGN and XNEW5) If XNEW > 7r/2 then XNEW = 7r - XNEWIEEE hex3F80 0000BE2A AAAO3C08 8888B95000013638 EF99B2075A052F346FBCXNEW -7rwhereSGN(x) = j + I i.f x ;::: 0l- I If x < 0lEI»'C'E..c;'Q)r+o·:::s:J:JCD'Cor+ '""(J)B)INT(x) = integer function6Compute sin(x):::: k An x2n - 1.n=OI) Let XSQR = XNEW2; INITIALIZE SINX =02) Do i = 6 to I step - 1SINX = XSQR X SINX + A(i)Enddo3) SINX = SIGN X XNEW X SINXStep B-2 computes the summation in a geometric series for economy. The major difference between steps A and B isthat A requires more'diverse ALU operations while B uses only multiplication and addition recursively.STEP 3: MAKE i\S888 REGISTER ASSIGNMENTSJust as in assembly language programming, registers must be allocated for variables. Using Rn to denote the' AS888register whose address is n, where 0 :s n :s F (hex), the following register assignments can be made:RORIR2R3R4R5XSIGNABSXXNEWXSQRSINX3-126

The following constants can also be defined:ConstantPI= 7rPIOVR2 = 7r/22PI =27rIOVR2PI = 1I27rDecimal3.1415931.5707976.2831850.159155IEEE hex40590FDB3FC90FDB40C90FDB3E22 F981STEP 4: SUBSTITUTE REGISTERS FOR VARIABLES IN THE ALGORITHMNow the algorithm can be rewritten with registers replacing variables:A)Reduce angle range to first quadrant (0 :5 x :5 7r/2).I) RI SGN(RO)2) R2 = II RO II3) R3 = R2 - 27r X INT(R2/27r)4) If R3 > 7r then R I = - R I; R3 R3 - 7r5) If R3 > 7r/2 then R3 = 7r - R3B)6Compute sin(x) =:: ~ An x2n - I.n=OI) Let R4 = R02; INITIALIZE R5 02) Do i = 6 to I step - IR5 = R4 x R5 + A(i)Enddo3) R5 = Rl x RO x R5Since various references to constants are made, it is probably best to load constants as needed rather than attempt toallocate registers for them. Constants can be loaded from a constant field in the microinstruction or from ROM. The trade-offis 32 bits by 16K of micromemory versus 32 bits by the number of constants (typically less than 16K). For this example,it will be assumed that a constant field in the microinstruction is acceptable.STEP 5: DECOMPOSE STEPS IN THE ALGORITHM INTO SIMPLE OPERATIONSThe sin(x) function can be microprogrammed as a subroutine; let FSIN be its entry address. RO would be loaded withx before FSIN was called. Upon return, R5 would contain sin(x). Now decompose the steps in the algorithm into simplearithmetic and logical operations. Other operations can be left as functions to be defined later.FSIN: SUBROUTINEA) Reduce angle range to first quadrant. (0 :5 x :5 7r/2)RIR2SGN(RO)ABS(RO)R3 R2 * IOVR2PIR3 INT(R3)R3 R3 * 2PIR3 R2 - R3Y = R3 - PIJump if Negative to Step A-5RI -RlR3 = R3 - PIY = PIOVR2 - R3Jump if Negative to Step B-1R3 = PI - R3I) Let RI = Sign of RO2) R2 IIROII3) R3 R2 - 27r * INT(R2/27r)4) IfR3 > 7r,then RI = - RI;R3 = R3 - 7r5) If R3 > 7r/2then R3 = 7r -R3rn~a..oC.Q)a:r::::o',fjCO.~C.c.«3-127

6B) Compute sin(x) == En=OR4 RO * ROR5 0An x2n - II) Let R4 R02. Let R5oR5R5R5R5R5R5R5R5R5R5R5R5R5R5R4 * R5R5 + A6R4 * R5R5 + A5R4 * R5R5 + A4R4 * R5R5 + A3R4 * R5R5 + A2R4 * R5R5 + AlR4 * R5R5 + AO2) Do i = 6 to I step - 1R5 = R4 X R5 + A(i)Enddo(To implement a loop,use an 'AS890 counterto index a memory containingthe constants.)Il>"C'E.C;'Q)r+0':::s:IJCD"Co...r+tJ)3-128R5 RO * R5 3) R5 R I X RO X R5R5 R5 * RI : RETURNEND SUBROUTINESTEP 6: TRANSLATE INTO 1\S888/890 INSTRUCTIONS; IDENTIFY SUBROUTINESThe· simplified steps of the algorithm can be represented fairly easily as 'AS888/890 instructions. Necessary functions(and suggested names) can be identified by inspection as:1) FMUL- Floating-point multiplication2) FADD - Floating-point addition3) FINT - Floating-point integer conversion4) FINV - Floating-point additive inverse (to subtract using FADD)5) FABS - Floating-point absolute value6) FSGN - Floating-point sign test7) FCHS - Floating-point change of sign (to multiply by SIGN)"Function" in this context refers to a special operation regardless of how it is coded. In fact, FMUL and FADD arefairly complex and require detailed explanation. FINV, FABS, FSGN and FCHS are single instruction operations that maskor mask and test. FINT requires several inline instructions or a subroutine and will be left to the interested reader as anexercise. Now the steps of the algorithm can be translated into' AS888/890 operations which include references to these functions.FSIN: SUBROUTINEA) Reduce angle range to first quadrant. (0 ::5 X ::5 7r12)RI FSGN(RO) ; Get sign bit (MSB)R2 FABS(RO) ; Take absolute value (clear MSB)R3 FMUL(R2,lOVR2PI) ; Multiply register and constantR3 FINT(R3) ; Floating-point integer conversionR3 FMUL(R3,2PI) ; Multiply register and constantR3 FADD(R2,INV(R3» ; Subtract registers by adding inverseY = FADD(R3,NEGPI) : TEST NEG; Subtract by adding negative constantJT SINI; Jump if true Gump if negative)RI = FINV(RI); Complement sign of RIR3 = FADD(R3,NEGPI); Subtract by adding negative constantSINI:Y = PIOVR2 - R3 : TEST NEG ; Subtract to compare (don't store)JT SIN2; Jump if true Gump if negative)R3 = FADD(PI,FINV(R3»; Subtract by adding negative register

6; B) Compute sin(x) == E An x2n - In=OSIN2: R4R5R5R5R5R5R5R5R5R5R5R5R5R5R5R5FMUL(RO,RO)A6FMUL(R4,R5)FADD(R5,A5)FMUL(R4,R5)FADD(R5,A4)FMUL(R4,R5)FADD(R5,A3)FMUL(R4,R5)FADD(R5,A2)FMUL(R4,R5)FADD(R5,A!)FMUL(R4,R5)FADD(R5,AO)FMUL(RO,R5)FCHS(R5,RI) : RETURN; Square by multiplying; Initialize series; Multiply registers; Add coefficient; MUltiply registers; Add coefficient; Multiply registers; Add coefficient; Multiply registers; Add coefficient; Multiply registers; Add coefficient; Multiply registers; Add coefficient; Multiply registers; Change MSB of R5 to MSB of R 1END SUBROUTINEThis contrived language has a syntax which may be suitable for a source program. For the sake of illustration, it canbe assumed that the microassembler recognizes this particular syntax. The series was computed inline instead of using aloop since it is relatively short. If a loop were used, a means of indexing the constants would be required.STEP 7: EXPAND SUBROUTINES INTO 1\.S888/890 OPERATIONSFMUL and FADD algorithms can now be expanded. Since they are called extensively from FSIN, they are more criticalto the efficiency of the final design. Wherever possible, it is desirable to reduce the execution time of both in order to maintainefficiency.Floating-Point MultiplicationLet M I be the multiplier and M2 be the multiplicand whose product is P. Let the sign, exponent and fraction fieldsof their IEEE representation be:Ml: ISllEllFIIM2 : IS21E21F21P : 1 S31 E31 F3 iP is found by multiplying mantissas (fraction plus implicit one) and adding exponents. Since M 1 and M2 are normalized,the range of I. F 1 x I. F2 is1.00 ... 0 :5 I.Fl x I.F2 :511.1. .. 10The implicit bit may "overflow" into bit position 24. This type of overflow must be detected so that the result can benormalized. Normalization requires right shifting the result of I.Fl X l.F2 and incrementing E3. The implicit bit is thencleared when S3, E3 and M3 are packed to form P. The floating-point multiplication algorithm may then be defined as follows:I) Unpack MI into signed fraction (SF!) and exponent (EI)2) Set the implicit bit in SFl3) Unpack M2 into signed fraction (SF2) and exponent (E2)4) Set the implicit bit in SF25) Perform SF3 = SFI X SF2 using signed integer multiplication6) Perform E3 = E I + E27) Test SF3 for overflow into bit 248) If true, then increment E3 and right shift SF39) Clear the implicit bit in SF310) Pack E3 and SF3 to get P..... en~oCoQ)a:t:o"+=ico"~c..Co

As before, the steps of this algorithm can be broken down into simpler operations:I) Unpack MI into signed fraction (SFI) and exponent (El)EI = FEXP(MI)SFI = FRAC(Ml)2) Set the implicit bit in SF!SFI = SF! OR BIT233) Unpack M2 into signed fraction (SF2) and exponent (E2)E2 = FEXP (M2)SF2 = FRAC (M2)4) Set the implicit bit in SF2SF2 = SF2 OR BIT235) Perform SF3 = SF! X SF2 using signed integer mUltiplicationSF3 = IMUL (SF!, SF2)6) Perform E3 = E I + E2E3 = EI + E27) Test SF3 for overflow into bit 24TEST (SF3 AND BIT24)JUMP IF FALSE to step 98) If true, then increment E3 and right shift SF3INC E3SF3 = RSHFT (SF3)9) Clear the implicit bit in SF3.SF3 = SF3 AND NOT _BIT23! 0) Pack E3 and SF3 to get PP = SF3 OR E3FEXP, FRAC, testing bit 24 and setting/clearing bit 23 are all mask operations that translate into single' AS888instructions. The integer multiplication (lMUL) is simply the multiplication algorithm supported by the' AS888instruction set. No significant hardware features are required to do floating-point multiplication, nor are any subroutinesrequired to support it.Register assignments can now be made as before. Since FSIN uses registers in the lower half of the registerfile. it might be preferable to restrict FMUL to the upper registers. For example:RF = PRE = Ml, Fl, SFIRD = M2, F2, SF2RC = EIRB = E2RE and RD can share variables that need not be preserved. Using this assignment, FMUL computes RFFMUL(RE,RD). RE and RD must be loaded prior to calling FMUL and RF must be stored upon return. By substitutingregisters for variables and reorganizing operations in the FMUL algorithm to better fit 'AS888/890 operations thefollowing source program may be created:FMUL: SUBROUTINERC = FEXP(RE)RE = FRAC(RE)RE = RE OR BIT23MQ = SMTC(RE)RB = FEXP(RD)RD FMAG(RD)RD RD OR BIT23RD SMTC(RD); Unpack MI into exponent; and fraction; Set implicit bit; Prepare to multiply; Unpack M2 into exponent; and fraction; Set implicit bit; Prepare to multiply3-130

Floating-Point AdditionRE 0 : RCA = # 22d ; Initialize to multiplyRE SMUll RD : LOOP RCA ; Integer multiplication iterationRE SMUL T RD ; Final step in signed multiplyY = TBO(RE,BITl):BYTE = # OIOOb:TEST Z ; Test "overflow"JF FMULI; Jump if false (exponent ok)INEX(RC)RE = SRA(RE)FMULl:RC = RC + RB : TEST CARRYJT ERRORRERERFSMTC(RE)RE AND # 807F _FFFFhRE OR RC : RETURN; Increment exponent: add 00800000; Shift fraction to normalize; Add exponents and test carry; Jump if carry true to handler; Get sign magnitude fraction; Clear implicit bit; Pack fraction and exponentThe floating-point addition algorithm (FADD) is slightly more complex than FMUL, since the two addendswill usually not have the same exponent. Therefore the smaller (absolute value) addend must first be chosen bycomparing exponents. Then it must be denormalized to align its digits with the digits of the larger addend. In otherwords, the two addends must have the same exponent before their fractions can be added. This process can be describedby the following algorithm:I) Unpack Al to get SFI and EI2) Set implicit bit in SFI3) Unpack A2 to get SF2 and E24) Set implicit bit in SF25) If E2 > EI then go to step 9CIIAIII ::5 IIA211)6) Let DIFF = EI - E27) Do i = I to DIFFSF2 = RSHFT(SF2) (Arithmetic right shift)Enddo8) Let E3 = EI , go to step 12(11A211 > IIAIII)9) Let DIFF = E2 - EI10) Do i = I to DIFFSFI = RSHFT(SFI) (Arithmetic right shift)EnddoII) Let E3 = E212) SF3 = SFI + SF213) Test "overflow" into bit 2414) Jump if false to step 17IS) Increment exponent E316) Normalize signed fraction with right arithmetic shift17) Clear implicit bit18) Pack: SUM = SF3 or E319) ReturnRegister assignments for variables must now be made. Since FSIN uses registers in the lower half of the' AS888register file, it is necessary to use the upper registers:RF = SUMRE = AI, FI, SFIRD = A2, F2, SF2RC EIRB = E2...VJ.....oc.Q)a:c:o"';:CO"~C.c.«3-131

By slightly reorganizing the sequence to better fit • AS888/890 operations, the following microprogram to performFADD can be created: .FADD: SUBROUTINE; I) Unpack Al to get SFI and EIRC = FEXP(RE)RE = FRAC(RE)2) Set implicit bit in SFIMQ = RE OR BIT23RE = SMTC(RE)3) Unpack A2 to get SF2 and A2RB = FEXP(RD)RD = FRAC(RD)4) Set implicit bit in SF2RD = RD OR BIT23RD = SMTC(RD); Get cxponent (EI); Get signed fraction (SF I); Set implicit bit; Convert to two's complement; Get exponent (E2); Get signed fraction (SF2); Set implicit bit; Convert to two's complement; '5) If E2 > EI then go to step 9RF = RC - RB : TEST NEGATIVE ; Compare A2 from A 1JT FADDI : RCA = # 8; Jump if E2 > EI; set up loop count6) Let DIFF = EI - E2.Y IRF = SLC(RF) : LOOP RCARCA = Y/RF7/ Do i = I to DIFFSF2 = RSHFT(SF2)EnddoRD = SRA(RD) : LOOP RCA8) Let E3 =EI, go to step 12RB = RC : JUMP FADD2; 9) Let DIFF = E2 - E IFADDI: RF = NOT(RF)Y IRF = SLC(RF) : LOOP RCARCA = Y/RF;\0) Do i = I TO DIFFSFI = RSHFT(SFI)EnddoRE = SRA(RE) : LOOP RCA; Rotate 8 times to get difference; Load difference in loop counter; Orient digits of smaller addend; Swap registers and branch; Complement result of E I - E2; Shift 8 times to get DIFF; Load DIFF in loop counter; Align SFI with SF2; II) Let E3 = E2 (no' instruction required - RB already has E2 in it);12) SF3 = SFI + SF2FADD2: RF = RD + RERF = SMTC(RF); 13) Test "overflow" into bit 24RF = TBO (RF, BIT24);14) Jump if false to step 17JF FADD3; 15) Else increment exponentINC RB : TEST NEG; 16) Normalize signed fractionRF = SRA(RF) : JT ERROR; Add; Convert to sign-magnitude; Check for normalization; If so, finish and exit; Test for exponent overflow; Jump to error handler if overflow3-132

; 17) Clear implicit bitFA003: RF = SETO (RF, BIT23);18) Pack: SUM = SF3 OR E3RF = RF OR RB : RETURN; Reset bit 23 of RF; OR signed fraction and exponentThere is an important consequence of FAOO which impacts the hardware. Since the number of shifts required to denormalizethe small addend is data dependent (computed in the ALU), it is necessary to provide a path between the ALU Y bus andthe' AS890 ORA bus. All the other operations are simple' AS888/890 instructions, including the FRAC and FEXP maskoperations discussed during the development of FMUL. ERROR is a floating-point overflow error handler.STEP 8: EVALUATE TRADE-OFFS AND BLOCK DIAGRAM THE HARDWAREA rough estimate of the FSIN worst case execution time can be arrived at by making the following observations aboutFSIN, FMUL and FAOO:FMULinteger recursion :::: 22 cyclesother instructions :::: 18 cyclestotal :::: 40 cyclesFAOOdenormalization :::: 23 cyclesother instructions :::: 25 cyclestotal :::: 50 cyclesFSINnumber of calls to FMUL = 12number of calls to FAOO = 11number of other cycles :::: 10Approximate worst case total = 10 + (12 X 40) + (11 x 50) = 1040 cycles. At 50 nanoseconds per cycle, thisrequires approximately 52 microseconds. There are few improvements that could be made in hardware to speed this time,except perhaps the addition of a flash mUltiplier which would reduce the integer computation by about 20 cycles (an overallreduction of about two percent). A barrel shifter could have the same benefit during floating-point addition for a total reductionof about 4 percent. For the sake of simplicity, it will be assumed that 52 microseconds is acceptable for the sin(x) computation.Another issue which must be considered is the problem of loading the' AS888 and' AS890 with constants. A slight materialscost reduction might be realized by storing constants in table PROMs rather than in control store memory. An interestinguse of the ORA and ORB ports on the 'AS890 would be to use the output of RCA or RCB to index data in the constantPROM. This would allow long series to be implemented in loop form rather than the inline method used in FSIN. Onceagain, the constant PROM will not be implemented for the sake of simplicity.Now the architecture can be designed to meet the requirements identified throughout this analysis:I) A path between the' AS888 Y bus and the' AS890 ORA bus.2) A path between the microinstruction register and the' AS890 ORA bus for loading loop counts and branchaddresses.3) A path between the microinstruction register and the' AS888 Y bus for loading constants.4) Independent control of SIOO in each' AS888 slice to allow bit/byte instructions.5) A status register to store' AS888 status for testing.6)A status mux to test the' AS888 status, bit 23 of the' AS888 Y bus, bit 24 of the' AS888 Y bus and hardwiredo and I.A system having these features is illustrated in· Figure 6- I .C/)~~oc.Q)a:co'';:CO,2C.c.

STEP 9: DEFINE MICROINSTRUCTION FIELDS DURING DETAILED HARDWARE DESIGNThe detailed hardware design will produce a wiring diagram that fixes the position within the microinstruction of eachof the various control signals that are connected from the microinstruction register to the' AS888, 'AS890, status mux andany other special hardware. Once this design is complete it is possible for the assembler to sort the control bits of each instructionproperly so that they will be properly oriented when the microprogram is installed in the target system.STEP 10: ASSEMBLE THE MICROPROGRAMTI is currently developing an 'AS888/890 microasscmbler. Several microassemblers arc commercially available, andmany users prefer to write their own. The microprogram shown in Table 6-1 was hand-assembled, but has a syntax thatis suitable for interpretation by a user-written assembler.SYSTEM INTERFACE.,,-tl::-.....::..:...:..::....-----------.! DRA7·DRAOALS1511/8'ALS 374:AS890YCCDADB'AS888 (4)~~--~----~--~CLK20MHz>------------__ ~-~MICROINSTRUCTIONREGISTER'ALS 374 (14)108·USE 'ALS374 OUTPUT CONTROL FOR BUFFERINGMICROPROGRAMMEMORY(16Kxl08)14Figure 6-1. Block Diagram of Floating-Point Processor3-134

Table 6.1. Floating Point Sin (x) Microprogram0000 SIN:000100020003000400050006000700080009OOOAOOOBOOOC0000OOOEOOOF0010001100120013001400150016001700180019001A001B• SIN1:001C SIN1:0010001E001F00200021002200230024• SIN2:0025 SIN2:002600270028• Rl = FSGN(RO)Rl = RO AND #8000 OOOOh• R2 = FABS(RO)R2 = ROR2 = RO SETO # 80h : BYTE = # 1 OOOb• R3 = FMUL(R2.10VR2PI)RE = R2RD = #3EA2 F984hJSR FMULR3 = RF• R3 = FINT(R3)RF = R3JSR FINT [EXERCISE FOR READER)R3 = RF• R3 = FMUL(R3.2PI)RE = R3RD = #40C9 OFDBhJSR FMULR3 = RF• R3 = FADD(R2.INV(R3))RE = R2RD = R5 XOR #8000 OOOOhJSR FADDR3 = RF• Y = FADD(R2.NEGPI)RE = R2RD = #C059 OFDBhJSR FADDY = RF : TEST NEGJT SINl• Rl = FINV(Rl)Rl = Rl XOR #8000 OOOOh• R3 = FADD(R3.NEGPI)RE = R3RD = #C059 OFDBhJSR FADDR3 = RFY = FADD (PIOVR2.INV(R3)) : TEST NEGRE = #3FC9 OFDBhRD = R3 XOR #8000 OOOOhJSR FADDY = RF : TEST NEGJT SIN2• R3 = FADD(PI.FINV(R3))RE = #4059 OFDBhRD = R3 XOR #8000 OOOOhJSR FADDR3 = RFR4 = FMUL(RO.RO)RE = RORD = ROJSR FMULR4 = RF0~g8 ~ >~ 0~~ao~i9~~S::U332·bit... Constant~~~~00X10211 1 00 FA 80000000 1 1 1 1 027XXXXl 1 1 700X20Xl 1 1 0 0 F 6 XXXXXXXX 1 1 1 100280011 1 0 0 1 8 XXXXXXXX 11 1 002XEOXl 1 1 o 0 F 6 XXXXXXXX 1 1 1 1OXXDXXl 1 1 1 X F F 3EA2F984 1 1 1 1lXXXXXl 1 1 X X F F XXXXXXXX 1 1 1 1OFX30X1 1 1 0 0 F 6 XXXXXXXX 1 1 1 103XFOXl 1 1 0 0 F 6 XXXXXXXX 1 1 1 1lXXXXXl 1 1 X X F F XXXXXXXXl 1 1 1OFX30X11 1 o 0 F 6 XXXXXXXXl 1 1 103XEOX1 1 1 o 0 F 6 XXXXXXXXl 1 1 1OXXDXX1 1 lOX F F 40C90FDB1 1 1 11XXXXX1 1 1 X X F F XXXXXXXX1 1 1 1OFX30X11 1 0 0 F 6 XXXXXXXX1 1 1 102XEOX1 1 1 0 0 F 6 XXXXXXXX 1 1 1 105XD021 1 1 0 0 F 9 80000000 1 1 1 11XXXXX1 1 1 X X F F XXXXXXXX 1 1 1 1OFX30X11 1 0 0 F 6 XXXXXXXX 11 1 102XEOX1 1 1 o 0 F 6 XXXXXXXX 1 1 1 1OXXDXX1 1 1 0 X F F C0590FDB 1 1 111XXXXX1 1 1 X X F F XXXXXXXXl 1 1 1lFXXOXl 1 o 0 0 F 6 XXXXXXXX 1 1 1 1lXXXXXll 1 X X F F XXXXXXXX 1 1 11o 1 X 1 0 2 1 1 1 0 0 F 9 80000000 1 1 11 027XXXXll 1 703XEOX11 1 0 0 F 6 XXXXXXXX 11 1 103XDXX1 1 1 1 X F F C0590FDB 1 1 1 1lXXXXXl 1 1 X X F F XXXXXXXX 1 1 1 1OFX30Xll 1 0 0 F 6 XXXXXXXX 1 1 11OXXEXX1 1 1 1 0 F 6 35C90FDB 1 1 1103XD021 1 1 0 0 F 9 80000000 1 1 11lXXXXX11 1 X X F F XXXXXXXXl 1 1 1lFXXOXl 1000F6 XXXXXXXX 1 1 1 1lXXXXX11 1 X X F F XXXXXXXX 1 1 1 1OXXEXX1 1 1 1 0 F 6 40590FDB 11 1103XD021 1 1 0 0 F 9 800000001 1 1 1lXXXXXl 1 1 X X F F XXXXXXXX 1 1 11OFX30Xl i 1 0 0 F 6 XXXXXXXX 1 1 11OOXEOXll 1 0 0 F 6 XXXXXXXX 1 1 1 100XDOX1 1 1 0 0 F 6 XXXXXXXX 1 1 1 1lXXXXX1 1 1 X X F F XXXXXXXX 1 1 1 1OFX40X1 1 1 0 0 F 6 XXXXXXXX 1 1 110>

Table 6.1. Floating Point Sin (x) Microprogram (Continued)0U.0:=~g8 ~ I%I>~I~ ~ IU oJ1~":''':'OI

Table 6.1. Floating Point Sin (x) Microprogram (Continued)0056005700580059005A005B005C005D005E005F0060 FMUL:006100620063006400650066006700680069006A006B006C006D006E006F0070 FMUL1:0071• R5 = FADD(R5.A0)RE = R5RD = #3F80 OOOOhJSR FADDR5 = RF• R5 = FMUL(RO,R5)RE = RORD = R5JSR FMULR5 = RF• R5 = FCHS(R5,R1) : RETURNR1 = R1 OR #7FFF FFFFhR5 = R5 XOR R1 : RETURN* RC = FEXP(RE)RC = RE AND#7F80 OOOOh* RE = FRAC(RE)RE = RE AND #807F FFFFh* RE = RE OR bit23RE = RE OR #0080 OOOOh* MO = SMTC(RE)RE = SMTC(RE)LOADMO : PASS* RB = FEXP(RD)RB = RD AND #7F80 OOOOh* RD = FRAC(RD)RD = RD AND #807F FFFFhRD = RD OR bit23RD = SMTC(RD)RE = 0 : RCB = #22DRE = SMUll RD : LOOP RCBRE = SMULT RDTBO(RE,bit1) : BYTE=#0100b: TEST ZJT FMULl* IN EX RCRC = RC ADD #0080 OOOOhRE = SRA(RE)RC = RC ADD" RB : TEST CARRYJT ERROR0072 RE = SMTC(RE)0073 RE = RE AND #807F FFFFh* FADD: RC = FEXP(RE)0074 FADD: RC = RC AND #7F80 0000* RE = FRAC(RE)0075 RE = RE AND #807F FFFFh0076 MO = RE OR bit230077 RE = SMTC(RE)* RB = FEXP(RD)0078 RB = RD AND #7F80 00000~g8 ~ aI>~I~ ~ ~ Ol~ ffi~~ ~ ~ c30....05XEOX1 1 1 0 0 F 6 XXXXXXXX 1 1 1 1 027XXXX1 1 1 7OXXDXX1 1 1 1 X F F 3F800000 1 1 1 1 027XXXX1 1 1 71 XXXXX 1 1 1 X X F F XXXXXXXX 1 1 1 101400741 11 7OFX50X11 1 0 0 F 6 XXXXXXXX 11 11 027XXXX1 1 1 700XEOX1 1 1 0 0 F 605XDOX1 1 1 0 0 F 61 XXX XX 1 1 1 X X F FOFX50X1 1 1 0 0 F 6o 1 X 1 0 2 1 1 1 o 0 F B0515001 1 1 o 0 F 0OEXC021 1 1 o 0 FA 7F800000 11 1 1 027XXXX1 1 1 7OEXE02 1 1 1 00 FA 807FFFFF 1 1 11 027XXXX1 1 1 7OEXF021 1 1 0 0 F B 00800000 1 1 11 027XXXX1 1 1 7OXEEX01 1 1 1 o 5 81EXXOX1 11 1 0 E 6ODXB021 1 1 00 FA 7F800000 1 11 1 027XXXX1 1 1 7ODXD021 1 1 00 FA 807FFFFF 11 1 1 027XXXX1 11 7ODXD021 1 1 0 0 F BOXDDX01 1 1 1 D 5 8OEEE001 1 1 1 0 F 9ODEE001 1 1 1 060ODEE001 1 1 o 0 7 000FOO011 1 1 0 3 81XXXXXX1 1 1 X F FOCXC021 1 1 o 0 F 1OEXEOX1 1 1 o 0 0 6OCBC001 1 1 o 0 F 11 XXX XX 1 1 1 X X F FOXEEX01 1 1 1 0 5 8OEXE021 1 1 0 0 FAOCXC021 1 1 o 0 FA 7F800000 1 11 1 027XXXX1 1 1 7OEXE02 1 11 o 0 FA 807FFFFF 1 1 11 027XXXX1 1 1 71 E X X 0 1 1 1 1 o 0 E BOEXE021 1 1 00 FA0>

Table 6.1. Floating Point Sin(x) Microprogram (Continued)0079007A007B007C007D007E007F008000810082 FADD1:0083008400850086 FADD2:008700880089008A0089008C FADD3:008D• RD = FRAC(RD)RE = RE AND #807F FFFFhRD = RD OR bit23RD = SMTC(RD)RF = RC - RB : CO=O: TEST NEGJT FADD1 : RCB = #8Y/RF = SLC(RF) : LOOP RCBY = RF : RCA = YRD = SRA(RD) : LOOP RCARB = RC : JUMP FADD2RF = NOT RFY/RF = SLC(RF) : LOOP RCBY = RF : RCA = YRE = SRA(RE) : LOOP RCARF = RD + RERF = SMTC(RF)RF = TBO (RF. bit24) : TEST ZJF FADD3INC RB : TEST NEGRF = SRA(RF) : JT ERRORRF = SETO (RF. bit23)RF = RF OR RB : RETURNI~~~~0 o:!:000 ffil ~No0

Excerpt froInSN74AS888, SN74AS890Bit-Slice ProcessorUser's GuideTEXASINSTRUMENTSrJ)....,-.oCoQ)a::r:::o"';:co"~c..Co

IMPORTANT NOTICETexas Instruments (TIl reserves the right to make changes in thedevices or the device specifications identified in this publicationwithout notice. TI advises its customers to obtain the latest versionof device specifications to verify, before placing orders, that theinformation being relied upon by the customer is current.TI warrants performance of its semiconductor products to currentspecifications in accordance with TI's standard warranty. Testing andother quality control techniques are utilized to the extent TI deemssuch testing necessary to support this warranty. Unless mandatedby government requirements, specific testing of all parameters of eachdevice is not necessarily performed.In the absence of written agreement to the contrary, TI assumes noliability for TI applications assistance, customer's product design, orinfringement of patents or copyrights of third parties by or arising fromuse of semiconductor'devices described herein. Nor does TI warrantor represent that any license, either express or implied, is grantedunder any patent right, copyright, or other intellectual property rightof TI covering or relating to any combination, machine, or process inwhich such semiconductor devices might be or are used.Copyright © 1986, Texas Instruments Incorporated3-140

4. 32-Bit CPU Design MethodologyMicroprogramming and bit-slice technology have made possible the development ofpowerful systems using flexible instructions sets and wide address/data buses toaccess more than one Gigaword of physical main memory. This section discussesone design approach to such a system, using , AS888 bit-slice and, ' AS890microsequencer components.A structured approach to system design, such as that illustrated in Figure 4-1, isrecommended in developing custom bit-slice designs. The product specification givesa starting point or basis for the project. In this example, four' AS888 bit slices areused to implement the 32-bit arithmetic portion of the CPU, and an ' AS890microsequencer is used for ALU and system control. A group of PROMs stores themicroinstructions; a writable control store could also be implemented using additionalcontrol logic and components to load and modify the microprogram memory. Thesystem is designed to accesS more than one Gigaword of memory ....--___ ,/ PRODUCT SPECIFICATION.0BLOCK DIAGRAM/MACRO INSTRUCTION FORMATSoAMICROMAP FOR DATA PATH CONTROL ,y.-__---.VMICROCODE DEFINITIONS.0MICROCODE FLOW CHARTS-0 AL..-___ ---I MICROCODE PROGRAMMING

Control, data and address buses shared by the system are accessed by three-stateregisters. The control register, as explained in section 4.1.2, supplies the non-CPUpart of a computer system with control signals. The data bus allows the ALU to supplydata for the rest of the system and can also be a source of data for the ALU; thisis accomplished by using three-state registers to drive the bi-directional data bus, alongwith registers to sample the bus. The address bus uses one of the external registerfile locations to maintain a program counter, thus allowing a 32-bit address bus capableof addressing about four Gigawords of main memory. Using three-state drivers ·forthis bus enables other subsystems to take control of the system buses.A pipeline register supplies the microsequencer and the ALU with both data andinstructions. To get macrocode into the system, an instruction register and a mappingPROM are used to convert the opcode to a microprogram routine address. Thecondition code signal, used for testing various conditions, is supplied by a registerinputbased PAL. PAL inputs can be fixed values or combinations of the status signalscoming from the ALU. The read address select pins for the' AS888's internal B registercan be sourced from the microword itself or from three nibbles of the macroword,to provide offsets for the N-way branches to various microcode routines.4.1 Designing a 32-Bit System4.1 .1 Construction qf the AlUA typical 32-bit system block diagram using the 'AS888 bit-slice and 'AS890microsequencer is shown in Figures 4-2 and 4-3. It can be broken down into twosections, the ALU (arithmetic logic unit) and the CCU (computer control unit). TheALU section performs all manipulation of data both to and from main memory, suchas arithmetic and logical operations. The CCU section controls instruction (macrocode)flow and any miscellaneous control operations, such as fetching instructions orsupplying addresses for main memory access.To cascade the four' AS888s to obtain the 32-bit arithmetic unit shown in Figure 4-4,the shift multiplex SIOO and 0100 terminals are connected to the SI07 and 0107terminals of adjacent packages, and the least significant package's signals areconnected to the most-significant package's. Optionally, SN74ALS240 inverting gatescan be connected to the S100-S107 terminals and the byte inputs to implement byteand bit control. Another chip, the SN74AS182 look-ahead carry generator, providesa ripple-carry function, to help system throughput.The design includes a 16-word register file, the SN74AS870 (see Figure 4-3).Thisallows the user to access 16 working areas for temporary data storage or addresscalculations such as indexing. In this design example, the' AS888's internal registerfile is not accessible directly by the user; it is reserved for microcode operations, suchas address computation and temporary storage for arithmetic operations. Addressingthe register files is permitted through the microprogram or from the macrocodeinstruction register under microcode control.The transfer register connected to the' AS888's Y and DB buses allows for feedbackinto the 'AS888 under microprogram control. Since the constant PROMs and theexternal register file share the A bus, they cannot be accessed at the same time. Thetransfer register enables data from the external register file to be transmitted to theB bus, making possible the addition of operands from the constant PROMs and theexternal register file, for example.Constant PROMs are also included to simplify the programming and operation of theALU by supplying fixed data for various operations, such as:3-142

4.1.2 Construction of the CCU1) Clearing the system register files for initialization. This will bring the system upto a known state.2) Supplying a correction value to the offset in a branch instruction, i.e., convertinga 16-bit offset to a true 32-bit address.3) Table look-up for fixed mathematical operations, such as computing sines andcosines.Sequencing and branching operations at speeds compatible with the ' AS888 aresupplied by the ' AS890, a microprogrammed controller working as a powerfulmicrosequencer (see Figure 3-1). Features of the' AS890 include:1) Stack capability. The 9-word stack can be accessed by using a stack pointeror a read pointer; the latter is designed for non-destructive dumping of the stackcontents.2) Register/counter facility. Two registers, ORA and ORB, can be used for latchingdata from the external data buses or as counters for loops. A ZERO signal isgenerated when the decremented counter reaches a zero value.3) Interrupt control. A register for temporarily holding the return address is supplied;upon entering the interrupt routine, the contents of the return register must bepushed onto the stack for later use.4) Next address generation. The Y output multiplexer offers a selection of sameor incremented address, address from ORA or ORB buses, address from stack,or a concatenation of ORA 13-0RA4 and B3-BO.A microprogram memory/pipeline register supplies the microsequencer and the restof the system with instructions (see Figure 4-2). The memory might consist of ROMs,or it could be a writable-control store with support logic to allow loading or updatingof the control store. For a general purpose machine with a fixed instruction set, ROMswould be more economic.Some' AS890 instructions are influenced by the CC input. Many are variations ofbranch and jump instructions. To form and supply CC, a register can be used to latchthe state of the' AS888 and supply inputs to a PAL for decoding, based upon themicrocode's needs. Combinatorial logic in the PAL allows multiple or single eventsto be selected or provides a fixed value of "1" or "0" for forced conditions.To supply the microsequencer with the proper address of the microcode-equivalentversion of the macrocode instruction, an instruction register and mapping PROM areneeded. Under microprogram control, the instruction register samples the data busto get the macrocode instruction. The opcode portion is passed to the mapping PROMto form an address to the microcode routine. When the microcode is ready to jumpto the routine, it turns off the Y bus output of the' AS890 and enables the outputof the mapping PROM. An optional means of altering the address uses B3-BO inputsof the' AS890 to implement a N-way branch routine. In this method, the ten mostsignificant address bits of ORA or ORA are concatenated with the B3-BO bits to supplyan address.Control information is supplied to the rest of the system via the control register andbus. By setting various bits within the control register, information can be passedto other subsystems, such as memory and I/O peripherals. Bit 0 could represent theread/write control line while bit 1 could select memory or I/O for the read/write. Bit 2might function to enable interrupts and bit 3 to indicate when the system should entera "wait" state for slow memory. The remaining control bits can be programmed bythe system designer to indicate additional condition states of the "macrosystem".IIen+""...oc.0)a:c:o"+iCO"~C.c.

Cf+:+:-s~JodaH UO!~e:>!ldd" .•14MICRO CONTROL BUSTO FIGURE 4-3MICROPROGRAMMEMORY'AS888 STATUS2TOr-______ ~iR~~~~ER12INSTRUCTIONREGISTERAS373(4)CONTROLREGISTORAS373(1)32 DATA BUS32 ADDRESS BUSCONTROL BUSFigure 4-2. CCU Block DiagramTO FIGURE 4-3TO FIGURE 4-3TO FIGURE 4-3

FROM FIGURE 4-2 /MICRO CONTROL BUS32 BBUS ~I32 ABUS321 32 T ~'AS888 STATUS - '4 ALU ICONSTANTI'AS888(4)PROMC ' (SEE FIGURE 4-4)n"{12 I 1-0F-2 LTO REGISTER"· I SELECTOR JFILES,12 8 L 74AS157(1), 32J.1.- 32TRANSFERREGISTER74AS373(4)1.-32I321.1 16-WORD I'4 1 REGISTER FilE74AS870(8)t. 32If32l "~321DATA-INREGISTER74AS373(4)I IDATA-OUTREGISTER74AS373(4)I I321MEMORYADDRESS REGISTER74AS373(4)IYBUS,FROM FIGURE 4-2,'32 DATA BUS"FROM FIGURE 4-232 ADDRESS BUSFROM FIGURE 4-2 >CONTROL BUS32 321.-32~Cf......j:>.(11Application Reports IFigure 4-3, ALU Block Diagram

Addressing of the register files, both the' AS888 internal and the' AS870 external,is done through the use of two 1-of-2 selector banks. The first bank selects addresssource; this design offers a choice for operand processing of fixed values from themicrocode or values from the macroinstruction latched in the instruction register. Thesecond bank selects the first or second operand as an address source for port 0 ofthe external register file; port 1 uses the third operand as an address source.It should be noted that the design presented in Figure 4-2 for the computer controlunit is a one-level pipeline that is instruction-data based.The address and contentsof the next instruction are being fetched while the current instruction is being executed.Tracing through the data flow, the following can be observed:1) The pipeline register contains the current instruction being executed;2) The ALU has just executed its instruction, and has the current status ready atits output pins;3) The status register that is attached to the ALU contains the previous instruction'sresulting status;4) The contents of the next microprogram word are being fetched at the same timethat the current instruction is being executed.4.2 Tracing through a 32-Bit ComputerWith the' AS888 and 'AS890 as foundation chips, the typical 32-bit supermini ofFigures 4-2 and 4-3 can now be functionally traced. First, note that the data of themain program is handled separately from that of the microcode - each on its ownbus. The system is initialized by setting the "clear" signal high - this causes a forcedjump to the beginning of the microcode memory. Instructions carried out by themicrocode at this point might run system diagnostics, clear all registers throughoutthe' AS888-based system, and set up the initial macrocode program address. In thisdesign, the first program address to fetch an instruction from main memory comesfrom a fixed value in the microcode memory; it is possible to allow the address tobe retrieved from a permanent location in main memory or from either a front panelor console, by modifying the microcode program slightly.Table 4-1 illustrates the microcode format for this design. Note that it contains controlsignals for all chips involved in the design. Some of these, such as TRANSLATCHand MARLATCH, are used with the system clock to provide controlled loading of thevarious holding registers. Others supply necessary addressing information, directinginput from either the main data bus or from the microcode word itself.The FETCH routine is shown in functional, assembler and microcoded forms in Tables4-2, 4-3 and 4-4. First, the program counter is read from the external register fileand stored into the memory address register. After the program counter is placed onthe address bus, the program counter is updated and stored while the data frommemory is allowed to settle down to a stable condition. The data is then latched inboth the instruction register and data-in register.The opcode field of the instruction register is passed through the mapping PROM toconvert the opcode to an equivalent microcode routine address. When YOE is forcedhigh by the microcode, the 'AS890 is tri-stated from the Y bus, and the mappingPROM's output is taken out of the tri-state mode to supply an address to the controlstore (microprogram memory); a forced jump is made to the microcode routine toperform the instruction.After the routine is complete, a jump is made back to the FETCH routine using thenext-address supplied by the microprogram. It is up to the systemdesigner/programmer to make sure that all system housekeeping is performed so thatnothing causes a fatal endless loop.3-146

I132 ""'\I'32.r:+5V -=PPPJ'AS888ZEROZERO-SSFCn+8-Cn +8--~-r---- SI07 5100IQI07 GlOOGP"B-BUS- - --A-BUS""'\-E' -£ ~PPPI~ I~~PPPI~~ PPP ~ I~"b-_ 'AS888'AS888'AS888"h-~l>-~ 1>-ZERO ZERO ZEROSSF I- SSF I--- SSF- Cn+8 Cn i- - Cn +8 ~r- - Cn +8 C n I---i-SI07 SIOO SI07 SIOO SI07 SI00r--QI07 QIOO QI07 QIOO QI07_QIQO~G P G P G P"-zl0 zi= 0is i=

MICROCODEFIELDTable 4-1. Microcode DefinitionPIN NAME INPUT TO FUNCTION0-13 DRA13-DRAO 'AS890 Used for next-address branches14-27 DRB13-DRBO 'AS890 Used for loading counter28-30 RC2-RCO 'AS890 Register/counter controls31-33 S2-S0 'AS890' Stack control34-36 MUX2-MUXO 'AS890 MUX control of V output bus37 INT 'AS890 Interrupt control38 RAOE . 'AS890 Enables DRA output39 RBOE 'AS890 Enables DRB output40 OSEL 'AS890 Mux control for DRA source41 INC 'AS890 hlcrementer control42 VOE :.\S890 Enables V output bus43-50 17-10 'AS888 Instruction inputs51 OEA 'AS888 DA bus enable52 EA 'AS888 ALU input operand select53 OEB 'AS888 DB bus enable54 OEV 'AS888 V bus output enable55 SELV 'AS888 V bus select56--57 EB1-EBO 'AS888 ALU input operand selects58 WE 'AS888 Register file write enable59 MAP PROM Enables mapping PROM to 'AS890 V bus60 iR Latch Latches data bus to instruction register61 CR Latch Latches control data to bus62-69 CTRL7-CTRLO Latch Data for control latch70-71 BSEL 1-BSELO Multiplexer Selects data for 'AS89072-75 B3-BO MUltiplexer Microcode data to switch76 CONDCD Latch Controls latch of 'AS888 status77-80 SELC3-SELCO PAL Selects combination of 'AS888 status81 DTALATCHI Latch Controls latching of data-in82 DTAIN Latch Enables data-in output to bus83 DTALATCHO Latch Controls latching of data-out84 DTAOUT Latch Enables data-out output to DB bus85 MAR LATCH Latch Controls latching of address86 MAR Latch Enables MAR output to address bus87 CONSTPROM PROM Enables PROM to DA bus88-99 A11-AO PROM Address of constant in PROM100 SWITCH2 Multiplexer Selects microcode or Instruction Register data101 SWITCH1 Multiplexer Selects microcode or Instruction Register data102-105 A3-AO Multiplexer Register file address ('AS888)106--109 B3-BO Multiplexer Register file address (,AS888)110-113 C3-CO Multiplexer Register file address ('AS888)114 REGUWR Register File Port 0 write enable115 REGLWR Register File Port 1 write enable116 REGU Register File Chip .enable on port 0117 REGL Register File Chip enable on port 1118 TRANSLATCH Latch Controls latch between V and DB bus119 TRANS Latch Enables output to DB bus120 SELCN2 MUltiplexer Supplies carry input to 'AS888121 SELCN1 Multiplexer Supplies carry input to 'AS888122 REGUB Multiplexer Selects address for external register file123-126 BVTE3 - BVTEO Three-state Enables data for byte/bit operations3-148

Table 4-2. Functional Listing of FetchFETCH:MAR = PC, Enable MAR outputPC = PC + 1IR = DIR = data bus, Disable 'AS890 Y bus,Enable mapping PROM to Y busTable 4-3. Assembler Listing of FetchFETCH: OP890 ",111,10;INC;OP888 NOP.GROUP5,10",1111;OEY;SELY;CR;CTRL 00000011;SELC 01;MARLATCH;MAR;SWITCH OO;REGL;TRANSLATCHOP890 ",111,10;INC;OP888 PASS,INCS,00",1111;OEB;OEY;SELC 01;MAR;REGLWR;REGL;TRANS;SELCN 01OP890 ",111,10;OP888 NOP.GROUP5,10;MAP;IR;SELC 01DTALATCHI;MARSet 'AS890 for continuePerform NOP and read external register 15Enable Y bus outputGenerate external control bus signalsSelect fixed CC value to 'AS890Latch value on Y bus and enable outputSelect address source and enable portLatch Y bus for transfer to B busSet 'AS890 for continueIncrement program counterEnable Y bus outputSelect fixed CC value to 'AS890Output address to address busUpdate program counter in register fileEnable transfer latch output to B busSelect, carrv input to LSP to be "1"Set 'AS890 for continuePerform NOPEnable mapping PROM to 'AS890 Y busLatch data bus to get macro level codeSelect fixed CC value to 'AS890Put data bus also in data registerOutput address to address busKey to Table 4-3OP888 a,b,c,d,e,fwhere:upper bits of instruction, 17-14b lower bits of instruction, 13-10c = value of EB1-EBOd A address of register filesB address of register filesC address of register filesOP890 V,W,X,V,Zwhere:v ORA value, 14-bitsw ORB value, 14-bitsx RC2-RCOV S2-S0MUX2-MUXOt/)....oQ.Q)a:c:o",t:iCO"~C.Q.

~U1os~JOdau uone:>!lddv I.Table 4-4. Microcode Listing of Fetch_DRAO0000000000000000000000000000DRB13-DRBO0x::J0 :!: 17-10Co)a: 0 NN en xCo) N ::Ja: en :!:I~~~~~~00000000000000 000 111 o 1 0 1 1 1 010 1111111100000000000000 000 111 o 1 0 1 1 1 010 1 1 1 1 0 1 0000000000000000 00000000000000 000 111 o 1 0 1 1 1 00 1 11111111l~-mW~ ~~~ffi ~ 1~g;j51 1 1 0 1 1 0 1 1 1 011000001 111o 1 1 1 1 1 0 1 001Table 4-4. Microcode Listing of Fetch (continued)DRA13-xCTRL7-3o:!:~§:l:W~enCTRLO~...JoW a!a!ena IIWenM~Wen II~i~i JI Co)enA11-AON:l:a:enenN-a!~I~~o o§ ~ a!Co)C") Men < a! !3 III~ J~U~~I~00000011 000000000000 111001000111100000000 000000000000 101010010111100000000 000000000000 111111000 1111

4.3 Defining the Macrocode Instruction FormatSince this is a 32-bit design, a variety of instruction formats are available. The sizeof the opcode, along with the types of addressing used, will affect both system sizeand performance. The formats shown in Table 4-5 will be used for discussion.All Table 4-5 formats have an opcode field of 11 bits and source/destination fieldsof 7 bits; the first three bits of the latter designate the address type, and the remainingfour bits are used for register access. The opcode length allows 2,048 macrocodedinstructions to be mapped to equivalent microcoded routines. The address fields canspecify any of the following modes: register, relative, autoincrement/autodecrement,indexed, absolute, and deferred. The offset used in the Type 0 instruction can be usedfor branch-based instructions, for an offset range of ± 32727.Table 4-5. Possible Instruction FormatsTYPE 0 -OPCODE + 16·BIT OFFSET0-10Opcode11-15Not Used16-31OffsetTYPE 1 -OPCODE + DESTINATION0-10Opcode11-24Not used25-31DestinationTYPE 2 -OPCODE + SOURCE + DESTINATION0-10Opcode11-17Not used18- 24Source25-31DestinationTYPE 3 -OPCODE + SOURCE1 + SOURCE2 + DESTINATION0-10Opcode11-17Source18-24Source25-31Destination4.4 Tracing a Macrocode InstructionMicrocode for a Type 3 multiplication instruction is shown in Table 4-6, using thefollowing assumptions:1) Code for retrieving the operands will not be shown. Jumps will be made toroutines that will place the temporary operands into internal register locations2 and 3 of the' AS888, after being fetched from main memory.2) A jump to a routine to store the product in the destination will be handled similarly.3) Multiplication will be unsigned; the result will be placed in two temporarylocations of the' AS888.4) An update to the program status word, which the user can access at the macrocodelevel must also be performed, but is not shown.Assembler code is shown in Table 4-7; a microcode listing is given in Table 4-8. Thefirst two lines of microcode are subroutine jumps to opcode fetching routines, whichstore the operands in register files 2 and 3 in the' AS888. The next two instructionsload up the' AS890 with a counter constant for performing the mUltiply loop, loadthe MQ register of the ' AS888 with the multiplier and clear the register that istemporarily used for the accumulator.IIC/).....lIo.oC.Q)a:t:o"';;CO"~Q.c.

Table 4-6. Functional Listing of MultiplyUMULl3:JUMPSUB SOURCE1JUMPSUB SOURCE2,BCOUNT=32REG 9=0MQ=REG 2LOOP:UMULI WITH REG 3DECREMENT BCOUNT,BRANCH TO LOOP IF NOT ZERO,LATCH 'AS888 STATUS,REG 9=ALUREG 8=MQJUMPSUB STORPSWJUMPSUB MDESTJUMP FETCHGet first operandGet second operandLoad DB counter registerClear temporary accumulatorLoad multiplierIssue the mUltiplyDecrement the DB counterLoop back until doneStore 'AS888 flagsStore intermediate resultStore intermediate resultUpdate macro program statusStore result at destinationGet next instruction4.5 System EnhancementsA loop is then entered to perform the multiply instruction 32 times to form the product,with the multiplicand coming from the internal register file of the' AS888. Upon exitingthe loop, the MQ register is stored in a temporary register location in the' AS888.The MQ register now contains the least-significant bits of the result and the temporaryaccumulator the most significant bits. A subroutine jump is made to the program statusword update routine; this will take the status flags of the last multiplication iterationand change the macrolevel status word. The next subroutine jump is to a destinationroutine, which is followed by a branch to the FETCH routine to get the next macroinstruction to be executed.The above example provides a broad overview of 32-bit system design using the'AS888 and' AS890. Certain additional options may enhance system performance.These include:1) Status latching. The design does not take into account changes that need tobe examined at the micro level while retaining macrolevel status information. Onesolution would be to include another register in parallel to the status latch andprovide control to choose between the two to form the condition code value.2) Interrupts. To efficiently use a computer system, interrupts are used to alterprogram flow in the case of I/O programming and real-time applications (involvinghardware timers). To include this capability, external hardware must be includedand the microcode modified accordingly. Information on interrupt implementationis given in section 3.3) Control store. One way of implementing microprogram memory is to use a ROMbaseddesign. It is becoming more common to design a writable control store,a completely RAM-based or part RAM, part ROM storage system, that can bealtered by system operation, such as initialization from a floppy disk subsystem,or by the user to optimize or implement new macrolevel instructions. The costof implementation must be weighed with the risks involved in changinginstructions which may not be supported by other sites.4) Instruction word definitions. Changing the instruction word definitions will havean effect on both system design and performance. Removing Type 3 instructionsfrom the design, for example, will have an effect on both hardware and software:the external register file addressing must be changed and the 1,-of-2 selector3-152

Table 4-7. Assembler Code of MultiplyUMULl3:OP890 SOURCE1 ... ll0.ll0;INC;YOE;OP888 NOP;GROUP5;SELC 0001;Perform a subroutine branchIncrement address and enable Y busTell 'AS888 to do nothing during jumpSet CC to "1" to set up 'AS890 continueMARMaintain address on main address buss~OP890 SOURCE2.00000000l00000.ll0.ll0.ll0; Perform subroutine branch and load BLOOP:INC;YOE;OP888 NOP.GROUP5;SELC 0001;MAROP890 ... 111.110;INC;YOE;OP888 CLEAR.GROUP5 .... 1 001;WE;SELC 0001;MAROP890 LOOP. .. lll.ll0;INC;YOE;OP888 LOADMO.INCS ... 0010;MAROP890 LOOP..l0l.111.100;INC;YOE;OP888 UMULI.GROUP4.01.0011 .. 1001;WE;MAROP890 ... 111.110;INC;YOE;OP888 PASS.INCS .... l000;WE;MAROP890 STORPSW ... ll0.ll0;INC;YOE;OP888 NOP.GROUP5;SELC 0001;MAROP890 FETCH ... lll;INC;YOE;OP888 NOP.GROUP5;SELC 0001Key to Table 4-7.OP888 a.b.c.d.e,fwhere:upper bits of instruction. 17-14b lower bits of instruction. 13-10value of EB1-EBOd A address of register filese = B address of register filesC address of register filescounterIncrement microaddress and enable Y busTell 'AS888 to do nothing during jumpSet CC to "1" to set up 'AS890 continueMaintain address on main address busPerform a continue instructionIncrement microaddress and enable Y busZero out register file accumulatorEnable writing to register fileSet CC to "1" to set up 'AS890 continueMaintain address on main address bussPerform a continue instructionIncrement microaddress and enable Y busLoad MO register with S + Cn. from externalregister fileMaintain address on main address busDecrement B and loop til ZERO = 1Increment microaddress and enable Y busPerform unsigned multiply on accumulatorUpdate register file accu~ulatorMaintain address on main address busPerform a continue instructionIncrement microaddress and enable Y busPut S + Cn in temporarv register fileAllow updating of register fileMaintain address on main address busPerform a subroutine branchIncrement microaddress and enable Y busTell 'AS888 to do nothing during jumpSet CC to "1" for set up • AS890 continueMaintain address on main address busPerform a branch to FETCH routineIncrement microaddress and enable Y busTell 'AS888 to do nothing during jumpSet CC to "1" for' AS890 cOl)tinueOP890 v.W.x.v.zwhere:v = DRA value. 14-bitswxvDRB value. 14-bitsRC2-RCOS2-S0MUX2-MUXOIIU)....oc.Q)a:s:::o.,t:CO.2Q.c.«3-153

emoved. Likewise, changing the opcode length may restrict the instructionaddress capability and also cause either an increase or decrease in the microcodesize.5) Dynamic memory access (DMA). The above system does not support dynamicmemory access. To include this function requires a change in the address outputcontrol, along with support circuitry for the type of DMA selected. Some errordetection and correction logic for main memory might also be included.6) Computer control unit. The design presented here shows a one-level pipelinearchitecture that is instruction-data based. System throughput may be increasedby converting to a pipeline of greater depth, or using another variety of onelevelpipeline, such as instruction-address based or address-data based. Caremust be taken when increasing the size of the pipeline, especially when handlingbranch/jump situations. The reader is advised to carefully research this areabefore implementing any design.4.6 Timing and System Throughput4.6.1 Fetch AnalysisA critical path analysis was undertaken to determine the maximum clock rate for theproposed system. The longest delay path is the multiplication data path, which involvesthe internal register file and the shift function ofthe' AS888. Table 4-9 contains the criticaldelay calculations for both the ALU and CCU. Since both portions ofthe system must besatisfied, a clock rate of 90 ns was selected for the following comparisons.Most microprocessors perform an instruction fetch in a pipeline mode; the nextinstruction is fetched while the current instruction is executing. The fetch code shownearlier requires a minimum of four cycles: three to issue the code and one to breakthe pipeline for processing the branch. This results in a total time of 360 ns, basedon a 90 ns cycle time. Fetch times for the representative microprocessors have beenestimated from data books and are shown in Table 4-10; wait states for slow memoryare not included. As can be seen from the table, the 'AS888 design example isestimated to run from 1.1 to 2.1 times faster than the 16-bit microprocessors.lEIl>"C'E.c:;.0)r+o·:::::J::cCD"Co"""Ir+en4.6.2Multiplication AnalysisThis analysis assumes that multiplication is unsigned integer and register to registerbased. No account is taken of time needed for instruction fetch or operand fetch orstore.The basic loop for the mUltiply takes 35 cycles: 2 for accumulator and multiplier setup, 32 for actual multiply loop and 1 to store the least-significant bits in an internalregister file. Given a cycle time of 90 ns, a 32 by 32 bit mUltiplication can beimplemented in 2.275 microseconds. A 16-bit multiply requires 16 iterations of theinner loop; both timings are included in Table 4-11 for comparison. Values for the16-bit multiplies of the representative microprocessors have been estimated from databooks.As shown in Table 4-11, the 16 by 16 multiply can be performed with the' AS888at a faster rate than the 16-bit microprocessors. Even comparing the 32 by 32 multiplyof the application design, one can see that the' AS888 based system has a bettermacroinstruction execution speed. Using the' AS888 and' AS890 in a system designwill allow high throughput and permit a flexible architecture.3-154

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Table 4-9. Critical Delay Path AnalysisCONTROL PATHDATA PATHPipeline Reg. Clock to Output 9 'AS888-1 Clock to C n 46MUX Select to Output 13 'AS182 Cn to Cn+ z 5'AS890-1 CC to Output 25 'AS888-1 Cn to SIO 25PROM Access Time 20 'AS888-1 SIO to Y 11Pipeline Reg. Setup Time -1 90 ns69 nsTable 4-10. Fetch Timing Comparison'AS888FETCH 32-81T Z8001 8086·1 80286 68000LData width 32 16 16 16 16No. of cycles 4 3 4 4 4Clock rate 11.11 MHz 4 MHz 10 MHz 10 MHz 8 MHzTotal time 360 ns 750 ns 400 ns 400 ns 600 nsTable 4-11. MUltiply Timing Comparison'AS888'AS888MULTIPLY 32·81T 16-81T Z8001 8086-1 80286 68000LSize 32 x 32 16 x 16 16 x 16 16 x 16 16 x 16 16 x 16No. of cycles 35 19 70 128 21 ,,;:::74Clock rate 11.11 MHz 10.98 MHz 4 MHz 10 MHz 10 MHz 8 MHzTotal time 3.15011s 1.729 I1S 17.511S 12.811S 2.1 115 - ";:::9.25I1s3-156

5" Floating-Point System DesignBit-slice processor architecture addresses the problem of optimizing systemperformance while allowing the user to balance hardware complexity against softwareflexibility. Bit-slice systems usually operate at or near the speed of the most primitiveof programmable processors, the PROM state sequencer. Of course, bit-slicearchitecture incorporates circuitry dedicated not only to sequencing, but also dataprocessing (ALU) operations. In keeping with the trend of these programmable devicesto track the speed of fast discrete hardware, the' AS888 8-bit sliceALU and' AS890microsequencer have been produced in Advanced Schottky bipolar technology. Inaddition to sheer speed, the components feature greater density (2 micron geometry)for greater functionality (more special purpose circuitry on board). The impact willbe faster, more powerful systems in applications which previously pushed the limitsof bit-slice processors.Consider an application in which bit-slice architecture has dominated for years: CPUdesign. The microprogrammed CPU itself spans a spectrum of uses ranging fromgeneral purpose minicomputers to compact airborne computers. A specific examplewhich illustrates various facets of design using the' AS888 and' AS890 is a CPU witha floating-point utility to compute sin(x).The design process can be subject to many influences, including personal preference,available development tools, peculiarities of the application, and constraints from theuser, customer or manufacturing environment. No hard and fast design rules couldbe applied universally, but most designers will start with a specific plan in mind.The goal of this example is to produce the hardware and microprogram which willimplement the sin (x) function in floating-point arithmetic. Before the microprogramcan be assembled, the hardware must be defined since the fields of themicroinstruction are dedicated to specific hardware once the microinstruction registeris hardwired to the devices it controls. Since the final architecture chosen dependson tradeoffs between implementing certain operations in hardware or software, criticalapplications will require that a cursory analysis of the software be made beforethe hardware is cast in concrete. Attempting to develop microcode for a tentativearchitecture will force the issue on which operations are better suited for hardware.Before the architecture or the microprogram requirements can be known, thealgorithms which describe the application processes must be defined. Once analgorithm is formulated it can be broken down into operations involving variable andconstant quantities. The variables can be assigned to registers and then the algorithmcan be translated into a microprogram. The following steps illustrate the plan for thisCPU design example incorporating a floating-point sin (x) utility:Step 1: Choose a floating-point number systemStep 2: Choose an algorithm for approximating sin (x)Step 3: Make' AS888 register assignmentsStep 4: Substitute registers for variables in the algorithmStep 5: Decompose steps of the algorithm into simple operationsStep 6: Translate into' AS888/890 operations; identify subroutinesStep 7: Translate subroutines into' AS888/890 operationsStep 8: Evaluate tradeoffs and block diagram the hardwareStep 9: Define microinstruction fields during detailed hardware designStep 10: Assemble the microprogramU)~'ōCoQ)a:s::::o"';:CO"~C.Co

5.1 Choose a Floating-Point Number SystemAn IEEE floating-point format will be chosen for this example for portability of dataarid software. It is important to note that the IEEE defines many standards in arithmeticprocessing, but for simplicity this example will encompass only number format.Furthermore, while several formats are IEEE compatible, only the basic single-precisionformat will be considered.The IEEE basic single-precision format is defined as a 32-bit representation in whichthe component fields are a 1-bit sign 5, an 8-bit biased exponent e and a 23-bit fractionf which are assembled in the foilowing order:15 I e31 0The quantity is evaluated as (- 1)S 2 e - 127 (1.f). Not-a-number, zero and infinityhave special representations. The one preceding the binary point is implied and is calledthe implicit one or implicit bit. It coincides with the fact that the digits are normalized(left justified).5.2 Choose an Algorithm for Sin (x)Many algorithms are discussed in the literature for approximating useful quantitieslike sin(x). Literature research is a good place to start to familiarize oneself with variousalgorithms and tradeoffs for a particlar application. Computer simulation is also usefulto compare algorithms for speed and accuracy. R.F. Ruckdeschel in BASIC ScientificSubroutines, Vol. 1 (BYTE, McGraw-Hili Publications Co. New York, N. Y., 1981, pp.159 -191 discusses tradeoffs and provides a simulation in BASIC for a sin (x)algorithm. An adaptation of this material has been chosen for this example:A) Reduce angle range to first quadrant. (0 :5 X :5 7r/2)6B) Compute sin (x) == I; Anx2n - 1. The coefficients are:n=OCoefficientDecimal1.000000-0.16666670.008333333- 0.00019841270.000002755760- 0.000000025070600.0000000001641060IEEE hex3F80 0000BE2A AAAD3C088888B9500D013638 EF99B2D75AD52F346FBC3-158

The algorithm can be implemented in the following steps:A) Reduce angle range to first quadrant. (0 ::; x ::; 7r/2)1) SIGN = SGN(x)2) ABSX = Ilxll3) XNEW = ABSX - 27r x INT(ABSX/27r)4) If XNEW > 7r then SIGN = - SIGN and XNEW5) If XNEW > 7r/2 then XNEW = 7r - XNEWXNEW -7rwhereSGN(x) = {+ 1 .if x 2:: 0-1 If x < 0INT(x) = integer function6B) Compute sin(x) == E An x2n - 1 .n=O1) Let XSOR = XNEW2; INITIALIZE SINX = 02) Do i = 6 to 1 step - 1SI!'JX = XSOR x SINX + A(i)Enddo3) SINX = SIGN x XNEW x SINXStep B-2 computes the summation in a geometric series for economy. The majordifference between steps A and B is that A requires more diverse ALU operationswhile B uses only multiplication and addition recursively.5.3 Make' AS888 Register AssignmentsJust as in assembly language programming, registers must be allocated for variables.Using Rn to denote the' AS888 register whose address is n, where 0 ::; n ::; F (hex),the following register assignments can be made:ROR1R2R3R4R5XSIGNABSXXNEWXSORSINXThe following constants can also be defined:Constant Decimal IEEE hexPI = 7r 3.141593 40590FDBPIOVR2 = 7r/2 1.570797 3FC90FDB2PI =27r 6.283185 40C90FDB10VR2PI = 1/27r 0.159155 3E22 F981....'C/)oQ.Q)CCc:o"';:CO"~C.Q.~3-159

5.4 Substitute Registers for Variables in the AlgorithmNow the algorithm can be rewritten with registers replacing variables:A) Reduce angle range to first quadrant (0 :5 X :5 7r/2).1) R1 SGN(RO)2) R2 = IIROII3) R3 = R2 - 27r x INT(R2/27r)4) If R3> 7r then R1 = -R1; R3 R3 - 7r5) If R3 > 7r/2 then R3 = 7r - R36B) Compute sin (x) == 1: An x2n - 1 .n=O1) Let R4 = R02; INITIALIZE R5 = 02) Do i = 6 to 1 step - 1R5 = R4 x R5 + A(i)Enddo3) R5 = R1 X RO X R5Since various references to constants are made, it is probably best to load constantsas needed rather than attempt to allocate registers for them. Constants can be loadedfrom a constant field in the microinstruction or from ROM. The tradeoff is 32 bitsby 16K of micromemory versus 32 bits by the number of constants (typically lessthan 16K)~ For this example, it will be assumed that a constant field in themicroinstruction is acceptable.5.5 Decompose Steps in the Algorithm into Simple OperationsThe sin (x) function can be microprogrammed as a subroutine; let FSIN be its entryaddress. RO would be loaded with x before FSIN were called. Upon return, R5 wouldcontain sin(x). Now decompose the steps in the algorithm into simple arithmetic andlogical operations. Other operations can be left as functions to be defined later.FSIN: SUBROUTINEA) Reduce angle range to first quadrant. (0 :5 X :5 7r/2)R1SGN(RO)1) Let R1 = Sign of RO»'C'E..C:;"Q)r+o·::::l::x:JCD'C...0r+enR2ABS(RO)R3 R2 * 10VR2PIR3 INT(R3)R3 R3 * 2PIR3 R2 - R3Y = R3 - PIJump if Negative to Step A-5R1 -R1R3 = R3 - PIY = PIOVR2 - R3Jump if Negative to Step B-1R3 = PI - R3.'2) R2 IIROII3) R3 R2 - 27r * INT(R2/27r)4) If R3 > 7r,then R 1 = - R 1 ;R3 = R3 - 7r5) If R3 > 7r/2then R3 = 7r -R33-160

B) Compute sin (x)R4R5RO * ROo6I: An x2n-1n=O1) Let R4 R02. Let R5oR5R5R5R5R5R5R5R5R5R5R5R5R5R5R5R5R4 * R5R5 + A6R4 * R5R5 + A5R4 * R5R5 + A4R4 * R5R5 + A3R4 * R5R5 + A2R4 * R5R5 + A1R4 * R5R5 + AORO * R5R5 * R1 : RETURN2) Do i = 6 to 1 step - 1R5 = R4 x R5 + A(i)Enddo(To implement a loop,use an 'AS890 counterto index a memory containingthe constants.)3) R5 R1 x RO x R5END SUBROUTINE5.6 Translate into' AS888/890 Instructions; Identify SubroutinesThe simplified steps of the algorithm can be represented fairly easily as 'AS888/890instructions. Necessary functions (and suggested names) can be identified byinspection as:1) FMUL - Floating-point multiplication2) FADD - Floating-point addition3) FINT Floating-point integer conversion4) FINV - Floating-point additive inverse (to subtract using FADD)5) FABS - Floating-point absolute value6) FSGN - Floating-point sign test7) FCHS - Floating-point change of sign (to multiply by SIGN)"Function" in this context refers to a special operation regardless of how it is coded.In fact, FMUL and FADD are fairly complex and require detailed explanation. FINV,FABS, FSGN and FCHS are single instruction operations that mask or mask and test.FINT requires several inline instructions or a subroutine and will be left to the interestedreader as an exercise. Now the steps of the algorithm can be translated into'AS888/890 operations which include references to these functions.tJ)....oc.Cl)a:c:o0';:COo~Q.c.«3-161

FSIN: SUBROUTINE; A) Reduce angle range to first quadrant. (0 :5 X :5 7r/2)R1 FSGN(RO) ; Get sign bit (MSB)R2 FABS(RO) ; Take absolute value (clear MSB)R3 FMUL(R2,1 OVR2PI) ; Multiply register and constantR3 FINT(R3) ; Floating-point integer conversionR3 FMUL(R3,2PI) ; Multiply register and constantR3 FADD(R2,INV(R3)) ; Subtract registers by adding inverseY = FADD(R3,NEGPI) : TEST NEG; Subtract by adding negative constantJT SIN1; Jump if true (jump if negative)R1 = FINV(R1); Complement sign of R1R3 = FADD(R3,NEGPI); Subtract by adding negative constantSIN 1: Y = PIOVR2 - R3 : TEST NEG ; Subtract to compare (don't store)JT SIN2; Jump if true (jump if negative)R3 = FADD(PI,FINV(R3)); Subtract by adding negative register6; B) Compute sin (x) :::: t An x2n - 1n=OSIN2: R4R5R5R5R5R5R5R5R5R5R5R5R5R5R5R5END SUBROUTINEFMUL(RO,RO)A6FMUL(R4,R5)FADD(R5.A5)FMUL(R4,R5)FADD(R5.A4)FMUL(R4,R5)FADD(R5.A3)FMUL(R4,R5)FADD(R5,A2)FMUL(R4,R5)FADD(R5.A 1)FMUL(R4,R5)FADD(R5,AO)FMUL(RO,R5)FCHS(R5,R1) : RETURN; Square by mUltiplying; Initialize series; Multiply registers; Add coefficient; Multiply registers; Add coefficient; Multiply registers; Add coefficient; Multiply registers; Add coefficient; Multiply registers; Add coefficient; Multiply registers; Add coefficient; Multiply registers; Change MSB of R5 to MSB of R1This contrived language has a syntax which may be suitable for a source program.For the sake of illustration, it can be assumed that the microassembler recognizesthis particular syntax. The series was computed inline instead of using a loop sinceit is relatively short. If a loop were used, a means of indexing the constants wouldbe required.5.7 Expand Subroutines into ' AS888/890 OperationsFMUL and FADD algorithms can now be expanded. Since they are called extensivelyfrom FSIN, they are more critical to the efficiency of the final design. Whereverpossible, it is desirable to reduce the execution time of both in order to maintainefficiency.3-162

5.7.1 Floating-Point MultiplicationLet M 1 be the multiplier and M2 be the multiplicand whose product is P. Let the sign,exponent and fraction fields of their IEEE representation be:Ml : IS11El1F11M2: IS21E21F21P: IS31E31F31P is found by multiplying mantissas (fraction plus implicit one) and adding exponents.Since Ml and M2 are normalized, the range of 1.Fl x 1.F2 is1.00 ... 0 $ 1.Fl x 1.F2 $ 11.1 ... 10The implicit bit may" overflow" into bit position 24. This type of overflow must bedetected so that the result can be normalized. Normalization requires right shiftingthe result of 1.Fl x 1 .F2 and incrementing E3. The implicit bit is then cleared whenS3, E3 and M3 are packed to form P. The floating-point multiplication algorithm maythen be defined as follows:1) Unpack M1 into signed fraction (SF1) and exponent (El)2) Set the implicit bit in SFl3) Unpack M2 into signed fraction (SF2) and exponent (E2)4) Set the implicit bit in SF25) Perform SF3 == SF1 x SF2 using signed integer multiplication6) Perform E3 == El + E27) Test SF3 for overflow into bit 248) If true, then increment E3 and right shift SF39) Clear the implicit bit in SF310) Pack E3.and SF3 to get PAs before, the steps of this algorithm can be broken down into simpler operations:1 ) Unpack M 1 into signed fraction (SF1) and exponent (El)El == FEXP(Ml)SFl == FRAC(Ml)2) Set the implicit bit in SFlSFl == SFl OR 81T233) Unpack M2 into signed fraction (SF2) and exponent (E2)E2 == FEXP (M2)SF2 == FRAC (M2)4) Set the implicit bit in SF2SF2 == SF2 OR 81T235) Perform SF3 == SFl x SF2 using signed integer multiplicationSF3 == IMUL (SF1, SF2)6) Perform E3 == E 1 + E2E3 == E1 + E27) Test SF3 for overflow into bit 24TEST (SF3 AND 81T24)JUMP IF FALSE to step 98) If true, then increment E3 and right shift SF3INC E3SF3 == RSHFT (SF3)•...,tJ)0C.Q)a:t:0.';:;CO.2C.C.«3-163

9) Clear the implicit bit in SF3.SF3 = SF3 AND NOT _ BIT2310) Pack E3 and SF3 to get PP = SF3 OR E3FEXP, FRAC, testing bit 24 and setting/clearing bit 23 are all mask operations thattranslate into single' AS888 instructions. The integer multiplication (IMULl is simplythe multiplication algorithm supported by the' AS888 instruction set. No significanthardware features are required to do floating-point multiplication, nor are anysubroutines required to support it.Register assignments can now be made as before. Since FSIN uses registers in thelower half of the register file, it might be preferable to restrict FMUL to the upperregisters. For example:RF = PRE = M1, F1, SF1RD = M2, F2, SF2RC = E1RB = E2RE and RD can share variables that need not be preserved. Using this assignment,FMUL computes RF = FMUL(RE,RD). RE and RD must be loaded prior tocalling FMULand RF must be stored upon return. By substituting registers for variables andreorganizing operations in the FMUL algorithm to better fit' AS888/890 operationsthe following source program may be created:FMUL: SUBROUTINERC = FEXP(RE)RE = FRAC(RE)RE = RE OR BIT23MQ = SMTC(RE)RB = FEXP(RD)RD FMAG(RD)RD = RD OR BIT23RD = SMTC(RD); Unpack M 1 into exponent; and fraction; Set implicit bit; Prepare to mUltiply; Unpack M2 into exponent; and fraction; Set implicit bit; Prepare to multiplyRE 0 : RCA = # 22d ; Initialize to multiplyRE = SMUll RD : LOOP RCA ; Integer multiplication iterationRE = SMUL T RD; Final step in signed multiplyY = TBO(RE,BIT1 ):BYTE = # 01 OOb:TEST Z ; Test "overflow"JF FMUL 1; Jump if false (exponent ok)INEX(RC)RE = SRA(RE)FMUL 1 :RC = RC + RB : TEST CARRYJT ERRORRERERFSMTC(RE)RE AND #807F_FFFFhRE OR RC : RETURN; Increment exponent: add 00800000; Shift fraction to normalize; Add exponents and test carry; Jump if carry true to handler; Get sign magnitude fraction; Clear implicit bit; Pack fraction and exponent3-164

5.7.2 Floating-Point AdditionThe floating~point addition algorithm (FADD) is slightly more complex than FMUL, sincethe two addends will usually not have the same exponent. Therefore the smaller(absolute value) addend must first be chosen by comparing exponents. Then it mustbe denormalized to align its digits with the digits of the larger addend. In other words,the two addends must have the same exponent before their fractions can be added.This process can be described by the following algorithm:1) Unpack A 1 to get SF1 and E 12) Set implicit bit in SF13) Unpack A2 to get SF2 and E24) Set implicit bit in SF25) If E2 > E1 then go to step 9( II A 1 II :5 II A211 )6) Let DIFF = E1 - E27) Do i = 1 to DIFFSF2 = RSHFT(SF2) (Arithmetic right shift)Enddo8) Let E3 = E1 , go to step 12(1IA211> IIA111)9) Let DIFF = E2 - E110) Do i = 1 to DIFFSF1 = RSHFT(SF1) (Arithmetic right shift)Enddo11) Let E3 = E212) SF3 = SF1 + SF213) Test "overflow" into bit 2414) Jump if false to step 1715) Increment exponent E316) Normalize signed fraction with right arithmetic shift17) Clear implicit bit18) Pack: SUM = SF3 or E319) ReturnRegister assignments for variables must now be made. Since FSIN uses registers inthe lower half of the' AS888 register file, it is necessary to use the upper registers:RF = SUMRE=A1,F1,SF1RD = A2, F2, SF2RC = E1RB = E2By slightly reorganizing the sequence to better fit 'AS888/890 operations, thefollowing microprogram to perform FADD can be created:FADD: SUBROUTINE; 1) Unpack A 1 to get SF1 and E1RC = FEXP(RE)RE = FRAC(RE)2) Set implicit bit in SF1MQ = RE OR BIT23RE = SMTC(RE); Get exponent (E1); Get signed fraction (SF 1 ); Set implicit bit; Convert to two's complement•...CJ)...oQ.(1)a:£::o"';:('Q"~C.Q.

3) Unpack A2 to get SF2 and A2RB = FEXP(RD)RD = FRAC(RD)4) Set implicit bit in SF2RD = RD OR BIT23RD = SMTC(RD); Get exponent (E2); Get signed fraction (SF2); Set implicit bit; Convert to two's complement5) If E2 > E1 then go to step 9RF = RC - RB : TEST NEGATIVE ; Compare A2 from A 1JT FADD 1 : RCA = # 8 ; Jump if E2 > E1; set up loop count6) Let DIFF = E1 - E2.Y/RF = SLC(RF) : LOOP RCARCA = Y/RF7) Do i = 1 to DIFFSF2 = RSHFT(SF2)EnddoRD = SRA(RD) : LOOP RCA8) Let E3 = E1, go to step 12RB = RC : JUMP FADD29) Let DIFF = E2 - E1FADD1: RF = NOT(RF)Y/RF = SLC(RF) : LOOP RCARCA = Y/RF;10) Do i = 1 TO DIFFSF1 = RSHFT(SF1)EnddoRE = SRA(RE) : LOOP RCA; Rotate 8 times to get difference; Load difference in loop counter; Orient digits of smaller addend; Swap registers and branch; Complement result of E1 - E2; Shift 8 times to get DIFF; Load DIFF in loop counter; Align SF1 with SF2; 11) Let E3 = E2 (no instruction required - RB already has E2 in it);12) SF3 = SF1 + SF2FADD2: RF = RD + RERF = SMTC(RF);13) Test "overflow" into bit 24RF = TBO (RF, BIT24); 14) Jump if false to step 17JF FADD3; 15) Else increment exponentINC RB : TEST NEG; 16) Normalize signed fractionRF = SRA(RF) : JT ERROR; 17) Clear implicit bitFADD3: RF = SETO (RF, BIT23); 18) Pack: SUM = SF3 OR E3RF = RF OR RB : RETURN; Add; Convert to sign-magnitude; Check for normalization; If so, finish and exit; Test for exponent overflow; Jump to error handler if overflow; Reset bit 23 of RF; Or signed fraction and exponent3-166

There is an important consequence of FADD which impacts the hardware. Since thenumber of shifts required to denormalize the small addend is data dependent(computed in the ALU) it is necessary to provide a path between the ALU Y bus andthe' AS890 DRA bus. All the other operations are simple' AS888/890 instructions,including the FRAC and FEXP mask operations discussed during the development ofFMUL. ERROR is a floating-point overflow error handler.5.8 Evaluate Tradeoffs and Block Diagram the HardwareA rough estimate of the FSIN worst case execution time can be arrived at by makingthe following observations about FSIN, FMUL and FADD:FMULinteger recursion =:: 22 cyclesother instructions =:: 18 cyclestotal =:: 40 cyclesFADDdenormalization =:: 23 cyclesother instructions =:: 25 cyclestotal =:: 50 cyclesFSINnumber of calls to FMUL = 12number of calls to FADD = 11number of other cycles =:: 10Approximate worst case total = 10 + (12 x 40) + (11 x 50) = 1040 cycles. At50 nanoseconds per cycle, this requires approximately 52 microseconds. There arefew improvements that could be made in hardware to speed this time, except perhapsthe addition of a flash multiplier which would reduce the integer computation by about20 cycles (an overall reduction of about two percent). A barrel shifter could have thesame benefit during floating-point addition for a total reduction of about 4 percent.For the sake of simplicity, it will be assumed that 52 microseconqs is acceptable forthe sin (x) computation.Another issue which must be considered .is the problem of loading the' AS888 and'AS890 with constants. A slight materials cost reduction might be realized by storingconstants in table PROMs rather than in control store memory. An interesting useof the DRA and DRB ports on the' AS890 would be to use the output of RCA or RCBto index data in the constant PROM. This would allow long series to be implementedin loop form rather than'the inline method used in FSIN. Once again, the constantPROM will not be implemented for the sake of simplicity.Now the architecture can be designed to meet the requirements identified throughoutthis analysis:1) A path between the' AS888 Y bus and the' AS890 DRA bus.2) A path between the microinstruction register and the' AS890 DRA bus for loadingloop counts and branch addresses.3) A path between the IT]icroinstruction register and the' AS888 Y bus for loadingconstants.4) Independent control of SIOO in each' AS888 slice to allow bit/byte instructions.5) A status register to store' AS888 status for testing.6) A status mux to test the' AS888 status, bit 23 of the 'AS888 Y bus, bit 24of the 'AS888 Y bus and hardwired 0 and 1.A system having these features is illustrated in Figure 5.1.fI)+-'a..oC.Q)a:c:o.~ctS.~C.c.

Cfen(Xls:uodaM uOrJ.eO!lddvSYSTEM INTERFACE1_ .IDRA7.DRAOAlS1511/8'AlS 374AS890I I tDA DB Y51005108'AS888 (4)ZNOVRC n +8- IHD 1DoSELYCCClK I , IClKiii~ 0W

5.9 Define Microinstruction Fields During Detailed Hardware DesignThe detailed hardware design will produce a wiring diagram that fixes the positionwithin the microinstruction of each of the various control signals that are connectedfrom the microinstruction register to the' AS888, 'AS890, status mux and any otherspecial hardware. Once this design ir complete it is possible for the assembler to sortthe control bits of each instruction so that they will be properly oriented when themicroprogram is installed in the target system.5.10 Assemble the MicroprogramTI is currently developing an 'AS888/890 microassembler. Several microassemblersare commercially available, and many users prefer to write their own. Themicroprogram shown in Table 5-1 was hand-assembled, but has a syntax that issuitable for interpretation by a user-written assembler.rJ)...,~oa.Q)a:c:o'';:CO,~a.a.«3-169

Cf--..Jos:uodaJ:l UOrl.eO!lddvTable 5.1. Floating Point Sin (x) Microprogram0000 SIN:000100020003000400050006000700080009OOOAOOOBOOOCOOODOOOEOOOF00100011* Rl = FSGN(RO)Rl = RO AND #8000 OOOOh* R2 = FABS(RO)R2 = ROR2 = RO SETO #80h : BYTE=#1000b* R3 = FMUL(R2,10VR2PI)RE = R2RD = #3EA2 F984hJSR FMULR3 = RF* R3 = FINT(R3)RF = R3JSR FINT [EXERCISE FOR READER)R3 = RF* R3 = FMUL(R3,2PI)RE = R3RD = #40C9 OFDBhJSR FMULR3 = RF* R3 = FADD(R2,INV(R3))RE = R2RD = R5 XOR #8000 OOOOhJSR FADDR3 = RF0X::J0 o::!:al~~8 ~~ 0 32-bit~No ~~ < alit.) ul1~~&lOI~ffil~I~~~8 ~ Constant a: ::!: III DRBO a: a: ~ III1~1~~i~ ~ ~ DRB13-00X10211100FA 80000000 1111 027XXXXll1700X20Xlll00F6 XXXXXXXX 1111 027XXXXll170028001110018 XXXXXXXX 1 1 1 0 027XXXXll1702XEOXlll00F6 XXXXXXXX 1111 027XXXXll17OXXDXXllllXFF 3EA2F984 1111 027XXXXll17lXXXXXlllXXFF XXXXXXXX 1111 01400601117OFX30Xlll00F6 XXXXXXXX 1111 027XXXXll1703XFOXlll00F6 XXXXXXXX 1111 027XXXXll17lXXXXXll1XXFF XXXXXXXX 1111 o 1 4 .... 1 1 1 7OFX30Xll100F6 XXXXXXXX 1111 027XXXXll17o 3 X E,O X 1 1 1 0 0 F 6 XXXXXXXX 1111 027XXXXll17OXXDXX1110XFF 40C90FDB 1111 02 7 X X X X 1 1 1 7lXXXXX111XXFF XXXXXXXX 1111 01400601117OFX30Xlll00F6 XXXXXXXX 1111 027XXXXl11702XEOX11100F6 XXXXXXXX 1111 027XXXXll1705XD0211100F9 80000000 1111 027XXXX1117lXXXXX111XXFF XXXXXXXX 1111 01400741117OFX30Xll100F6 XXXXXXXX 1111 027XXXXll17

Table 5.1. Floating Point Sin (x) Microprogram (continued)00120013001400150016001700180019001A001B* SIN1:001C SIN1:0010001E001F00200021002200230024* SIN2:0025 SIN2:002600270028* Y = FADD(R2,NEGPI)RE = R2RD = #C059 OFDBhJSR FADDY = RF : TEST NEGJT SINl* Rl = FINV(Rl)Rl = Rl XOR #8000 OOOOh* R3 = FADD(R3,NEGPI)RE = R3RD = #C059 OFDBhJSR FADDR3 = RF. Y = FADD (PIOVR2,INV(R3)) : TEST NEGRE = #3FC9 OFDBhRD = R3 XOR #8000 OOOOhJSR FADDY = RF : TEST NEGJT SIN2* R3 = FADD(PI,FINV(R3))RE = #4059 OFDBhRD = R3 XOR #8000 OOOOhJSR FADDR3 = RFR4 = FMUL(RO,RO)RE = RORD = ROJSR FMULR4 = RF0)(:J0 o~~a:8 ~~al>~ 0 32·bit1E~oN:J II} DRB13· ° 0lu ....I1~~~~I~al~IWWW c ;::: ~alU W OO(l)U_ Constant 1E ~ III DRBO i2 ~ ~ ~I~I~I~I~02XEOXlll00F6 XXXXXXXX 1111 027XXXXl117OXXDXXlll0XFF C0590FDB 1111 027XXXX1117lXXXXXll1XXFF XXXXXXXX 1111 014007411171FXXOX11000F6 XXXXXXXX 1111 027XXXXl112lXXXXXlllXXFF XXXXXXXX 1111 0170000111701Xl0211100F9 80000000 1111 027XXXX111703XEOX11100F6 XXXXXXXX 1111 027XXXX111703XDXX1111XFF C0590FDB 1111 027XXXX11171XXXXXlllXXFF XXXXXXXX 1111 01400741117OFX30Xll100F6 XXXXXXXX 1111 027XXXX1117OXXEXX11110F6 35C90FDB 1111 027XXXXl11703XD0211100F9 80000000 1111 027XXXX1117lXXXXX111XXFF XXXXXXXX 1111 014007411171 F X X O·X 1 1 0 0 0 F 6, XXXXXXXX 1111 027XXXX1 1121XXXXX1 11XXFF XXXXXXXX 1111 01700001117OXXEXXll110F6 405.90FDB 1111 027XXXX111703XD0211100F9 80000000 1111 027XXXX1 1 1 7lXXXXX111XXFF XXXXXXXX 1111 01400741117OFX30X11100F6 XXXXXXXX 1111 027XXXX1 1 1 700XEOX1 1 100F6 XXXXXXXX 1111 027XXXX1 1 1 7OOXDOXl 1 100F6 XXXXXXXX 1111 027XXXX1 1171XXXXX111XXFF XXXXXXXX 1111 014006011170~)(40X1 1 100F6 XXXXXXXX 1111 027XXXX1 1 1 7nwCf-....JApplication Reports

Cf-..,JNs~JodaMuo!~eo!ldd"Table 5.1. Floating Point Sin(x) Microprogram (continued)* R5 = A60029 R5 = #2F34 6FBCh002A002B002C002D* R5 = FMUL(R4,R5)RE = R4RD = R5JSR FMULR5 = RF* R5 = FADD(R5.A5)002ERE = R5002FRD = #B2D7 5AD5h0030 JSR FADD0031 R5 = RF* R5 = FMUL(R4,R5)0032 RE = R40033 RD = R50034 JSR FMUL0035 R5 = RF* R5 = FADD(R5,A4)0036 RE = R50037 RD = #3638 EF99h0038 JSR FADD0039 R5 = RF003A003B003C003D* R5 = FMUL(R4,R5)RE = R4RD = R5JSR FMULR5 = RF0X::J0 o:E~No . ww~g8 ~ctal>~ 0l~ M M MI;5 al~IW w we -;I~I~~~32-bit ~ ~ ~ DRB13- 1~~lu u:lctalU w OOenu!:: Constant ex: :E en DRBO ex: ex: ~ enOXX50X11110F6 2F346FBC 1 1 1 1 027XXXX111704XEOX11100F6 XXXXXXXX 1111 027XXXX111705XDOX11100F6 XXXXXXXX 1111 027XXXX11171XXXXX111XXFF XXX~XXXX 1111 01400601117OFX50X11100F6 XXXXXXXX 1111 027XXXX111705XEOX11100F6 XXXXXXXX 1111 027XXXX1117OXXDXX1111XFF B2D75AD5 1111 027XXXX11171XXXXX111XXFF XXXXXXXX 1111 01400741117OFX50X11100F6 XXXXXXXX 1111 027XXXX111704XEOX11100F6 XXXXXXXX 1111 027XXXX111705XDOX11100F6 XXXXXXXX 1111 027XXXX11171XXXXX111XXFF XXXXXXXX 1111 01400601117OFX50X11100F6 XXXXXXXX 1111 027XXXX111705XEOX11100F6 XXXXXXXX 1111 027XXXX1117OXXDXX1111XFF 3638EF99 1111 027XXXX11171 X X X X X 1 1 1 X X F- F XXXXXXXX 1111 01400741117OFX50X11100F6 XXXXXXXX 1111 027XXXXll1704XEOX11100F6 XXXXXXXX 1111 027XXXX111705XDOX11100F6 XXXXXXXX 1111 027XXXX11171XXXXX111XXFF XXXXXXXX 1111 01400601117OFX50X11100F6 XXXXXXXX 1111 027XXXX1117

Table 5.1. Floating Point Sin(x) Microprogram (continued)Cf"-JW* R5 = FADD(R5,A3)003ERE = R5003FRD = #B9500D01h0040 JSR FADD0041 R5 = RF* R5 = FMUL(R4,R5)0042 RE = R40043 RD = R50044 JSR FMUL0045 R5 = RF* R5 = FADD(R5,A2)0046 RE = R50047 RD = #3C08 8888h0048 JSR FADD0049 R5 = RF* R5 = FMUL(R4,R5)004ARE = R4004BRD = R5004CJSR FMUL004DR5 = RF* R5 = FADD(R5,A 1)004ERE = R5004FRD = #BE2A AAADh0050 JSR FADD0051 R5 = RF* R5 = FMUL(R4,R5)0052 RE = R40053 RD = R50054 JSR FMUL0055 R5 = RFApplication Reports I0X:J0 o:!Eal~:il8 ~ctal>~ 0 32-bit~No ~ ~ ~ DRB13-~r ~ glu ulctalUWW O(l)U!::: a: :!E (I) DRBO a: a: ~ (I)I~MMMlctal~~WW c ~ Constant~~I~I~05XEOX11100F6 XXXXXXXX 1111 027XXXX1117OXXDXX1111XFF B9500D01 1111 027XXXX11171XXXXX111XXFF XXXXXXXX 1111 01400741117OFX50X11100F6 XXXXXXXX 1111 027XXXX111704XEOX11100F6 XXXXXXXX 1111 027XXXX111705XDOX1·1100F6 XXXXXXXX 1111 027XXXX11171XXXXX111XXFF XXXXXXXX 1111 01400601117OFX50X11100F6 XXXXXXXX 1111 027XXXX111705XEOX11100F6 XXXXXXXX 1111 027XXXX1117OXXDXX1111XFF 3C088888 1111 027XXXX11171XXXXX111XXFF XXXXXXXX 1111 01400741117OFX50X11100F6 XXXXXXXX 1111 027XXXX111704XEOX11100F6 XXXXXXXX 1111 027XXXX111705XDOX11100F6 XXXXXXXX 1111 027XXXX11171XXXXX111XXFF XXXXXXXX 1111 01400601117OFX50X11100F6 XXXXXXXX 1111 027XXXX111705XEOX11100F6 XXXXXXXX 1111 027XXXX1117OXXDXX11111FF BE2AAAAD 1111 027XXXX11171XXXXX111XXFF XXXXXXXX 1111 01400741117OFX50X11100F6 XXXXXXXX 1111 027XXXX111704XEOX11100F6 XXXXXXXX 1111 027XXXX111705XDOXlll00F6 XXXXXXXX 1111 027XXXXl1171XXXXX111XXFF XXXXXXXX 1111 01400601117OF X 50 X 11100 F 6 XXXXXXXX 1111027 XXXX 1117

Cf-...I.J::.sJJodaH UO!Je:llldd'V.Table 5.1. Floating Point Sin (x) Microprogram (continued)0056005700580059005A005B005C0050005E005F0060 FMUL:00610062006300640065* R5 = FADD(R5,A0)RE = R5RD = #3F80 OOOOhJSR FADDR5 = RF* R5 = FMUL(RO,R5)RE = RORD = R5JSR FMULR5 = RF* R5 = FCHS(R5,R1) : RETURNRl = Rl OR #7FFF FFFFhR5 = R5 XOR Rl : RETURN* RC = FEXP(RE)RC = RE AND #7F800000h* RE = FRAC(RE)RE = RE AND #807F FFFFh* RE = RE OR bit23RE = RE OR #0080 OOOOh* MO = SMTC(RE)RE = SMTC(RE)LOADMO : PASS* RB = FEXP(RD)RB = RD AND #7F80 OOOOh0>0 o~co~~8 ~~ 032-bit ~ ~ 0~::> ~ DRB13-IW~-.:(cooww~ colo u:l(1)0 _ Constant a: ~ II) DRBO a: a: ~ II)I~MMMI

Table 5.1. Floating Point Sin (x) Microprogram (continued)0066006700680069006A006B006C006D006E006F0070 FMUL1:0071* RD = FRAC(RD)RD = RD AND #807F FFFFhRD = RD OR bit23RD = SMTC(RD)RE = 0 : RCB = #22DRE = SMUll RD : LOOP RCBRE = SMULT RDTBO(RE,bitl) : BYTE = #01 OOb : TEST ZJT FMULl* INEX RCRC = RC ADD #0080 OOOOhRE = SRA(RE)RC = RC ADD" RB : TEST CARRYJT ERROR0072 RE = SMTC(RE)0073 RE = RE AND #807F FFFFh* FADD: RC = FEXP(RE)0074 FADD: RC = RC AND #7F80 0000* RE = FRAC(RE)0075 RE = RE AND #807F FFFFh0076 MQ = RE OR bit230077 RE = SMTC(RE)* RB = FEXP{RD)0078 RB = RD AND #7F80 00000X::J0 o::!:III000 wc:t1ll0 ~Ic:t~>~ ~~o nw0 32-bit N::J "I DRB13- 00 -1I~ M M Mlc:t III W W W W C -;c:tIllOWWO O(l)O!::: Constant ~ ::!: ~ DRBO ~ ~ 10 ~ ~I~I~I~~ODXD0211100FA 807FFFFF 1111 027XXXXll17ODXD0211100FB 00800000 1111 027XXXX1117OXDDX01111D58 XXXXXXXX 1111 027XXXXll17OEEE0011110F9 00000016 1111 617XXXXll14ODEEOOll11060 XXXXXXXX 1111 567006All14ODEE001110070 XXXXXXXX 1111 067XXXXll1700FOOOll11038 XXXXXXXX 1 0 1 1 027XXXXll141XXXXXX111XFF XXXXXXXX 1111 017XXXXll17OCXC0211100Fl 00800000 1111 027XXXXll17OEXEOX1110006 XXXXXXXX 1111 027XXXXl117OCBC0011100F1 XXXXXXXX 1111 027XXXX1110lXXXXX111XXFF XXXXXXXX 1111 017XXXX1117OXEEX01111058 XXXXXXXX 1111 027XXXX1117OEXE0211100FA 807FFFFF 1111 027XXXX1117OCXC0211100FA 7F800000 1111 027XXXX1117OEXE0211100FA 807FFFFF 1111 027XXXX11171EXX0111100EB 00800000 1111 027XXXX1117OEXE0211100FA 807FFFFF 1111 027XXXX1117ODXB0211100FA 7F800000 1111 027XXXX1117'f'-lU1Application Reports •

'f-'-...J0)suodaH uo!~e;)!ldd'lf•Table 5.1. Floating Point Sin (x) Microprogram (continued)0079007A007B007C0070007E007F008000810082 FADD1:0083008400850086 FADD2:008700880089008A008B008C FADD3:0080* RD = FRAC(RD)·RE = RE AND #807F FFFFhRD = RD OR bit23RD = SMTC(RD)RF = RC - RB : CO=O: TEST NEGJT FADDl : RCB = #8Y/RF = SLC(RF) : LOOP RCBY = RF: RCA = YRD = SRA(RD) : LOOP RCARB = RC : JUMP FADD2RF = NOT RFY/RF = SLC(RF) : LOOP RCBY = RF: RCA = YRE = SRA(RE) : LOOP RCARF = RD + RERF = SMTC(RF)RF = TBO (RI; bit24) : TEST ZJF FADD3INC RB : TEST NEGRF = SRA(RF) : JT ERRORRF = SETO (RF, bit23)RF = RF OR RB : RETURN0X::::I0 o::!E11:1~g8 ~~ 0 32-bit~ ~ 01~p,p,p,I

General InformationNumerical IndexGlossaryExplanation of Function TablesParameter Measurement InformationFunctional IndexLSI DevicesApplication. ReportsAdvanced, Schottky FamilyError Detection and CorrectionMemory MappingBit-Slice Processor 8-Bit FamilyExcerpt - SN74AS888, SN74AS890Bit-Slice Processor User's GuideMechanical Data4-1

III4-2

MECHANICAL DATAORDERING INSTRUCTIONSElectrical characteristics presented in this data book. unless otherwise noted. apply for circuit type(s) listedin the page heading regardless of package. The availability of a circuit function in a particular package is denotedby an alphabetical reference above the pin-connection diagram(s). These alphabetical references refer tomechanical outline drawings shown in this section.Factory orders for circuits described in this catalog should include a four-part type number as explained in thefollowing example.EXAMPLE~~----------------------~~MUST CONTAIN TWO TO FOUR LETTERSSN74ALS232 N 4SNSNJJANBStandard PrefixJEDEC PUBLICATION 101, Class BMIL-M-3B510 Qualified2. Unique Circuit Description )-__________________ ---JMUST CONTAIN SIX TO TEN CHARACTERS(From Individual Data Sheet)Examples:74522554LS61074ALS23274ALS632A74ALS29864MUST CONTAIN ONE OR TWO LETTERSD, DW ("Small Outline" Packages)J, JD, JG, JT, N, NT, NW, p, W (Dual-in-Line Packages)FH or FN (Chip Carriers)(From pin-connection diagram on individual data sheet)4. Instructions (Dash No.) }------------'3 PEP processing, level 3 (N or NT packages only)tThese circuits in dual-in-line and "small outline" packages are shipped in one of the carriers shown below. Unless a specific methodof shipment is specified by the customer (with possible additional costs), circuits will be shipped in the most practical carrier. Pleasecontact your TI sales representative for the method that will best suit your particular needs."Small Outline" (D, DW)Dual-in-Line (J, JD, JG, JT, N, NT, NW, p, W)- A-Channel Plastic Tubing- Tape and Reel- Barnes Carrier (W only)....., n:sn:sCCOucn:s.s::::uQ)2IITEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • OALLAS, TEXAS 752654-3

MECHANICAL DATAD plastic "small outline" packagesEach of these "small outline" packages consists of a circuit mounted on a lead frame and encapsulatedwithin a plastic compound. The compound will withstand soldering temperature with no deformation, andcircuit performance characteristics will remain stable when operated in high-humidity conditions. Leadsrequire no additional cleaning or processing when used in soldered assembly.14-PIN D PACKAGEf6,20 (0.244)8,74 (0.344).8,55 (0.337)3,81 (0.150)~1~----------~411,75 (0.069)1,27 (0.050)(See Note AI050(0020) ~5'21 (0.205Il' . X 45° 460 (0.1811 0,229 (0.009010,25 (0.0101 ' 0,190 (0.00751'~L:~~'~Jr?o0,51 (0.0201NOTES: A. Body dimensions do not include mold flash or protrusion.S B. \ Mold flash or protrusion shall not exceed 0.15 (0.006).C. Leads are within 0,25 (0.010) radius of true position at maximum material dimension.CD(") D. Lead tips to be planar within ±O,051 (0.002) exclusive of solder.:::rQ) ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES::lCrQ)cQ).....Q)III4-4 TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

MECHANICAL DATAD plastic "small outline" packagesEach of these "small outline" packages consists of a circuit mounted on a lead frame and encapsulatedwithin a plastic compound. The compound will withstand soldering temperature with no deformation, andcircuit performance characteristics will remain stable when operated in high-humidity conditions. Leadsrequire no additional cleaning or processing when used in soldered assembly.16-PIN 0 PACKAGEf6,20 (0.244)93,81 (0.150)8~Ir---------------~I1,75 (0.069)1,35 (0.053)0,102 (0.004)0,79 (0.031)0,28 (0.011),... 7° NOMI 4 PLACESj l 0,457PIN SPACING1,27 (0.050)See Note a(0.018)0,356 (0.014)5,21 (0.205)050 (0.020) {4'60 (0'181)~ 0,229 (0.0090), X 45° 0,190 (0.0075)0,25 (0.010) I ~7° NOM Jl4 PLACESdJ(I~~JLt 4°±~01,12 (0.044)0,51 (0.020)NOTES: A. Body dimensions do not include mold flash or protrusion.B. Mold flash or protrusion shall not exceed 0,15 (0.006).C. Leads are within 0,25 (0.010) radius of true position at maximum material dimension.D. Lead tips to be planar within ± 0,051 (0.002) exclusive of solder.ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHESco+JCOCC6.2s:::CO..s:::::CJQ)~IIITEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-5

MECHANICAL DATAow plastic "small outline" packagesEach of these "small outline" packages consists of a circuit mounted on a lead frame and encapsulatedwithin a plastic compound. The compound will withstand soldering temperature with no deformation, andcircuit performance characteristics will remain ,stable when operated in high-humidity conditions. Leadsrequire no additional cleaning or processing when used in soldered assembly.20·PIN ow PACKAGEr 10.65 (0.419) 2010.15 (0.400)r-:~:~:~::~::----'rr=m-~ ~ ~7.55 (0.297)-~ ~ ~ ~ I11""I"M' 1}G)~1~ ______________________ ~1~041sCD(")::rQ):::IC:)"Q)oQ)r+•Q)~r70NOM4 PLACES2.65 (0.104)"'~J~I - I - I I 0,490(0.019)0'30~.(0'012) -0.10 (0.004) I I -+I 14- 0.350 (0.014)0.785(0.031) ~' I0.585 (0.023)1.27 (0.050) TPNOTES: A. Body dimensions do not include mold flash or protrusion.B. Mold flash or protrusion shall not exceed 0,15 (0.006).C. Leads are within 0.25 (0.010) radius of true position at maximum material dimension.D. Lead tips to be planar within ± 0.051 (0.002) exclusive of solder.ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES\-7 0 NOM 1.27 (0.050) I I4 PLACES ~--t.-..I4-6TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

MECHANICAL DATAOW plastic "small outline" packagesEach of these "small outline" packages consists of a circuit mounted on a lead frame and encapsulatedwithin a plastic compound. The compound will withstand soldering temperature with no deformation, andcircuit performance characteristics will remain stable when operated in high-humidity conditions. Leadsrequire ,no additional cleaning or processing whim used in soldered assembly.24-PIN OW PACKAGE15'5(0'610)~15,3 (0.602)- - - - -13120,785 (0.031)0,585 (0.023)NOTES: A. Body dimensions do not include mold flash or protrusion;B. Mold flash or protrusion shall not exceed 0,15 (O.0061.C. Leads are within 0,25 (O.OlO) radius of true position at maximum material dimension.O. Lead tips to be planar within ±0,051 (0.002) exclusive of solder.I::::~:~::I0,5(0.02)X45"LI=-r- ~ IkJ!j .. II~ 7° NOM lJ140 ±4° \-4 PLACES0,320 (0.013) 1,27 (0.050)0,230 (0.009) 0.40 (0.016)ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES.... coCOCC6(.)"2COJ:(.)Q)~aTEXAS -II}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-7

MECHANICAL DATAFK ceramic chip carrier packagesEach of these hermetically sealed chip carrier packages has a three-layer ceramic base with a metal lidand braze seal. The packages are intended for surface mounting on solder lands on 1.27 (O.050-inch)centers. terminals require no additional cleaning or processing when used in soldered assembly.FK package terminal assignments conform to JEDEC Standards 1 and 2.FK CERAMIC CHIP CARRIER PACKAGES(28-terminal package shown)CERAMIC CHIP CARRIERSJEDECOUTLINEDESIGNATION"MS004CB 20MS004CC 28NO.OFATERMINALS MIN MAX8.69 9.0910342) 10.358)11,23 11,6310.4421 10.4581MINBMAX7.80 9,0910.307) 10.358)10,31 11,6310.406) 10.4581* All dimensions and notes for the specified JEDEC outline apply.cQ),....Q)II~I~I~0,56 (O,022)-+j~ 1.63 (0,064)ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES4-8, TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

MECHANICAL DATAFN plastic chip carrier packageEach of these chip carrier packages consists of a circuit mounted on a lead frame and encapsulated withinan electrically nonconductive plastic compound. The compound withstands soldering temperatures withno deformation, and circuit performance characteristics remain stable when the devices are operated inhigh-humidity conditions. The packages are intended for surface mounting on solder lands on 1,27 (0.050)centers. Leads require no additional cleaning or processing when used in soldered assembly.FN PLASTIC CHIP CARRIER PACKAGE(28-terminal package used for illustration)1,22 (0.048) X 4501,07 (0.042)o28 27 26252423[It:::] ;::: ::::::1,35 (0.053) X 45° . 0,94 (0.037)1,19 (0.047) / 0,69 (0.027) RRMAX:1dC.I:,::I:A~::'.U'"- - - (See Note B)--- ,I-~;:::::::o/,ISEATING PLANE(See Note C)JEDECOUTLINEMO 047AAMO 047ABMO 047ACMO 047AENO. OFTERMINALS MIN MAX MIN20284468A9.78 10.03 8.89103851 103951 10.350112.32 12.57 11.4310.4851 10.4951 10.450117.40 17.65 16.51106851 106951 10650125.02 25.27 24.1310.9851 10.9951 109501All dimensions and notes for the specified JEDEC outline applyMAXMIN9.04 7.87103561 10.310111.58 10.4110.4561 10.410116.66 15.4910.6561 10.610124.33 23.1110.9561 109101MAX8.3810330110.9210.430116.0010630123.621093010,81 (0.032)-H0,66 (0.026) w f1,52 (0.060) MIN- I -*-I ~4 (0.025) MINI-.i:.~:~~ :~:~~~: ~ I ~LEAD DETAILNOTES; A. Centerline of center pin each side is within 0,10 (0.004) of package centerline as de'termined by dimension B.B. Location of each pin is within 0,127 (0.005) of true position with respect to center pin on each side.C. The lead contact points are planar within 0,10 (0.004).ALL LINEAR D)MENSIONS ARE )N MILLIMETERS AND PARENTHETICALLY IN INCHESm(.)"2m..c(.)Q)~IITEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-9

MECHANICAL DATA68-pin GB pin grid array ceramic packageThis is a hermetically sealed ceramic package with metal cap and gold-plated pins.68·PIN GB PACKAGEcQ),....Q)IITOPVIEW4.57 (0.180)IIIIlJ120)13.5 (0.530)NOM1----oBoI,::~,':.~~ti-~' IT IT,1 Lll [m~:.:.~::o:~::2.39 (0.094) 0.406 (0 016) 1.12 (0.044)2.54 (0.100) T.P.M~-±~~~~~~~------~L 1°00000008- 1(£) 0 000 0 0 0008·-+J 00 00 2.54 (0.100) T.P.H00 00G00 00B~~:~M F 0 0 0 0E00 00000 00c00 00B00000000000A~. 000000008--1.. 1. 27(0.050)INDEX2 3 4 5 6 7 B 9 10 11 L NOM(5•• Not. A)NOTE A: Pins are located within 0,127 (0.005) radius of true position relative to each other at maximum material condition and within0,254 (0.010) radius relative to the center of the ceramic.ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES4-10 TEXAS ..INSTRUMENlSPOST OFF)CE BOX 225012 • DALLAS. TEXAS 75265

MECHANICAL DATAJ ceramic packages (including JO, JT, and JW dual-in-line packages)Each of these hermetically sealed dual-in-line packages consists of a ceramic base, ceramic cap, and alead frame. Hermetic sealing is accomplished with glass. The packages are intended for insertion inmounting-hole rows on 7,62 (0.300) or 15,24 (0.600) centers. Once the leads are compressed and insertedsufficient tension is provided to secure the package in the board during soldering. Tin-plated ("brightdipped")leads require no additional cleaning or processing when used in soldered assembly.NOTE: For the 14-, 16-, and 20-pin packages, the letter J is used by itself since these packages are available only in the 7,62 (0.300)row spacing. For the 24-pin packages, if no second letter or row spacing is specified, the package is assumed to have 15,24 (0.600)row spacing.14-PIN J CERAMIC~:~: :~:~~~: 14 PLACESALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES16-PIN J CERAMICI 19.9410.785} ~.~"=,,,,"{~~~~:!jIi. Ii.Ih rl~,!;~::~tr\105' -SEATINGPLANE--....---,--If.W; • 19,18 (0.755) I I00000000~~~~~~~~~~S~~~~T111+1+--++--ttto.6i21~~~~~~IN16 PLACES ~I- ~:~~ :~:~~:: j~~ 16 PLACES16 PLACES -II~ 0.3810.015}~:~~ :~:~~~: 4 PLACES• For memories of 64 bits and up and a few MSI/LSI products in Series 54/74 and Series 5451745that are derived from memory circuit bars, this maximum is 7,62 (0.300). All other dimensions applywithout modification.ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES....coCOCCOCJ'2CO..cCJQ)~IINOTE A: Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.TEXAS ~INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-11

MECHANICAL DATAJ ceramic dual-in-line packages (continued)20-PIN J CERAMICClgCl ~:~~ :~.~;~:7,62 (0 300)6,22 (0 245)24,76 (0.975)""'1">-----23,62 (0.930) -----.l_1.~," .. "".{~~~~~~~~j1 1,27 (0 050) NOM~05. _S;~~~~G --'--y---.-90 MIN20 PLACES -.--_____ y~\.- ~:~~ \~:~~:\20 PLACESGLASSSEALANT0,58 (0.023)0,38 (0.015)20 PLACESALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES24-PIN JT CERAMIC, O,300-INCH ROW SPACINGf4------31,8 (1.250) MAX----....,.jGLASSSEALANT10-gar24 PLACES0,36 (0.014)--.\r-0,20 (0.008)24 PLACESSEA TlNG-r-''----...-I-,PLANEIII '------------'ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHESNOTE A: Each pin centerline is located within 0,25 (0,010) of its true longitudinal position,4-12 TEXAS -Ij}INSTRUMENTSPOST OFFICE BOX 225012 - DALLAS, TEXAS 75265

MECHANICAL DATAJ ceramic dual-in-line packages (continued)24-PIN JW CERAMIC~---------;~:~:~:;;~:----------~@@@@@@@@@@@@0.63 10.0251 RNOMCD®00®@0®®@@@~------------

MECHANICAL DATAJ ceramic dual-in-line packages (continued)This is a hermetically sealed ceramic package with a metal cap and side-brazed tin-plated leads.JD CERAMIC-SIDE BRAZE~~N :. ==~_B_MAX~~~~~~'I(DD~~~~A:~:'----' n 0 uTbJ l D' NUM,,", -LC0--------------------~ct.ct.I4-A----tf 1,7B (0.070)1 __ I 0,51 (0.020) MIN 0,76 (o.o~O)j t ,- SEATING~mmtlmmm5,08(0.200)MAX i',";: PLAN'~ :;J( 3.181O.~2S( M"II 0,38 (0.015) 1,91 (0.075) MAX ..j 1+-1 j-..jj.- 0,20 (0.008) -.I 1+-2,54 (0.100) NOM 0,53 (0.021)~~~eS~:~I~~ 0.38 (0.015)~ DIM16 18 20 22 24A +0.51 (+0.020) 7,62 7,62 7.62 7.62 7.62-0.25 (-0.010) (0.300) (0.300) (0.300) (0.300) (0.300)B.(MAX) 20,57 23.11 25,65 27.94 30,86(0.810) (0.910) (1.010) (1.100) (1.215)C (NOM) 7.37 7,37 7.37 9,91 7.37(0.290) (0.290) (0.290) (0.390) (0.290)cQ)r+Q)DIM ~24 28 40 48 52 64A +0.51 (+0.020) 15.24 15.24 15,24 15.24 15,24 22.86- 0.25 (- 0.01 0) (0,600) (0.600) (0.600) (0.600) (0.600) (0.900)B(MAX) 31.8 . 36.8 52.1 62,2 67.3 82.6(1.250) (1.450) (2.050) (2.450) (2.650) (3.250)C (NOM) 15,0 15.0 15.0 15.0 15,0 22,6(0.590) (0.590) (0.590) (0.590) (0.590) (0.890)ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHESNOTE A: Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.4-14 TEXAS ..INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

MECHANICAL DATAN plastic packages (including NT and NW dual-in-line packages)Each of these dual-in-line packages consists of a circuit mounted on a lead frame and encapsulated withinan electrically nonconductive plastic compound. The compound will withstand soldering temperature withno deformation, and circuit performance characteristics will remain stable when operated in high-humidityconditions. The packages are intended for insertion in mounting-hole rows on 7,62 (0.300). 15,24 (0.600),or 22,86 (0.900) centers. Once the leads are compressed and inserted, sufficient tension is provided tosecure the package in the board during soldering. Leads require no additional cleaning or processing whenused in soldered assembly.NOTE: For all except 24-pin packages, the letter N is used by itself since only the 24-pin package is available in more than one row-spacing.For the 24-pin package, the 7,62 (0.300) version is designated NT; the 15,24 (0.600) version is designated NW. If no secondletter or row-spacing is specified, the package is assumed to have 15,24 (0.600) row-spacing.14-PIN N PLASTIC . 19.B (0.7BOI~ lB.O (0.7101

MECHANICAL DATAN plastic dual-in-line packages (continued)20-PIN N PACKAGE7,62 ± 0,25(0.300 ± 0.010)2,0 (0.080) NOM(+------ ~~:~~ :~::~::-----.!(See Note B)(See NoteA)sCD('):rQ):::sC:;"e!-OQ)r+Q)H:::: ::::::J t4 PLACESVIEWAParts may be supplied in accordancewith the alternate side view at theoPtion of TI. European-manufacturedparts may have pin 1 as shown inview A. Alternate-side·view partsmanufactured outsKi. of the USAmay have a maximum package lengthof 26,711.050).NOTES: A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.B. For solder-dipped leads, this dimension applies from the lead tip to the standoff.C. Parts may be supplied with a draft angle of 7 0 typical at the option of TI.ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES4-16 TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

MECHANICAL DATAN plastic dual-in-line packages (continued)24-PIN NT PLASTIC)4--------31,8 (1.250) _______ ---0126.6 (1.125!~7'62±0'25(0.300 ± 0.010)7.1 (0.280) MAX-1 2.0 (0.080) NOM__ J..51 -:-T0.25 (0.010) NOM-SEATING PLANE105'goo24 PLACES J\-0.36 (0.014)\ 0.25 (0.010)24 PLACES(S.e Note B)':::.::.::=1:: vv: v v: V: I0.38 (0.015)00000000008@MIN 1.78 (0.070)-1 r--l.14 (0.045) 24 PLACES5.08 (b200) ~iM1AX -'fJ- -.jIIr- l• 14(0045)MIN24 PLACES4.06 (0.160)- ~ ~ .-J L 0.533 (0 021)"I r-0.381 (0015)3.17 (0.125) 24 PLACES2.16 (0 085) (S.e Note B)0.71 (0028) PIN SPACING 2.54 (0 100) T P.4 PLACES (Se. Note A)NOTES: A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.B. For solder-dipped leads, this dimension applies from the lead tip to the standoff.ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES...., coCOCCOC.,)°2CO~C.,)Q)•2TEXAS ".!}INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265.4-17

MECHANICAL DATAN plastic dual-in-line packages (continued)24-PIN NW PLASTIC32,8 (1,2901 MAX-----+I@@@@@@@@@@@@14'~6~550112,0 (0.0801 NOMCD CD @ 0 ® ® 0) ® ® @ @ @H ~25 (0.0101 NOM -1 r 1,78 (0.0701 MAX 24 PLACESJ L -Ij~_.-__ -u-,- ..J ~ ~-. 5,08 (0.2001 MAX-SEATINGPLANE.--~ 24 PLACES 0,51 (0.0201 MIN _0,28 t 0,08 -Ii'"""" J I ~ 0,83 (0.0331 MIN J 3,17 (0.1251 MIN(0.011 t 0.0031 24 PLACES I~' 24 PLACES24 PLACES O,457:t 0,076 I+- 2,42 (0.0951 MAX l-(See Note BI (0.018:t 0.0031 4 PLACES24 PLACES PIN SPACING 2,54 (0.1001 T. P.(See Not. BIISe. Note AIALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES28-PIN N PLASTIC1------36,6 (1.4401 MAX----~sCD(")::rD,):JO·D,)oD,),..D,)III«itr,(d~:::OOO~~1'j"'~~~~r---O) ---r. .J.. 5.08 (0.2001 MAXJ lt -_SEATING PLANE105 -r-. 0 ~ 3,17 10.1251 MIN11 (0.01 1 , 0.0031 (0.018! 0:0031..1 10- j 0,84 (0.0331 MIN90° 0,28 ! 0.08 0 46 ~ 0 08PIN SPACING 2,54 (0.1001 T. P., (See Not. AI 1,52 (0.0601 NOMALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHESNOTES: A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.B. For solder-dipped leads, this dimension applies from the lead tip to the standoff.(O~~~ : ~:~~Ol4-18 TEXAS •INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

MECHANICAL DATAN plastic dual-in-line packages (continued)40-PIN N PLASTIC, I' 53,1 (2.090) MAX I""~~~:~::~

II4-20

TI Sales Offices .TI DistributorsALABAMA: Huntsville (205) 837·7530.ARIZONA: Phoenix (602) 995·1007;Tucson (602) 624·3276.CALIFORNIA: Irvine (714) 660·8187;Sacramento (916) 929·1521;~:~t~l~r:'~~!6k~~~o~~bb;Torrance (213) 217·7010;Woodland Hills (818) 704·7759.COLORADO: Aurora (303) 368·8000.CONNECTICUT: Wallingford (203) 269·0074.FLO RI DA: Ft Lauderdale (305) 973·8502;Maitland (305) 660·4600; Tampa (813) 870·6420.GEORGIA: Norcross (404) 662·7900.ILLINOIS: Arlington Helghls (312) 640·2925.INDIANA: Ft Wayne (219) 424·5174;Indianapolis (317) 248·8555.IOWA: Cedar Rapids (319) 395·9550.MARYLAND: Baltimore (301) 944·8600.MASSACHUSETTS: Waltham (617) 895·9100.MICHIGAN: Farmington Hills (313) 5531500;Grand Rapids (616) 957·4200.MINNESOTA: Eden Prairie (612) 828·9300.~t~S~~~sR!31K~n56'::.7~~6. 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CompanyGraham ElectronicsKierulff ElectronicsMarshall IndustriesMilgray ElectronicsNewark ElectronicsTime ElectronicsR.V. Weatherford Co.Wyle Laboratories, .Zeus Component, Inc. (Military)TI AUTHORIZED DISTRIBUTORS INCANADAArrow Electronics CanadaFuture ElectronicsTI AUTHORIZED DISTRIBUTORS INUSA-OBSOLETE PRODUCT ONLYRochester Electronics, Inc.Newburyport, Massachusetts(617) 462·9332ALABAMA: Arrow (205) 837·6955;Kierulff (205) 883-6070; Marshall (205) 881 ·9235.ARIZONA: Arrow (602) 968·4800;Kierulff (602) 437·0750; Marshall (602) 968·6181;Wyle (602) 866·2888.CALIFORNIA: Los AngeleslOrange County:Arrow (818) 701·7500, (714) 838·5422;Kierulf! (213) 725·0325, (714) 73,·57", (714) 220·6300;Marshall (818) 999·5001, (818) 442·7204,(714) 660·0951; R.V. Weatherford (714) 966·1447,(213) 849·3451, Wyle (213) 322·8100, (818) 880·9001,(714) 863·9953; Zeus (714) 632-6880;Sacramento: Arrow (916) 925·7456;Marshall (916) 635·9700; Wyle (916) 638·5282;San Diego: Arrow (619) 565·4800;Kierulf! (619) 278·2112; Marshall (619) 578·9600;Wyle (619) 565·9171;San Francisco Bay Area: Arrow (408) 745-6600;(415) 487·4600; Kierulff (408) 971·2600;Marshall (408) 943·4600; Wyle (408) 727·2500;Zeus (408) 998·5121.COLORADO: Arrow (303) 696·1111;Kierulff (303) 790·4444; Wyle (303) 457·9953.CONNECTICUT: Arrow (203) 265·7741;Diplomat (203) 797·9674; Kierulff (203) 265·1115;Marshall (203) 265·3822; Milgray (203) 795·0714.FLORIDA: Ft Lauderdale: Arrow (305) 429·8200;Diplomat (305) 974·8700; Kierulff (305) 486·4004;Orlando: Arrow (305) 725·1480;Marshall (305) 841·1878; Milgray (305) 647·5747;Zeus (305) 365·3000; Tampa: Arrow (813) 576·8995;Diplomat (813) 443·4514; Kierulf! (813) 576·1966.TEXASINSTRUMENTSCreating useful productsand services for you.GEORGIA: Arrow (404) 449·8252;Kierulf! (404) 447·5252; Marshall (404) 923·5750.ILLINOIS: Arrow (312) 397·3440;Diplomat (312) 595·1000; Kierulff (312) 250·0500;Marshall (312) 490·0155; Newark (312) 784·5100.INDIANA: Indianapolis: Arrow (317) 243·9353;Graham (317) 634·8202; Marshall (317) 297·0483;Ft Wayne: Graham (219) 423·3422.IOWA: Arrow (319) 395·7230.~~~~!~:(:;a3)s::21\t!i.Arrow (913) 642·0592;MARYLAND: Arrow (301) 995·0003;Diplomat (301) 995·1226; Kierulff (301) 636·5800;Milgray (301) 995·6169; Marshall (301) 840·9450;Zeus (301) 997·1118.MASSACHUSETTS: Arrow (617) 933·8130;Diplomat (617) 935-6611; Kierulf! (617) 667·8331;Marshall (617) 272-8200; Time (617) 532·6200;Zeus (617) 863·8800.MICHIGAN: Detroit: Arrow (313) 971·8220;Marshall (313) 525·5850; Newark (313) 967-0600;Grand Rapids: Arrow (616) 243·0912.MINNESOTA: Arrow (612) 830·1800;Kierulf! (612) 941·7500; Marshal: (612) 559·2211.MISSOURI: St. Louis: Arrow (314) 567·6888;Kierulf! (314) 739·0855.NEW HAMPSHIRE: Arrow (603) 668-6968.NEW JERSEY: Arrow (201) 575·5300, (609) 596·8000;Diplomat (201) 785·1830;General Radio (609) 964·8560; Kierulf! (201) 575-6750;(609) 235·1444; Marshall (201) 882·0320,(609) 234·9100; Milgray (609) 983·5010.NEW MEXICO: Arrow (505) 243·4566.NEW YORK: Long Island: Arrow (516) 231·1000;Diplomat (516) 454·6400; Marshall (516) 273·2053;Milgray (516) 420·9800; Zeus (914) 937·7400;Rochester: Arrow (716) 427·0300;Marshall (716) 235·7620;~r~fg~~~'

TI WorldwideSales OfficesALABAMA: Huntsville: 500 Wynn Drive, Suite 5'4,Huntsville, AL 35B05, (205) 837·7530.ARIZONA: Phoenix: 8825 N. 23rd Ave., Phoenix,AZ 8502', (602) 995·'007.CALIFORNIA: Irvine: 1789' Cartwright Rd., Irvine,CA 92714, (7'4) 660·8'87; Sacramento: '900 PointWest Way, Suite 17', Sacramento, CA 958'5,~~I~~ 9J:'~~~' bf:gno~!!2~2~~~~ (~\~) 2~~~0~;ve.San!a Clara: 5353 Bet?, Ross Dr., Santa Clara, CA~~~~:n~:?~1~~i2'3)'2~~~0~r Knox St.,Woodland Hills: 2'220 Erwin St., Woodland Hills,CA 9'367, (818) 704·7759.COLORADO: Aurora: '400 S. Polomac Ave.,Suite 10', Aurora, CO BOOI2, .(303) 368·8000.CONNECTICUT: Wallingford: 9 Barnes IndustrialPark Rd., Barnes Industrial Park, Wallingford,CT 06492, (203) 269·0074.FLORIDA: Ft. Lauderdale: 2765 N.w. 62nd St.,Ft. Lauderdale, FL 33309, (305) 973·8502;Maitland: 260' Maitland Center Parkway,Maitland, FL 32751, (305) 660·4600;Tampa: 5010 W. Kennedy Blvd., Suite 10',Tampa, FL 33609, (8'3) 870-6420.GEORGIA: Norcross: 55'5 Spalding Drive, Norcross,GA 30092, (404) 662·7900~r~ll~g?~~: ~~~~t~~~LH~~~~:(~~~) ~40~J~~~qUin,:~~:8~~,: (~~'9~:I:;~$~~0 Inwood Dr., Ft. Wayne,Indianapolis: 2346 S. Lynhurst, Suite J·400,Indianapolis, IN 4624', (317) 248·8555.IOWA: Cedar Rapids: 373 Collins Rd. NE, Suite 200,Cedar Rapids, IA 52402, (319) 395·9550.MARYLAND: Baltimore: , Rulherford PI.,7'33 Rutherford Rd., Baltimore, MO 2'207,(301) 944·8600.MASSACHUSETTS: Waltham: 504 Totten Pond Rd.,Waltham, MA 02'54, (617) 895·9'00.~~~~~~~~~ ~rl~I~I~~~gl(~n7;l3~5Jl Mile Rd.,MINNESOTA: Eden Prairie: "000 W. 78th St.,Eden Prairie, MN 55344 (6'2) 828·9300.MISSOURI: Kansas City: 80BO Ward Pkwy., KansasCity, MO 64"4, (8'6) 523-2500;51. Louis: "8'6 Borman Drive, St. Louis,MO 63'46, (3'4) 569-7600.NEW JERSEY: Iselin: 485E U.S. Route' Soulh,Parkway Towers, Iselin, NJ 08830 (20') 750·'050NEW MEXICO: Albuquerque: 2820·D Broadbent PkwyNE, Albuquerque, NM 87'07, (505) 345-2555.NEW YORK: East Syracuse: 6365 Collamer Dr., EastSyracuse, NY '3057, (3'5) 463·929';Endicott: "2 Nanticoke Ave., P.O. Box 6'8, Endicott,NY '3760, (607) 754·3900; Melville: , HuntingtonQuadrangle, Suite 3C'0, P.O. Box 2936, Melville,NY '1747, (516) 454-6600; Pittsford: 285' Clover St.,Pittsford, NY '4534, (7'6) 385-6770;Poughkeepsie: 385 South Rd., Poughkeepsie,NY '260', (9'4) 473-2900.NORTH CAROLINA: Charlotte: 8 Woodlawn Green,Woodlawn Rd., Charlotte, NC 282'0, (704) 527-0930;~~e49~kl.~~~iBP;~72d5s Blvd., Suite '00, Raleigh,OHIO: Beachwood: 23408 Commerce Park Rd.,Beachwood, OH 44'22, (2'6) 464-6'00;g~~5~3~:(~f~)~~J~3~7i'24 Linden Ave., Dayton,OREGON: Beav.rton: 6700 SW '05th St., Suite "0,Beaverton, OR 97005, (503) 643-6758.PENNSYLVANIA: Ft. Washington: 260 New York Dr.,Ft. Washington, PA '9034, (2'5) 643·6450;Coraopolis: 420 Rouser Rd., 3 Airport Office Park,Coraopolis, PA '5'08, (4'2) 77'-8550.PUERTO RICO: Hato Rey: Mercantil Plaza Bldg.,Suite 505. Hato Rey, PR 00919, (B09) 753-8700.TEXAS: Austin: P.O. Box 2909, Austin, TX 78769,(512) 250-7655; Richardson: 1001 E. Campbell Rd.,Richardson, TX 75080,(2'4) 680-5082; Houston: 9'00 Southwest Frwy.,Suite 237, Houston, TX 77036, (7'3) 778-6592;San Antonio: '000 Central Parkway South,San Antonio, TX 78232, (5'2) 496·1779.UTAH: Murray: 520' South Green SE, Suite 200,Murray, UT 84'07, (BO,) 266·8972.VIRGINIA: Fairfax: 2750 Prosperity. Fairfax, VA22031, (703) 849-1400.WASHINGTON: Redmond: 50'0 '48th NE, Bldg B,Suite '07, Redmond, WA 98052, (206) 881·3080.WISCONSIN: Brooklleld: 450 N. Sunny Slope,Suite 150, Brookfield, WI 53005, (4'4) 785·7140.CANADA: Nepean: 30' Moodie Drive, MallornCenter, Nepean, Ontario, Canada, K2H9C4,Wi~3~~~~;J9~~i ~!~h"'~~~~~~~i;,8ga~~~~e St. E,(4'6) 884·9'8'; St. Laurent: Ville St. Laurent Quebec.~~~~J~a~~s~R;'~~,~ili'5~8t39~~urent, Quebec,ARGENTINA: Texas Instruments ArgentinaS.A.I.C.F.: Esmeralda '30, '5th Floor, '035 BuenosAires, Argentina, , + 394·3008.AUSTRALIA (l NEW ZEALAND): Texas InstrumentsAustralia Ltd.: 6·10 Talavera Rd., North Ryde(Sydney), New South Wales, Australia 2113,2 + 887·"22; 5th Floor, 4'8 St. Kilda Road,Melbourne, Victoria, Australia 3004, 3 + 267-4677;17' Philip Highway, Elizabeth, South Australia 5"2,8 + 255·2066.AUSTRIA: Texas Instruments Ges.m.b.H.:~2~~~~:~~O~be B/'6, .A·2345 Brunn/Geblrge,~~~~~~Mde~~::~ ~~~~t~~:~:~~~ R~:IS~U~ ~~~~e,"30 Brussels, Belgium, 2/720.BO.00.BRAZIL: Texas Instruments Electronlcos do Brasil~~~a~a~~~, ~ar~iI~e06~5~~U Andar Plnhelros, 05424DENMARK: Texas Instruments AIS, Malrelundvej46E, DK·2730 Herlev, Denmark, 2 • 9' 7400.FINLAND: Texas Instruments Finland OY:Teoilisuuskatu '9D 005" Helsinki 5', Finland, (90)70'·3133.FRANCE: Texas Instruments France: Headquartersand Prod. Plant, BP 05, 06270 Vllleneuve·Loubet, .(93) 20·0,-Ql; Paris Office, BP 67 6·'0 AvenueMorane·Saulnler, 78'4' Velizy·Viliacoublay,(3) 946·97·'2; Lyon Sales Office, L'Oree D'Ecully,Batlment B, Chemin de la Forestiere, 69'30 Ecully,~~ ~;~~~g~~t6~~~~us~r~:~~~~fg~~'e~~ Sebastopol~Bfl~2ri~:n6~:.(gme;i.~:~; ~~~I~~:au~~I~a~~~~e,Le Perlpole-2, Chemin du Plgeonnler de la Ceplere,3'100 Toulouse, (61) 44·'8-'9; Marseille Sales Office,Noilly Paradls-'46 Rue Paradis, '3006 Marseille,(91) 37·25·30.~TEXASINSTRUMENTSCreating useful productsand services for youGERMANY (Fed. Republic of Germany): TexasInstruments Deulschland GmbH: Haggertystrasse 1,D·B05O Freising, 8'6' +BO·4591; Kurfuerstendamm'95/196, D·looo Berlin '5, 30+882·7365; III, Hagen43/Kibbelstrasse, ,'9, D·4300 Essen, 20'·24250;Frankfurter Allee 6·8, 0-6236 Eschborm "06'96 + B070; Hamburgerstrasse ", 0·2000 Hamburg76,040+220·'154, Klrchhorsterstrasse 2, D·3000~~~~~v~~;fll'd~~~ ~~~:l~~~~al,b,a~~wg8f; '1,~~\~~~1~~31Jl9, ~~:~t7aas~~u,re, ~5:g0+ ~~~I~~';26' +35044.HONG KONG (+ PEOPLES REPUBLIC OF CHINA):Texas Instruments Asia Ltd., 8th Floor, WorldShipping Ctr., Harbour City, 7 Canton Rd., Kowloon,Hong Kong. 3 + 722·'223.IRELAND: Texas Instruments (Ireland) Limited:Brewery Rd., Stillorgan, County Dublin, Eire,'8313".ITALY: Texas Instruments Semiconduttorlltalia Spa:Viale Delle Sclenze, ',020'5 Clttaducale (Rieti),Italy, 746 694.'; Via Salarla KM 24 (Palazzo Cosma),Monterotondo Scalo (Rome), lIaly, 6+9003241; VialeEuropa, 38·44, 20093 Cologno Monzese (Milano),2253254'; Corso Svlzzera, 185, '0100 Torino, Italy," 774545; Via J. Barozzl 6, 40100 Bologna, Italy, 5'35585'.JAPAN: Texas Instruments Asia Ltd.: 4F Aoyama~~~y~~~~p~~' ~b~I~-4~~2'~~; l1~~~~~ra~~n;,tgt,u,Nlssho Iwal Bldg., 30 Imabashl 3· Chome,Hlgashl·ku, Osaka, Japan 54', 06·204·'88'; NagoyaBranch, 7F Daini Toyota West Bldg., '0-27, Melekl4·Chome, Nakamura·ku Nagoya, Japan450, 52·583·869'.KOREA: Texas Instruments Supply Co.: 3rd Floor,~~;:'~~0~:~~o~~~~a:n4~~88bfangnam.ku,MEXICO: Texas Instruments de Mexico SA: Mexicog~~: ~6~fg'.'"5~Zf60~0 - 10th Floor, Mexico,MIDDLE EAST: Texas Instruments: No. 13, 1st FloorMannal Bldg., Diplomatic Area, P.O. Box 26335,Manama Bahrain, Arabian Gulf, 973 + 27468'.NETHERLANDS: Texas Instruments Holland B.V.,P.O. Box '2995, (Bullewijk) 1100 CB Amsterdam,Zuld-Oost, Holland 20+56029".~~~~:~hi.eb~~d~~t~uo~~~~ (~)or~;6~:S: PB106,PHILIPPINES: Texas Instruments Asia Ltd.: '41h~~~~i;~~e~~g:!~I~i,d~hl~~~rn~:~~~ g~~~~~~,PORTUCAL: Texas Instruments Equlpamento5:~I~~~~~c5~ (~~7~?:15aL~~ja~~~7~n~:~~%~~~~al,2·948·'003.~~NA~t:~~N:x~~?~~lr~~~~E~~~ ~~~~~S~~;ongBakar Batu, Unit OHl2, Kolam Ayer Industrial Estate,Republic of Singapore, 747·2255.SPAIN: Texas Inslruments Espana, SA: CIJoseLazaro Galdlano No.6, Madrid '6, "458.'4.58.SWEDEN: Texas Instruments International TradeCorporation (Sverlgelilialen):Box 39'03, '0054Stockholm, Sweden, 8· 2354BO.SWITZERLAND: Texas Instruments, Inc., Reidstrasseh~~'~~ig Dietlkon (Zuerich) i/witzerland,TAIWAN: Texas Instruments Supply Co.: Room 903,205 Tun Hwan Rd., 7' Sung·Klang Road, Taipei,Taiwan, Republic of China, 2 + 52'·932'.UNITED KINGDOM: Texas Instruments Limited:Manton Lane, Bedford, MK4' 7PA, England, 023467466; St. James House, Wellington Road North,Stockport, SK4 2RT, England, 6' +442·7'62.BM

Please send me the following Texas Instruments Bit-Slice ProcessorUser's Guide(s):DB01 0 SN74AS888/890, 8-Bit-Slice Processor User'sGuideDB02 0 SN74AS897, 16-Bit Barrel Shifter User's GuideDB03 0 74AS-EVM-8, Bit-Slice Evaluation Module User'sGuideNAME 1 1 1 1 1 1 1 1 1 1 1 1 1 1TITLE 1 1 1 1 1 1 1 1 1 1 1 1 1 1COMPANY I 1 1 1 1 1 1 1 1 1 1 1 1 1 1ADDRESS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11.-1 ---1...-1_L---JL---J'-----J'-----J'-----J-----I M / S 1--1 --l,.1-----L....1---1.-1---lCITY 1 1 1 1 1 1 1 liST ATE 1 1 1 ZIP 1 I.-....J...I--....J...-I --1.1--1.-1---lPHONE ( )I~ ~I~I~~~~~I~I EXT. ~I ~I~I~I~SDV011DV600R Expires 5/87Please send me the following Texas Instruments Bit-Slice ProcessorUser's Guide(s):DB01 0 SN74AS888/890, 8-Sit-Slice Processor User'sGuideDB02 0 SN74AS897, 16-Bit Barrel Shifter User's GuideDB03 0 74AS-EVM-8, Bit-Slice Evaluation Module User'sGuideNAME 11...----l,.1____l__1---I.-1 ---l1~1~1~11----l-1____l__1~1 ---l1~1~1~11----l-~1~TIT L E 1.-1 ---ll----,-I ----1-1 --....J...-I ___ II----I.I---...l-I --1.-1 ---1.--1 ---LI--J...I----I-I --....J...-I ___ II----I.----L.-I ____COMPANYI~I--....J...-I_II----I.I---...l-I--I.-I---I.--I ---L1---l..1----L.-1--....J...-1_11----I.1---...l-1--I.-1~ADD RES S ,--I --&.1---,-1 ~I ---&.--1 --.l1~1-----""-1 ---.1--1 -,--I --&.1---,-1 ~I ---&.--1 --.11---....1---11 1 1 1 1 1 1 11M / S II----l--I ----

PLACESTAMPHERETexas InstrumentsLiterature Response CenterP.O. Box 809066Dallas, Texas 75380-9066PLACESTAMPHERETexas InstrumentsLiterature Response CenterP.O. Box 809066Dallas, Texas 75380-9066

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