Professional Documents
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BUGBOOK'V1
. INTRODUCTORY EXPERIMENTS IN DIGITAL
ELECTRONICS, 8080A MICROCOMPUTER PROGRAMMING,
AND 8080A MICROCOMPUTER INTERFACING
OUTPUT
Deaeee DEVICE
Accumulator
n
2
15
Inatruction . oO
register
8-BIT BIDIRECTIONAL DATA BUS
a
ALU =
/
BUFFER
LATCH
Flag flip-fiops 4
Register B za
Register C
INPUT STATUS
DEVICE LATCH
The name BUGBOOK™is a registered trademark, of E&L Instruments, Inc., for a series of books
that provide a laboratory—or experiment-oriented approach to electronic topics. Present and forth-
coming titles in this series include the following:
Bugbook | and ||. Explores the 7500 series of integrated circuits.
Bugbook IIA. The use of asymchronous digital communication techniques, UAR/T devices
and 20mA current loops.
Bugbook II1. Interfacing the 8080A-type microcomputer.
Bugbook IV. Using the 8255-type programmable interfact chip: (in preparation, available Sum-
mer, 1978).
Bugbook V and VI. A combined approach to digital electronics and microcomputer inter-
facing.
Bugbook VII. Microcomputer—Analog Converter Software and Hardware Interfacing.
Bugbook VIII. Assembly language programming for 8080 processors (in preparation, available
Summer, 1978).
Also included are the Bugbook Continuing Education Series books:
BRS-1 The 555 Timer Applications Sourcebook, with Experiments
BRS-2 The Design of Active Filters, with Experiments
BRS-3 DBUG: An 8080 Interpretive Debugger
BRS-4 The Design of Operational Amplifier Circuits, with Experiments
BRS-5 The NCR Basic Electronics Course, with Experiments
BRS-6 The NCR Data Communications Book
BRS-7 Phase-locked Loop Bugbook
In each case the Bugbook provides both text material andsexperiments, which permit one to
demonstrate and explore the concepts that are covered in the book. These books remain among the
very few that provide step-by-step instructions concerning how to learn basic electronic concepts,
wire actual circuits, test microcomputer interfaces and program computers based upon the popular
8080-type microprocessor chip. We have found that the books are very useful to the electronic
novice who desires to join the ‘‘electronics revolution.’ with minimum time and effort.
Bugbooks V and VI are on digital electronics, microcomputer interfacing, and microcomputer pro-
gramming and they are an attempt to integrate these three subjects into a single unified course.
This course is orientated toward laboratory experiments, for we bélieve that this is the best way to
convey the excitement and importance of the microelectronics revolution. The following is a
partial list of topics covered in this book: What is Interfacing?, Device Select Pulses, The 8080A
Distinction Set, Data Bus Techniques, Accumulator Input/Output, Memory Mapped Input/Output,
Flags and Interrupts and more. You will find Bugbook VI is ideal for both self-study and organized
classroom use.
The Bugbooks have been well accepted in the United States and abroad. Selected books are now
being translated into German, Italian, Chinese and Japanese. If you are interested in further details
concerning these translations, contact the series editors. Both domestic and foreign short courses
are available in conjunction with the Extension Division at Virginia Polytechnic Institute and State
University. Please write or call Dr. L. Leffel, Continuing Education Center, VPI & SU, Blacksburg,
VA 24061, phone (703) 951-5241. Short courses on microcomputer interfacing and microcom-
puter software development are given by Tychon, Inc., Blacksburg, VA 24060. For more informa-
tion on these courses, write or call Dr. Christopher Titus, at Tychon, phone (703) 951-9030.
We continue to be interested in identifying other authors who could contribute books to the Bug-
book series. If you have an interest in writing or publishing such a text, please contact one of the
Bugbook series editors.
i edited by
Titus, Titus, Rony & Larsen
INC
BUGBOOK’ V1
INTRODUCTORY EXPERIMENTS IN DIGITAL
ELECTRONICS, 8080A MICROCOMPUTER PROGRAMMING,
AND 8080A MICROCOMPUTER INTERFACING
by
DAVID G. LARSEN PETER R. RONY
Department of Chemistry Department of Chemical Engineering
Published by
[=°
E & LINSTRUMENTS, INC.
61 First Street
Derby, Connecticut 06418
Telephone (203) 735-8774
Copyright © by David G. Larsen, Peter R. Rony, and Jonathan A. Titus 1977
.
Larsen, David G.
The bugbook VI.
Bibliography: p.
1. Microcomputers--Laboratory manuals.
2. Computer interfaces--Laboratory manuals.
3. Digital electronics--Laboratory manuals.
|. Rony, Peter R., joint author. Il. Titus, Jonathan A., joint author.
lil. Title.
QA76.5.L3323 ppl.6’4’04 77-2700
Printed by
Capital City Press
Montpelier, Vermont
BUGBOOK V tia
TABLE OF CONTENTS
PREFACE
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We
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te
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RTTHE
MONINND
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iv
StOrew ACCUM ALOL Dire Chis GV ANn yi lel lo utenteinKei cmon tc siete 3-10
Senile 2 Srmaciench Ul Denn eriow antria trOha. ects te eo ce lo PS Sula
IMIS OO he 0 OO OO oO De OkG a Do mG G5
»
Experiment No. 1.
Experiment No. 2
Experiment No. 3.
Experiment No. 4.
Experiment No. 5
Experiment No. 6
NEVALERT 6 2 og 6 4 0 Fao G6 0 5
ANSWCTS* (.) oeasy oa 0
De Morgan's Theorem . . . .
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ei
(phy
ey
Be
OD
41D
pnt
fed
09
10
1G
Complement Accumulator: CMA
AND Register with Accumulator: ANA S48
Exclusive-OR Register with Accumulator: XRA
OR Register with Accumulator: QRA . .
Immediate Logical Operations: ANT, XRI, and ORT eS
ee
Thiyd Program . . 5 = + . “1 ia Oy
‘ i
Fourth Program... .. . ee Ss ‘
Eli
dd
vii
BUGBOOK VI
TABLE OF CONTENTS
PREFACE
Introduction . A
E7al
Objectives . yi
What is a Device aeleet "pulse? eo. eee oo iat
The Substitution of Software for iaeawane? Uses for Device
Select Pulses . if
Use of Device Select Pulses * perebe aye rectatad areas Chips Ff =3}
Generating Device Select Pulses 17-6
I/O Instructions : fess)
The Fetch, Input, and Gat put fochine Cyoies AS
First Program ol etic sec ches =a
Second Program. . . ° 7 thes thao to Ga chi peo eon 17-18
Introduction to the eepaniments U9
Experiment No. 17-20
Experiment No. 17=23
Experiment No. 25
Experiment No. 7=30
Experiment No. L7=35
Experiment No. 17-40
Experiment No. 17-44
Experiment No. 17-46
Experiment No. DULHLWNE-E
WOMAN 17-49
ROVEOW en elles tes aren Vs (st ee isl cl (ol Usiyeutal “oulenvie) is ES}
ANSWEES! “5 a 6 (6 « = « @ @ 17-54
etal
QUEpULr Drives Capapalaityas tly mr orks sf el isis) Gipise coe, oie ero ne Oma?
Microcomputer Input ... 5 GUO 0s oer SMa oo Gl dete eo Oe)
Some Input Three-state Barter’ Circuits BSG SS Abe Soleo cats ace AUN}
ACCUM acOGey,O mins ELUctlOnS takes ceyaie © his o) Sins se eis are =20=15
Pirseelnpur OULDUEEDEOpramy ris ss) us oss» ae Sh cl enter a) fees gen 20x15
DCCODR ETO Cham maimrege ie “Nea Men nema etc. sso ie) sacle) ei. ke ORL
Their dP Oe Vanes iem ce susie set ne ss) sic) “kbeeee ee Bl a ats te Gils, oe) ORT
HOWL CHE LOCLAM MMs tuctnerm sw cARs Uoettssss sie sc) =) suk si els Ty Gus e OS ty
Fifth Program .. on seers S BAO ORNS ehottier dt ioe Gawd: Ako ae
Introduction to Le eos nee Ge De ON SG Sia se OR cho Gwe ZU Aw
lipgaasliseiNGlarlh 95 te 6 600 Gib m5 o Seo alin Ho Sto 6 ao OSI
lOp.qoyeseshinye No, 7A kes 4G ag GG gd So Gem oud Glos e Gam LUEG
lDpqercimalteynys, INGiS Seo an GO fo ob og 8 0 of oo Td oo ot 2ORs
MENON na amie ees he a ey eee ce Lcl Tuech emanicn ict & Gb ieheca) a perd0 Si)
GW Ot MEM cele Semen ice enram crmalie! ie. (c'* tay Se dcelt ol isl ict aot ao, Ro eee Etoete) MeLO 40)
Introduction . Zoi
Objectives BORIk
What is a Flag? 23=2
First Example: Interfacing a Keyboard 23—2
Second Example: Solvent Level Control 23-6
Polled Operation . 3K,
What is an Interrupt? 23=110)
Types of Interrupts 23d)
Restart: RST X . ESSN.
Enable and Disable Tepetaiee: oe fw os or 23aS,
Third Example: Interrupt-driven Keyboard Interface >. . 23-14
Priority Interrupts 23-18
Hardware Priority iatestoncs 23=2i
Interrupt Software 23-24
Introduction to the pee enone 23-50
Experiment No. 23= 51)
Experiment No. 23-34
Experiment No. 23=37
Experiment No. 23=39
Experiment No. 23-42
Experiment No. 23-46
Experiment 23-49
Experiment 23-54
Experiment 23-58
Experiment 23=63
Experiment 23-69
Experiment 23-75
Review . ee USAT
Answers 23-78
IEPEDICES
bppendiz 1: teferences
- + + + e+ oe
hppendin 2: Definitions, fugoook Vee ee ee ee ew oo TT
hppendix 3: Definit ow af Se en ee a
bypen4iz 4: Outboards Pe ee eg ee ere ee ar ier .
Fower Outboards ++ 6 +e re er cee ener soso een
Logic Switch Outboards -. + + se ee we ew wo oer eevee
LED lamp Monitor Outboards
- - + + ee ee we eo we we oe
Deplay snd Latch/Dieplay Outboards Sot el neg a eo aa
Clock Outhboarde «+ + + re eo ro aya a ee a ea er
Preatboarding Station Outboard ..+ +++ ee a
Decoder Outboard » se ew eee tr owe ww wvrereervves
Wonostable Outboard +--+ + eo th we we re we wee o ee
fateh Cutbeathd oe ne hte he teen Hwanseee nes
Maltiplexer Outboard .- +--+ ee ee oe ev ee 7
Driver/Iaverter/WOR Outboard... - ee ee ee we ae
Univereal Asynchronous Receiver/Transmitter Outboard ...
TUL/2Omh Current Loop Interface Outboard ....--6-.
TEL/BS-232C Interface Outboard 2. 1 ee et ee we ww
Programmable Timer Outboard «+--+ +++ Peres rrr
: hppendix 5: Octal/Wex Conversion Tale ..- +++ +--+ ees
& hppendix 6: Description of the WM-1 Microcomputer
Introduction.
+ ++ce ee eveerevenr
Objectives - 2 + ee eo er eer reves
the WOOO Wicroproceseor Chip... 1 + ee ee ew re we
Fower + + + eer ee oe
——
vw Clock Inpute . 2-2 er eer eo woe *
WD-1 Vicrocomputer
Buses « - - -
fueuc(Outett
op oc te ne we tenner eves
WO-1 Microcomputer: The Overall System ..
How &Z% Operates + + + 6 6 ow we ww wee
How the Microcomputer Operates - - ++ + + «
Appendix 7: Yquipment Inventory for Bugbooks V and VI _* *
hppendin
3: Index 2 - ee er er er wr wr ww rw vere
Rev. 9/22/77
xvi
The information in this book has been checked and is believed to be entirely
reliable. However, no responsibility is assumed for inaccuracies. Furtheremore,
such information does not convey to the purchase of the semiconductor devices
described any license under the patent rights of E&L Instruments, Inc. or others.
E&L Instruments, Inc. reserves the right to change specifications without notice.
PREFACE
Welcome to the new electronics revolution. In ten years, integrated circuit tech-
nology has transformed the digital integrated circuit chip from an expensive
electronic component containing only simple logic functions and few transistors
into a highly complex component containing up to ten thousand transistors. The
computer-on-a-chip is here! It contains everything--central processing unit,
of a digital
read/write memory, read-only memory, and interface circuitry--required
computer. Within several years, you will be able to purchase a handful of such
chips for $100 to $200. By 1982, there may be one billion microcomputers in
Right now, only 250,000 minicomputers and large computers in the United
existence.
States. A computer revolution? Certainly.
In education, we believe that the new electronics revolution will create important
opportunities and changes:
invariant: the
In the face of these changes, one thing will remain essentially
time that a student spends in school. If anything, the number of credit hours
required for graduation will decrease. Educators will be faced with the problem
cutting back on
of incorporating the above topics into various curricula without
other important courses. How can this be done? Perhaps by integrating several
courses together and covering only essential concepts.
Once you have mastered the basic concepts of digital electronics and are knowledge-
able with the techniques of wiring digital circuits using integrated circuit chips,
we expose you to more complicated digital chips and digital systems. You learn
how to wire the universal asynchronous receiver/transmitter (UART) as a digital
communications device between your simple circuits and a teletypewriter. You
learn how to interface an 8080-based microcomputer as well as most of the important
concepts associated with microcomputer programming and interfacing. Work on the
UART chip is performed with the aid of a 70-page Bugbook, Bugbook ITA. Interfacing
& Setentifte Data Communication Experiments Using the Universal Asynchronous
Recetver/Transmitter (UART) and 20 mA Current Loops. The principles and techniques
of 8080-microcomputer interfacing and programming are discussed in the 592-page
Bugbook, Bugbook III. Microcomputer Interfacing Experiments Using the Mark 80 R
Microcomputer, an 8080 System. Bugbook IV, which is on the use of the 8255
programmable peripheral interface chip, is still in pereparation at the time of
writing of this preface. We have delayed it in order to permit the completion of
Bugbooks V and VI.
Bugbooks V and VI, which consist of 23 chapters and 870 pages, is an experiment
in digital electronics education. As mentioned earlier} we are attempting to
integrate the subjects of digital electronics, microcomputer interfacing, and
microcomputer programming into a single unified course.\ In effect, we are
consolidating the material found in Bugbooks I, II, and III into a single labor-
atory textbook. The concepts and techniques of microcomputer programming and
interfacing are discussed at the same time that you learn basic *digital concepts
and perform experiments on popular TTL integrated circuit chips such as the 7400,
7402, 7404, 7442, 7475, 7490, 7493, 74121, 74125, 74126, 74150, 74154, 74181,
and 74193. Some material in the earlier Bugbooks has been omitted, and much
new material added, specially in the microcomputer sections.
We believe that the pendulum of digital electronics will now move steadily
towards the use of microcomputers. Such being the case, there will be consider-
able incentive in educational institutions to introduce microcomputers
at an
early stage in a student's curriculum. What is true for the college student
should also be true for the professional scientist or engineer who desires
to
update his knowledge of digital electronics. Bugbooks V and VI are directed
toward such individuals.
We have also observed a need for additional educational material in the field
of electronics that is experiment-based but is directed towards more specific
topics. This need is being filled by an additional series of Bugbooks called
the Bugbook Application Series. The first book in this series is The 556 Timer
Applications and Sourcebook, with Experiments and is written by Howard Berlin.
Howard has just completed his second book in the series, The Design of Active
Filters, with Experiments, and is currently preparing a third book, Designing
with Operational Amplifiers, with Experiments. Dr. Stanley Wolf is writing an
Applications Series Bugbook on the theory and uses of oscilloscopes. We expect
this series to grow rapidly as we identify authors who can fill in the needed
areas in electronics with experimental-based books along the style lines
characteristic of the Bugbooks.
We wish to again than those individuals who continue to back our educational
efforts. Mr. Murray Gallant and E&L Instruments, Inc. have supported the
development of the MMD-1 microcomputer by Jon Titus at Tychon, Inc. Mr. Bob
Veltri has provided us with excellent photographs of the hardware. Our wives
are no longer quite so patient. After hearing about the glories of microcom-
puters and reading about the "smart home," the now expect us to interface our
households. Manana.
UNIT NUMBER 16
WHAT IS INTERFACING?
INTRODUCTION
This unit introduces you to a few of the objectives of interfacing and provides
definitions for some of the concepts involved.
OBJECTIVES
ari) Distinguish between hardware and software, and give examples of each.
Ao Define controller.
“\o List five important control signal lines on the Dyna-Micro microcomputer.
In preceding units, we have provided you with information on basic digital electronics
that you will need as you interface an 8080-based microcomputer. We still have
more subjects to cover--three-state bussing, shift registers, arithmetic/logic
units, and buffers--but you already have been exposed to the logic operations, AND,
OR, NAND, NOR, and exclusive OR; the gating characteristics of the four basic
gates; decoders; latches and flip-flops; counters; monostable multivibrators;
input/output devices such as logic switches, pulsers, clocks, and displays;
digital codes; and the important terms, strobe, enable, disable, gate, and inhibit.
Before you jump into the subject of microcomputer interfacing, we believe that it
would be useful to provide you with some perspective on why you would want to
interface a microcomputer in the first place.
For those of you who have access to the McGraw-Hill publication, Bustness Week,
we would direct your attention to the July 5, 1976 issue and the article entitled,
"The Smart Machine Revolution: Providing Products with Brainpower." Some
excerpts from the article are as follows:
o '" 'This is the second industrial revolution,' says Sidney Webb, executive
vice-president of TRW Inc. ‘It multiplies man's brainpower with the same
force that the first industrial revolution multiplied man's muscle
power.'
~
A tidal wave of smart products such as these is on the way. They will
dramatically change the marketplace for consumer, commercial, and industrial
products. The computer-on-a-chip, powering the brains of smart products,
will spawn new industries and thousands of new companies. And in the process
it will wipe out some existing companies, and even some industries."
o "The key to the sudden surge in sales of microprocessors and to the wave
of new smart machines they will power is simply price. C. Lester Hogan,
vice-chairman of Fairchild Camera & Instrument Corp., demonstrated this
element dramatically at a Boston convention a few weeks ago. He pulled 18
microprocessors from his pocket and tossed them out to his audience. ‘That's
$18 million worth of computer power--or it was 20 years ago,' he said.
Hogan explained that his $20 microprocessor is as powerful as International
Business Machines' first commercial computer, which cost $1 million in the
early 1950s. 'The point I'm making,’ Hogan said, ‘is that computer power
today is essentially free.'
Even a year ago, those $20 microprocessors cost more than $100, and the
16-3
"The most exciting new products to come from the computer-on-a-chip will
be for the consumer. Microprocessors will go into homes, autos, appliances,
and other consumer goods in far greater numbers than into other products.
"Between 7 and 10 microprocessors will be in each home by 1980,' predicts
Andrew A. Perlowski, who heads microprocessor activities at Honeywell Inc.
His company is already hard at work on energy management and security systems
for the home."
Factory automation has moved slowly, partly because manufacturers did not
want an entire plant shut down because one bit one bit in a computer failed. 'The
advantage of the MPU is that it chops up the control job in smaller pieces,
and an individual MPU won't pull down a whole network if it fails,’ says
Sheldon G. Lloyd, engineering vice-president at Fisher Controls Co. 'The
microprocessor makes it economically possible to develop and build hier-
archical systems.'
"Many jobs now being done by microprocessors were too small to automate
before. Dow Chemical Co. is considering MPUs for a variety of jobs ‘where
computations are required that aren't quite complex enough to justify a
minicomputer,' says Charles R. Honea, process instrument manager at Dow's
Texas Div. For instance, Dow uses microprocessors to calculate the flow
of ethylene piped into the plant. The information was charged manually
and required half a dozen people. 'And it was always a day behind,' Honea
says. ‘You had no way of knowing how much ethylene you used today.'
"Software is not only the biggest problem now for the MPU users, but it
even
is also where most of the costs are.’ ‘Software costs are actually
Marley,
more for a microcomputer than for a minicomputer,' says Richard
a New Hampshire consultant who has designed smart products for several
small companies. He says that he spends up to $100,000 on every software
design, while the cost of hardware designs is down to around $20,000."
So far the biggest MPU effort is coming in digital test instruments, such
as voltmeters, counters, and frequency synthesizers, and in such analytical
instruments as spectrometers and chromatographs. ‘Probably 90% of digital
instruments selling for $2000 or more will use microprocessors by 1980,'
says industry analyst Galen W. Wampler."
o "Over the next several years, smart products and machines will spread at
an ever increasing rate. Software will be@ome available so that anyone
will be able to program a microcomputer. Schools will be turning out a
flood of young people familiar with microprocessors and eager to build
products with them. The semiconductor industry will continue to develop
more powerful parts. ‘In the next 5 to 10 years we will be able to turn
out 1 million devices on a single chip,’ predicts Richard L. Petritz,
vice-president of New Business Resources, a venture capital company. This
will mean that the power either of a large mainframe computer or of a
complete minicomputer with large amounts of memory will be available on
a single chip." .
o "Development time is so short for a smart product now and the entry costs
are so low that there will be ‘myriad examples of new companies spawning,
with bright, young fellows developing MPU-based products,’ says Fairchild's
Hogan. Petritz says: 'The MPU will reduce the application of electronics
essentially to that of writing a computer program, and the average person
can be educated to program a computer.'
MICROPROCESSOR VS MICROCOMPUTER
We have had difficulty in finding a good definition for the term, digttal computer.
In looking around for such a definition, we found an excellent pair of paragraphs
by Donald Eadie in his book, "Introduction to the Basic Computer," that provide
some insight into what is meant by the term, processor. Thus:
At the moment, the microprocessor does not quite have such a definition. As semi-
conductor manufacturers develop the capability to manufacture an entire computer
on a single chip, including memory and I/0 ports, we believe that the term, micro-
processor, will assume the meaning given above.
"This lesson begins with the word 'microprocessor.' To some people micro-
processor means microcomputer. To cther people the words microprocessor
and microcomputer are different. To them, 'microprocessor' is a broader
and more generic term which describes an extremely small electronic system
capable of per ree specific tasks. Thus, microcomputer is an application
of microprocessors." 6
While on this subject, we would also like to quote from the article by Laurence
Altman in the April 18, 1974 issue of Electrontes:
As an example of what is coming in the near future, we would like to quote from
an announcement in the June, 1976 issue of Digital Design:
x
There is more to the announcement, but the point that we wish to make is that
this single chip is much closer to a true computer-on-a-chitp than most microprocessor
chips that are currently on the market. The 8080A microprocessor chip discussed
in this Bugbook is still a microprocessor; it contains no built-in read/write
memory, ROM, or I/O capability.
HARDNARE YS SOFTWARE
Hardware and software are important terms that will be used repeatedly in this
unit. It is appropriate, therefore, to define them early:
The Dyna-Micro microcomputer, along with any integrated circuit chips, wire,
breadboarding aids, and peripheral devices, are all considered to be the hardware.
The programs and subroutines that you use and write are the software. In time,
you will observe that it requires considerable effort to write good programs that
take maximum advantage of available memory, the instruction set, and the time that
is required to execute individual instructions.
WHAT IS A CONTROLLER?
The question of cost becomes an important factor when one considers the use of
computers as controllers. One would not control 100 devices, each with a value
of $500, with a $1,000,000 computer; the use of such a large computer to control
$50,000 worth of equipment is a form of overkill. On the other hand, such a computer
would be useful in the control of a $20,000,000 chemical plant. However, with
today's technology, it is doubtful that a million dollar computer would be required;
probably $200,000 would buy a very large minicomputer system that would serve the
requirements of the plant. One can justify the cost of a computer/controller if
16-8
The Business Week article that we excerpted earlier in this unit should provide
you with some perspective concerning the potential applications for microcomputers.
We would like to discuss this subject in further detail with the aid of Figure
16-1 and Table 16-1.
APPLICATIONS
COMPUTER
MICRO
Figure 16-1. Schematic diagram that depicts applications that are foreseen for
microcomputers, which will carve out their own niche between discrete
logic and inexpensive minicomputers.
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At the higher end of the computer spectrum, micrecomputers are not currently being
used to replace large number-crunching computers of the PDP 10, IBM 360, and |
IBM 370 class. However, one California company has proposed the use of 256 8080A
microcomputers arranged in the form of a "hypercube."' According to them, such a
computer would rival or exceed large computers in number-crunching capability.
It is quite possible that future computer generations will take advantage of |
distributed computer architecture. Again, the problem is software development.
Table 16-1 depicts the spectrum of computer equipment complexity, from simple
hard-wired logic systems to high-performance data processing equipment. Costs
are declining across the board. Every five years, the cost for an equivalent amount)
of computing capability decreases approximately ten-fold.
COMPUTER HIERARCHIES
Rev. 9/22/77
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MEMORY 10
CPU ry
MODULE
—— CONTROLBUS |
I/O device Input/output device. A card reader, magnetic tape unit, printer,
or similar device that transmits data to or receives data from
a computer or secondary storage device. In a more general
sense, any digital device, including a single integrated circuit
chip, that transmits data to or receives data or strobe pulses
from a computer.
central proces- A single integrated circuit chip that performs data transfer,
sing untt control, input-output, arithmetic, and logical operations by
(mlteroprocessor) executing instructions obtained from memory.
memory Any device that can store logic 0 and logic 1 bits in such a
manner that a single bit or group of bits can be accessed
and retrieved.
A typical microcomputer constructed from an 8080A chip possesses all of the mini-
mum requirements for a digital computer:
Op lteis diistital.
ADDRESS BUS
The Intel 8080A microprocessor chip contains a 16-bit address bus that is used for
the identification of specific memory locations or specific I/0 devices. It is
a unidirectional bus, which means that address information can only be output from
the 8080A chip. When addressing memory, 216 = 65,536 different memory locations
can be accessed. We say that the 880A is a "64K" device, where the "K" is an
abbreviation for kilobyte, or 1024 bytes.
16-14
The Intel 8080A address bus is also used to supply the 8-bit device code for
input and output devices. When addressing input-output devices, the address bus
bus assumes a new identity, i.e., it is subdivided into two identical 8-bit device
code bytes, either of which yoy can use when wiring an interface circuit to 1/0
devices. When addressing I/0 devices using the IN or OUT microcomputer instructions,
you can address 2° = 256 different input devices and 2® = 256 different output
devices.
Whenever you encounter the term, bus, you should be alert for the possibility that
different types of information appear on the bus lines at different times. In the
case of the 8080A address bus, this is certainly true. Most of the time, the
information that appears on the address bus is the address of a specific memory
location. Occasionally, the information that appears on the address bus is a device
code. The microcomputer knows when the bus is being used to access memory and when
it is being used to identify I/0 devices: tt provides the appropriate control pulse
that informs you what it ts doing! We shall discuss these control pulses in a
section below.
The Intel 8080A microprocessor chip contains an 8-bit bidirectional data bus that
permits eight bits of data, known as a byte, to be transferred between the 8080A
chip and memory or I/0 devices. Different types of fhformation appear on the data
bus lines at different times. Much of the time, the data that appears is an
instruction byte from memory. At other times, the data that appears on the data
bus is one of the following:
o Control status bits used to derive some of the control bus signals.
How do you know when these different types of data transfers are occurring? The
microcomputer tells you, by providing the appropriate control or status pulses that
inform you of the type of activity in current progress. It should be clear now
that an understanding of the control bus is essential to the understanding of the
behavior of the 8080A microcomputer. Such a statement is true for any type of
digital computer that you encounter.
CONTROL BUS
Although called a control bus, the set of signals in question do not actually
16-15
comprise a bus since different types of information do not appear on the individual
signal lines at different times. Each signal line is uni-directional and uni-
functional. With this caveat, we shall continue to call the set of control signals
associated with the 8080A chip a control bus; the term is too widely used in the
microcomputer literature for us to suggest any reasonable alternative.
The five basic types of activities in which the 8080A microprocessor chip engages
are the following: ‘
. Memory Read
- Memory Write
I/O Read
. I/O Write
FR Interrupt/Interrupt
WAPwWN Acknowledge
wrt te To transmit data from some other digital device into a specific
memory location. A synonym for store.
Five separate control signal lines are provided, one for each of the above
activities. These lines have the following abbreviations:
isi:
The pulse width depends on the speed of the 8080A-based microcomputer; for the
Dyna-Micro microcomputer, which is clocked at 750 kHZ, the pulse width is 1.333
us.
aid of the
The uniqueness of each of the control signals can be seen with the
truth table given on the following page. These control signals are available
on the SK-10 bus socket on the Dyna-Micro printed circuit board (Figure 16-3).
You will use them, speciallyIN and OUT, to gate the transfer of data between
digital integrated circuit chips(wired on the breadboard)
and the CPU of the
8080A-based microcomputer.
16-16
MEMR MEMW IN OUT IACK Operation
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The above defintions have been obtained from reference 2. We can thus define
computer interfacing as
Although the details of computer interfacing vary with the type of computer
employed, the general principles of interfacing apply to a wide variety of
computers. For the 8080A microcomputer, the basic objectives of interfacing are
summarized in Figure 16-4. If you desire to interface the microcomputer, your
object is to:
interrupt signal
from input or
output devices.
OUTPUT
INPUT MICRO- 8 bits data
8 bits data DEVICE
DEVICE COMPUTER
Figure 16-4. The four principle tasks of interfacing: .input, output, device select
pulse generation, and interrupt servicing. Hs
A better way of viewing three of the four tasks of interfacing, is given in the
diagram below:
DL SADDRESSIBUST _ mau)
CPU
MODULE
CONTROL BUS _
The transfer of 8 bits of data between the CPU and an I/0 device occurs over the
8-bit bidirectional data bus. The specific I/0 device that is involved in the
16-19
data transfer is selected via the use of 8 bits on-the address bus. The precise
timing of the data transfer is determined by the presence of an IN or OUT pulse
on the control bus. Therefore, during the transfer of data between the CPU and
an I/O device, all three busses participate!
There is much more to say about computer interfacing, but we will save it for
subsequent units.
We have indicated previously that you must synchronize the transfer of data between
a computer and an 1/0 device, and that this synchronization is accomplished with
the aid of pulses called device select pulses. An important point is that
several device select pulses may be required for a single I/O device. For
example, the 74198 shift register has a pair of control inputs that determine
whether the register shifts left, shifts right, or parallel loads eight bits of
data. The chip also contains clock and clear inputs. Thus, a single 74198 chip
may require three or four unique device select pulses. The fact that you can
generate 256 different input device select pulses and 256 different output device
select pulses does not mean that you can address 512 different "devices."' A
more reasonable number is of the order of 50 to 100 devices. Rarely will you
require so many device select pulses. If you do, there are other tricks that you
can use to generate still more such pulses.
In the following Unit, you will learn how to generate device select pulses.
also provided is a discussion of the various uses for device select pulses.
16-20
REVIEW
The following questions will shelp you review a few of the important concepts of
microcomputer interfacing.
a. cross-assembler
b. editor
d. wire
g. FORTRAN program
ANSWERS
= software
software
hardware
hardware
hardware
hardware
software
. hardware, whatever it is
Boo hardware
moana
2. The bidirectional data bus, the control bus, and the address bus
~ INTRODUCTION
This unit will teach you how to generate input and output device select pulses,
which are the microcomputer-generated synchronizing signals between the micro-
computer and external 1/0 devices, which could be simple integrated circuit
chips. The most useful circuit is one that is based upon the 74154 decoder chip;
sixteen different device select pulses can be generated.
OBJECTIVES
Yo Give one or two schematic diagrams of circuits that can be used to generate
device select pulses.
fo list how many machine cycles exist for some typical 8080A instructions.
iN 9 Wire a circuit that will permit you to single step the Dyna-Micro microcomputer.
Le2
Device select pulses are easy to generate and are inexpensive. In a typical
application, a 74L154 decoder chip is used. At a cost of $1.25 per chip, 2t
will cost you approximately 8¢ for each device select pulse that you generate,
in quantities of sixteen.
It is easy to write a program that generates a single device select pulse, such
as the negative pulse, OUT 0, shown below,
For the MMD-1 microcomputer, the pulse width is 1.333 us. Ina subsequent
unit, you will learn how to write various types of time delay loops that
repeatedly execute a small group of microcomputer instructions. By writing such
a program, you will be able to generate a series of device select pulses,
as shown for OUT 1,
OUT 1
TH } timing loop
OouT | —————~-
JMP
With a pair of device select pulses and a single preset-clear flip-flop such as the
7474, you can write a time delay loop program that generates a single clock pulse
at the output of the latch,
OUT 2
OUT 2
SI 1 @ }timing loop
U OUT2
Um OUT-S OUT 3
OUT 3
By adding a second time delay loop to your program, you can generate a series
of clock pulse with a known duty cycle that is specified by the program,
OuUT4 OUT 4
5 } timing loop
OUT 5
j \ timing loop
OUT 5 JMP
these last two circuits, you have substituted software for either a
With
timer wired
monostable multivibrator or an astable mulitivibrator such as the 555 IC
You have already used a number of different Outboards, such as
as an oscillator.
the pulser Outboard and the clock Qutboard. With your ability to substitute
7474
software for hardware, you are now able to replace such Outboards with a
(which contains two flip-flops) and appropriate programs in the microcomputer.
chip
A much more efficient interface circuit is based around an 8-bit latch and single
device select pulse,
07
OUT 7 °
With device select pulse OUT 007 and an 8212, it is possible to latch all eight bits
the bidirectional data bus and use such bits as individual control lines at various
points in a digital circuit. In the next unit, you will learn how to wire such
a latch circuit. ay
You will not be able to substitute software for certain types of chips, such as
latches and three-state buffers. Nevertheless, as long as speed is not your
requirement, you can use software to substitute for most of the important functions
of MSI and many LSI integrated circuit chips. This point is made quite well with
the PACE microcomputer in the manual, "Logic Designers Guide to Programmed
Equivalents to TTL Functions," which is available from National Semiconductor
Corporation for $5.00. All the PACE programs can be converted to operation on
an 8-bit microcomputer such as the 8080A or Motorola 6800. The hardware for which
they have provided equivalent microcomputer software include the following:
They have also provided software equivalents for the following types of digital
systems, each of which consists of a number of 7400-series integrated circuit
chips:
You are already familiar with a number of integrated circuit chips in the MSI
category. Some of them require strobing or enabling in order to perform their
digital function. Thus:
7490 decade counter: Logic 1 at pins 2 and 3 clears counter
Logic 1 at pins 6 and 7 sets counter to 9
Clock input is at pin 14
»
In microcomputer systems, the 7442 and 74154 decoders are used to help in the
generation of device select pulses. However, they can also be used as general
decoders that are enabled by such pulses.
To generate a device select pulse, you require two types of information from the
8080A microcomputer:
1. The 8-bit identification code, called a device. code, of the 1/0 device.
The origin of both types of information is in software, zi.e., the IN and OUT
instructions that you encountered in the early modules in this*Bugbook. These
instructions include the 8-bit device code and cause the microcomputer to generate
the appropriate IN or OUT synchronization pulse. The location of the IN and OUT
instructions in the program determine the specific instant when the
device select pulses are generated.
In other words, during the generation of a device select pulse, both the address
bus and the control bus are active. As shown in Figure 17-1, the 8-bit device
code is obtained from the 16-bit address bus, and the two synchronization pulses,
IN and OUT, from the control bus. In the 8080A microcomputer, the 16-bit address
bus is subdivided into two 8-bit device codes. For the Intel 8080A chip, both codes
are identical during the execution of the third IN or OUT machine cycle.
What do you do with the 8-bit address bus and synchronization pulses? You might wire
them to a 74154 4-line-to-16-line decoder, as shown in Figure 17-2. With a
single 74154 decoder, you use only four of the eight address bus bits and either
IN or OUT. A more ambitious device select pulse decoding circuit is shown in
Figure 17-3. All eight address bits are used, and seventeen 74154 decoders
provide you with the opportunity to generate 256 unique pulses. To generate
all 512 input and output device select pulses, two circuits of the type shown in |
Figure 17-3 would be required. This is rarely done in actual interfacing applications
MEMORY
address
bus 8-bit address for
memory
16-bit
external input / output
devices.
Figure 17-1. To generate a group of device select pulses, you require eight
bits from the address bus and two synchronization pulses, IN and OUT,
from the control bus.
+5V GND
Memory e
address
bits Na
A-O
Sixteen different
SN74154 device select pulses.
alii:
iN or OUT
Figure
a
17-2. / To generate sixteen different device select pulses, you need
\fouy/ bits from the address bus and either the IN or OUT synchronization
pulse, for input and output devices, respectiyely.
‘ =
G2
Ae? 7
ae 22
a-4—=
SN 74154 No. O
Figure 1/-3. Circuit for generating 256 different device select pulses.
It is not likely that you will need to generate 512 different device select pulses.
A more limited decoding circuit that is based upon Figures 17-2 and 17-3 is
shown in Figure 17-4 below:
+5V GND
iN
or
Device select
OUT pulse 004,
ae LAMP
A-| MONITORS
A-O
+5V GND
Figure 17-4. One possible decoding circuit for generating sixteen absolute
decoded device select pulses.
The circuit includes an absolute decoding of the complete 8-bit device select
address byte, i.e., all eight bits, not just four. This is not a widely used
circuit and is mentioned for illustration only. It may be more useful to use
one of the 74154 chips for input device select pulses, and the other one for
output pulses.
The preceding circuits are ones that we use to generate device select pulses.
However, there exist altermative schemes to decode the address and control
buses, and we would like to them. In Figure 17-5, we use a pair
illustrate
of 74154 decoders, and thus decode the 8-bit address bus byte.
absolutely
Each device select pulse that we generate requires a separate 7402 (or 7432)
gate, as shown in Figure 17-6. This circuit is useful only if the device
select pulses in your system are scattered randomly in the range, 000 to
3778 and all functions are centrally located. Only two 74154 decoder chips
and four 7402 2-input NOR gate chips--which contain a total of
17-10
IN
Or Device
OU select
pulse
Figure 17-5. Absolute decoding scheme for device select pulses that requires a
7402 or 7432 gate for each device select pulse desired.
+5V GND 17-11
no connection
IN
or
OUT LAMP
MONITORS
A-2
A-|
+5V GND
17-6. Circuit that demonstrates how 2-input NOR gates are employed to
Figure
generate individual device select pulses.
select pulses.
sixteen NOR gates--are required to obtain sixteen different device
If the device codes are sequential, then this circuit is not preferred.
A related decoding technique is shown in Figure 17-7. Rather than connect the
IN or OUT control signals to a decoder, instead you connect them to individual
7402 (or 7432) gates. Such a decoding scheme is used in the Dyna-Micro micro-
17-7). Four address bus bits are connected to a 74L42 decoder, the
computer (Figure
gates to provide
output channels of which are then gated with 7402 2-input NOR
the microcomputer board.
the necessary device select pulses for the 7475 latches on
A7 are wired to 74LS05
Note in Figure 17-7 that address bus bits A3 through
and then tied to the
inverters, the outputs of which are all connected together
iN>—
D input of the 74L42 decoder. The D input must always be at logic 0 if device
select pulses are to be generated. The technique employed here is the open
collector bussing technique of tieing the outputs of special open collector
integrated circuit chips to a common bus line. We have essentially constructed
a five-input OR gate, which enables the 74L42 decoder. We shall discuss this later.
It is also possible to decode 8-bit device code bytes using gates and comparators.
This is particularly useful in real situations where only a few device select
pulses are needed. For example, consider the circuit shown in Figure 17-8. On
the left, two distinct device select pulses are generated with the aid of a pair
of 7430 8-input NAND gate chips. The device code for the top 7430 gate is
11000110,, or 306 in octal code, whereas the device code for the bottom gate is
11001111,, or 317 in octal code. The unique output state from the 7430 NAND gate
is logic 0, which occurs only when the proper device code has been applied to the
gate. If the OUT control signal is also at logic 0, the unique output from the
7432 2-input OR gate, i.e., logic 0, either clears or presets the 7476 flip-flop.
The circuit of Figure 17-8 demonstrates how you can use device select pulses to
control AC power. Optically-isolated solid state relays permit you to use digital
signals to turn on and off AC loads operating at either 115 Volts or even 220 Volts.
Relays can be obtained that will switch 10 amperes at these voltage levels, and they
cost only $15 in quantities of one. This subject has been discussed in greater
detail in Bugbook III, Unit Number 5.
Note that the device codes correspond to the 8-bit ASCII codes for the characters
"RF" and "O" , in which the parity bit is at logic l.
*sas—nd joeTes sdTAap jndjno omy
7-18
apooep ATeqntTosqe oj soqe8 GNVN Jndut-g O¢ys Fo ated e shoTdwe Jey, ZIMoATO AeToeA 97eIS PTTOS "S-/T ean8Ty
ind #40 UD} =O
cons Ofbl
19
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. SoS]
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17-14
of 7485 comparator chips, the pin
A final decoding circuit consists of a pair
configuration and truth table for which are given below:
"185 20 mw 90 ns 1
'S85 365 mW 11 ns Tea
Bara Sena SBNARSS(ALA BARES)
63 A BA-BA B.A B A*BA_ 8B, GND
(EUS,
82
INPUTS
RENE SEOAz
RECA
CASCADING INPUTS ANE
a-8 A’B AvB A-B al GND
description
These four-bit magnitude comparators perform comparison of straight binary and straight BCD (8-4-2-1) codes. Three
fully decoded decisions about iwo 4-bit and are externally available at three outputs. These
words (A, B) are made
by
devices are fully expandable to any number of bits without external gates. Words of greater length may be compared
connecting comparators in cascade. The A > B, A <B, and A = B outputs of a stage handling less-significant bits are
bits. The
connected to the corresponding A > B, A <B, and A = B inputs of the next stage handling more-significant
for the
stage handling the least-significant bits must have a high-level voltage applied to the A = B input and additionally
voltages applied to the A > B and A < B inputs. The cascading paths OF the ’85 and ‘S85 are implement-
‘L85, low-level
ed with only a two-gate-level delay to reduce overall comparison times for long words.
FUNCTION TABLES
COMPARING CASCADING
INPUTS INPUTS OES
85, ‘S85
A3=B3 |A2=B2 |A1=81 | AO=B0 x x H te 1's H
A3
= B3 | A2= B82 | A1l= 81 | AO= BO (" L L H L
185
A3-63 ]A2=82]A1-81 |A0-B0| L rm Hq rE H H
a3-83 |A2=82]A1-81|A0-80| H h H H L H
A3-B3 |A2-82]A1-81|A0-80| H H H H H H
a3-B3 |A2=82|A1=81|A0-80] H H i H H L TEXAS INSTRUM ENTS
a3-83|A2-82|a1-81{ao-eo] Lt tL | et et oL Bone anrice Gow soi e WALucedrerasioeats
H = high level, L = low level, X = irrelevant
We are providing information for both the high-power (7485, 74885) and low-power
(74L85) chips since they have different pin configurations and truth tables. You
may wish to minimize fan-in through the use of the 74L85 chip.
As can be seen in Figure 17-9, the only condition that you use ts A= B. If
the address bus byte A is equal to the byte B that you set at the B inputs to the 74
you will obtain a logic 1 at the A = B output from the 7485 chip at the top right.
You invert this signal and then gate it with the OUT control signal to obtain
desired device select pulse.
VAS
+5V GND
+5V GND
Figure 17-9. Decoding circuit using a pair of 7485 4-bit comparator chips.
This circuit produces an absolutely decode single device select
pulse. However, you can change the device code simply by altering
the 8-bit B input to the comparators. In this case, the B input
corresponds to 11000110, or 306 in octal code.
1/0 INSTRUCTIONS
325 <B2> OUT Place the 8-bit device code on the address bus, the accumulator
contents on the bidirectional data bus, and generate an OUT ccntrol
signal. The contents of the accumulator remain unchanged.
555m E2 EN Place the 8-bit device code on the address bus, permit data on
the bidirectional data bus to be input into the accumulator, and
generate an IN control signal.
The second byte of each instruction is the 8-bit device code. You use the control
signal and the information on the address bus to generate the required device select
pulse. A more succinct way of stating the two above instructions is:
555 <B2> IN Input into the accumulator the contents of the input device
selected by the device code in the second byte.
17-16
Although device select pulses are frequently used to transfer information between
the accumulator and an I/0 device, they also are used to strobe the operation of
I/O devices under conditions where data transfer to or from the accumulator does
not occur. . ‘
Having described several circuits that you can use to generate device select
pulses, we will shortly provide you with several programming examples that
illustrate the behavior of the IN and OUT instructions, both of which are two-byte
instructions. If you execute either the IN or OUT instruction in the single-step
mode and monitor the contents of the 8-bit data bus, you will observe something unusu
a third byte appears that does not correspond to a byte present at that point in yo
program. What is this extra byte? It is the 8-bit byte being transferred to or
from the 8080A's accumulator register during an IN or OUT instruction cycle. It is
during the execution of this third machine cycle that:
When you single step through an 8080A microcomputer program, you single step through
machine cycles rather than instruction bytes. Without going into great detail,
we can define machine cycle as follows:
As an example of a machine cycle, there is the FETCH machine cycle, during which
the instruction code is fetched from the memory location addressed by the program
counter. Simple arithmetic and logical operations involving the 8080A's internal
registers are also performed during the FETCH cycle.
The output instruction, OUT, consists of two FETCH machine cycles in sequence,
t.e.,the instruction code and then the device code, followed by an OUTPUT machine
eyele--the third step that you observe when you execute an OUT instruction--during
which the contents of the accumulator are made available on the bidirectional
data bus. The output device code appears as two identical 8-bit device code bytes
on the address bus and an OUT pulse is generated. The IN instruction consists of
two FETCH machine cycles in sequence,i.e.,the instruction code and then the device
code, followed by an INPUT machine cycle--the third step that you observe when you
execute an IN instruction--during which the input buffer/latch within the 8080A
chip is enabled to permit input data on the bidirectional data bus to be transfer-
red to the accumulator. Two identical 8-bit device code bytes appear on the address
bus, and an IN pulse is generated.
AVAVE
FIRST PROGRAM
Let us first consider the program given in Experiment No. 5 in Unit Number 11:
LO memory Instruction
address byte Mnemonic Description
If you would execute this program using the single-step circuit, you would observe
the following bytes, in succession, on the bidirectional data bus:
002 002 FETCH machine cycle for device code for port 2.
You observe such information on the data bus because (a) all instruction bytes
move over the data bus from the memory to the instruction register within the
8080A chip, and (b) the contents of the accumulator is output on the data bus
during the third machine cycle of the OUT instruction.
The program increments the contents of the accumulator during each loop. Also,
contents to port 2 during each pass through the loop. You
it outputs that
observe this at an 8-bit port that increments from 00000000, to 111111115 and
then repeats the counting sequence.
* NOTE: This is the I/0 device address that appears at bits AO through A7 on
the address bus.
1/-18
SECOND PROGRAM
»
In the second program, given below, you actually modify the device code in the
OUT instruction. In this program, you encounter for the first time the use of
a register patr instruction, LXI H; the use of register pair H to define the
16-bit address of a memory location M; and the use of a memory reference instruction,
INR M. From this point forward, if you encounter an unfamiliar instruction, please
refer to the instruction set summary provided in Unit Number 18.
LO memory Instruction
address byte Mnemonic Description
This program permits you to output the accumulator contents to 256 different
devices in sequence, starting with the device given at HI = 003 and LO = 316.
On every loop of the program, the device code at LO = 316 is incremented by one.
This is not a very useful program, but it does demonstrate the fact that the
device code is not inviolate within a program. With very few instructions,
you can alter the device code and thus sequence through a series of devices.
In practice, the device code of the output device of interest would probably
be stored in a register, and a MOV instruction used to transfer the register
contents to memory location M addressed by the register pair H.
Would you obtain a useful result if this program were in ROM, PROM, or EPROM?
No, because then you would not be able to alter the contents of memory location
LO = 316.
Rev. 9/22/77
7-19
The following experiments demonstrate how you can generate, and use, device
select pulses. You will also wire a bus monitor and gain experience with the
use of a single-step circuit.
4 You count IN‘and OUT strobe pulses with the aid of a 7490 counter
while the microcomputer is operating in the single-step mode.
You also determine the bit pattern for the keyboard.
PURPOSE
The purpose of this experiment is to wire a‘ bus monitor, a three-digit octal
display that monitors the data that appears on the bidirectional data bus.
0.400, py
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PINS OMITTED
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PIN 12 LATCH DATA INPUT D
PIN 13 LATCH DATA INPUT C
PIN 14 LOGIC SUPPLY VOLTAGE, Vcc
TIL3II
STROBE
step 1
Wire the circuit shown or use a LR-27 bus monitor Outboard. When you wire the
above circuit, as with any interface cireutt tn thts Bugbook, do so with the
power to the microcomputer turned off!
STEP 2
Connect the latch STROBE input to logic 0. This enables the displays so that
17-2)
each numeric indicator display follows the inputs.
Apply power to the MMD-1l microcomputer. You should observe that most of the
dots in the numeric indicators are lit. What you are observing is the wait
loop in the Keyboard EXecutive EPROM being executed at a clock rate of 750 kHz.
The only thing that you can learn from the fact that all of the numeric indi-
cator dots are lit is that the microcomputer is executing a program.
STEP 3
Now. connect the STROBE input to the OUT control signal line on the SK-10 bus
socket. If you cannot find OUT, please refer to Figure 16-3.
STEP 4
Press the RESET key on the MMD-1 microcomputer. What three-octal-digit byte
appears on the bus monitor? Write it in the space below.
> O |
<7
Yes.
STEP 5
What is the significance of the information that appears on the bus monitor
when the STB input is connected to OUT? If you are not certain how to answer
this question, load some arbitrary octal values into read/write memory and
observe what information appears on the bus monitor. Also examine your "program!
and again observe the relationship between the byte on the bus monitor and the
byte displayed at Port 2. What do you conclude?
We conclude that the information on the bus monitor (an output port for the
microcomputer) and at Port 2 are identical. The two output ports give the
contents of the memory location addressed by the 16-bit address given in
Ports 0 and 1, or the byte to be loaded into memory, the LO address register, or the
HI register. The bus monitor makes it easier to enter and check a program.
Save this circuit for all of the remaining experiments in this Bugbook.
Experiment No. 2 ts similar to this one, but employs a different numeric
indteator, the HP 5082-7300.
APPENDIX TO EXPERIMENT NO. lL
A less expensive bus monitor circuit can be constructed from Port 1 on the
MMD-1 microcomputer. Rather than three octal digits, the monitor consists of
eight LEDs that continuously monitor the state of the bidirectional data bus,
DO through D7. To construct this bus monitor, place.a switch in the ENABLE
input line to the Port 1 7475 latch chips, as shown below,
When the switch is closed, 7475 chips 1C24 and IC25 operate normally as Port 1.
When the switch is opened, they operate as an 8-bit bus monitor.
EXPERIMENT NO. 2
PURPOSE
The purpose of this experiment is to wire a bus monttor using the HP 5082-7300
numeric indicator. This experiment is identical to Expermiment No. 1.
HP 5082-7300
STROBE (STB)
step 1
Wire the circuit shown. We recommend that you do so with the power to the
microcomputer turned-off.
STEP 2
Connect the latch STROBE input to logic 0. This enables the displays so that
7-2
each numeric indicator display follows the inputs.
Apply power to the MMD-1 microcomputer. You should observe that most of the dots
in the numeric indicators ar® lit. What you,are observing is the wait loop in
the Keyboard EXecutive EPROM being executed at a clock rate of 7/50) kize the
only thing that ; you can learn from the fact that all of the numeric indicator dots
are lit is that the microcomputer is executing a program.
STEP 3
Now connect the STROBE input_to the OUT control signal line on the SK-10 bus
socket. If you cannot find OUT, please refer to Figure 16-3.
STEP 4
Press the RESET key on the MMD-1 microcomputer. What three-octal-digit byte
appears on the bus monitor? Write it in the space below.
x
Yes.
STEP 5 ait
What is the significance of the information that appears on the bus monitor
when the STB input is connected to OUT? if you are not certain how to answer
this question, load some arbitrary octal values into read/write memory and
observe what information appears on the bus monitor. Also examine your "program"
and again observe the relationship between the byte on the bus monitor and the
byte displayed at Port 2. What do you conclude?
Save either this ctreutt or the ctreutt in Experiment No. 1 for all of the
remaining experiments in thts Bugbook.
Rev. 9/22/77
7-25
EXPERIMENT NO. 3
PURPOSE
The purpose of this experiment is to construct a single-step circuit for the
Dyna-Micro microcomputer.
7474
O= Full speed
|= Single step
READY
(On SK-IO
socket)
CLOCK
or
PULSER
WAIT
step 1
Wire the circuit shown. Use the READY and WAIT locations on the SK-10
breadboarding socket. Note in the above diagram that the chips to the right of
the dotted line are already wired on the printed circuit board as shown.
The specific SK-10 bus socket connections that you must make are shown below:
ATP
7474
(pin |)
ty
STEP 2
Connect the latch enable input (STB) of the bus monitor to logic 0 (GND). This
permits you to observe all information that appears on the bidirectional data
bus. Place the single-step circuit in the single~step mode (pin 4 of the 7474
chip connected to logic 1). If you are using the single-step Outboard, set the
logic switch to the position that corresponds to single-step operation.
Press the RESET key. You should observe a 4()3 on the bus monitor. This ts the
first instructton byte in the KEX software routine. x
STEP 3 .
?
Using the pulser, single step through the keyboard executive (KEX), which starts
at memory location HI = 000 and LO = 000. Compare your observations with the
sequence of bytes that we observed on the bus monitor, as given below. The
purpose of this listing is th show you how the single step operation works. You
may not understand every instruction below.
Memory Instruction
address byte Mnemonic Description
000 070 061 LXI SP Load immediate two bytes into the stack
pointer register
000 073 O41 LXI H Load immediate two bytes into register
pair H
003 000 XYZ XYZ MEMORY READ machtne cycle, in which the
contents of memory Location HI = 003 and
LO = 000 are moved to regtster C. You
observe this memory byte on the bus
monttor. Your XYZ value ts the value
contained in the first read/write memory
location on your MMD-1 microcomputer.
001 001 008 003 OUTPUT machine cycle, during whitch the
contents of the accumulator are output to
port 1. The device code ts output as two
tdentical 001 bytes on the address bus for
the Intel 8080A chip.
000 000 000 000 OUTPUT machtne cycle, during which the
eontents of the accumulator are output to
port 0. The device code ts output as two
identical 000 bytes on the address bus.
000 105 vat MOV A,C Move contents of register C to the accumulator
0038 377 000 STACK WRITE machine cycle, during which the
HI address byte in the program counter ts
moved to the stack tn memory
008 376 1138 STACK WRITE machine cycle, during which the
LO address byte in the program counter ts
moved to the stack tn memory
000 000 160 160 INPUT machine cycle, during which a byte
ts input fromthe keyboard. The byte,
160, is input tf you do not press any key.
The device code is output as two identical
000 bytes on the address bus.
Rev. 9/22/77
We will stop here as we enter the time delay subroutine. Clearly, the value of
the single-step and bus monitor circuits is that they permit you to observe data
being transferred between memory or I/O devices and the interior of the 8080A
microprocessor chip, t.@., you are able to observe machine cycles other than the
FETCH cycle. This is particularly important when you check and test new programs.
STEP 4
Return the microcomputer to its full operating speed, 750 kHz.
Now load 377 into the HI register (port 1), the LO register (port 0), and the
data register (port 2). All twenty-four lamp monitors should now be lit.
Place the single-step circuit (or Outboard) in the STEP position, press the RESET
button on the microcomputer keyboard, and single-step through the KEX program.
When does the HI register change from Sin to 003? You will have to single step the
program at least to the first OUT instruction. Why?
At the machine cycle that immediately follows the execution of the instruction
byte at HI = 000 and LO = 101. The only time that this data is changed is
during the execution of an OUT 001 instruction. These LEDs are not connected to
the address bus. The are only used to represent the HI address byte.
sTeP 5
Continue to single step through KEX. When does the LO register change from 3/7
to 000?
At the machine cycle that immediately follows the execution of the instruction
byte at HI = 000 and LO = 104. The only time that this data is changed is during
the execution of an OUT 000 instruction.
STEP 6
Continue to single step through KEX. When does the data register change from 3/7
to whatever is stored at memory location HI = 003 and LO = 000?
At the machine cycle that immediately follows the execution of the instruction
byte at LO = 107. The only time that this data is changed is during the
execution of an OUT 002 instruction.
Save your bus monitor and single-step etreuits and continue to the next experiment.
Rev. 9/22/77
20
EXPERIMENT NO. 4
PURPOSE .
pulses, IN and
The purposeof this experiment is to count input and output strobe
QUT. You will first count OUT strobe pulses, then you will change the clock input
to the 7490 chip to the IN signal and count IN strobe pulses.
+5V GND)
MONITORS
PROGRAM
LO Address Instruction
byte byte Mnemonic Description
Rev. 9/22/77
003 000 000 Device code for port 0
STEP 1
This program is an interesting one, since it demonstrates a number of important
concepts associated with input and output instructions and the
operation of the MMD-1 microcomputer.
STEP 2
Before you wire the 7490 circuit, load the above program into memory and execute
it at 750 kHz. What bit pattern do you observe at port 0?
STEP 3
Now press the following keys in sequence: 0, 1, 2, 3, 4, 5, 6, and 7. Write the
bit pattern that you observe at port 0 in the space below for each of these keys.
What correlations do you observe between the key numbers and the bit pattern?
11110000
11110001
11110010
11110011
11110100
11110101
11110110
11110111
NDOALPWNERO
32
Note that whenever you press a key, bit D7 becomes logic 1. For keys 0 through
7, the least significant three bits correspond to the octal equivalent of the
key. »
;
step 4
Press the remaining keys with the exception of RESET. Write the bit pattern that
you observe in the space below.
11111000
11111010
11111011
11111100
11111101
aaDRIES(0)
aval
(ae)
Cpu
28
t=
[asl
Bee
jest Ta
Again, whenever we pressed a key, bit D7 became logics1. This is the bit that
is used by KEX to determine whether or not a key is pressed. Refer to Experiment
No. 2 in this unit and the instruction at LO = 320. This is where KEX detects a
key closure. x
STEP 5
Wire the counter circuit and connect the OUT output to the counter. With the
microcomputer executing the program at the full clock rate, switch the logic
switch (or wire) connected to the 7474's pin 4 input to the logic 1 state. The
microcomputer is now in the single-step mode.
STEP 6
If you do not have a bus monitor, all that you will be able to do in this
epxeriment is to count the OUT control signal pulses. Single step through the
program and observe that you obtain a single count for every nine times that
the single-step pulser is pressed in and out. If the use of the pulser becomes
tedious, substitute a clock Outboard that is operating at a frequency of
approximately 0.3 to 1 Hz.
=w
STEP /
Remove the wire connecting OUT to pin 14 of the 7490 counter. Connect IN to
pin 14. IN is adjacent to OUT on the SK-10 breadboarding socket. Continue
to execute the program in the single-step mode. You should observe a single
count on the 7490 counter for every nine clock pulses applied to the single
step circuit.
STEP 8
If you have a bus monitor, connect the latch enable (STB) input to logic 0.
Now single step through the program. You should observe the sequence of bytes
given below. Even if you do not have a bus monitor, please study the following:
Memory Instruction
address byte Mnemonic Description
003 000 343 IN Input byte into the accumulator from the
keyboard
003 OOL 000 000 Device code for keyboard on MMD-1 micro-
computer
000 000 160 160 INPUT machine cycle, during whtch a byte
ts input from the keyboard. The byte,
160, ts input tf you do not press any key.
The device code ts output as two identical
000 bytes on the address bus.
000 000 160 160 OUTPUT machine cycle, during whitch the
contents of the accwnulator are output to
port 0. This is the byte that ts input
from the keyboard. The device code ts
output as two identical 000 bytes on the
address bus.
003 005 000 000 LO address byte for the start of the program
003 006 003 003 HI address byte for the start of the program
. etc S
This program repeats itself every nine machine cycles. Why does a seven-byte
program take nine steps to execute?
17-34
Each step is a "machine cycle," and the IN and OUT instructions require an
additional machine cycle for proper execution. This extra machine cycle is
preset within the 8080A chip and is characteristics of other types of
instructions as well, including memory reference instructions, calls, returns,
PUSH, and POP.
Once source of difficulty tn this experiment ts that you must execute a program
at 750 kHz tntttally before you enter the single step mode of operation. If you
forget to do so, you wtll never leave the KEX program.
STEP 9
Press key 7 and keep it pressed. If you have a bus monitor, what byte appears
during the INPUT and OUTPUT machine cycles?
We observed the byte 36/ during both the INPUT and OUTPUT machine cycles. This
byte was also output to port 0. By being able to monitor information on the
bidirectional data bus, we were able to observe data moving into the accumulator
from the keyboard, and data moving out of the accumulator into the port 0 latch.
x
Save the 7490 counter, single-step, and bus monitor circuits and continue to the
following experiment.
»
.
Wess
EXPERIMENT NO. 5
PURPOSE
The purpose of this experiment is to construct a decoder circuit based upon the 74154
decoder chip that can generate sixteen different output device select pulses.
|
INPUTS OUTPUTS
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OUTPUTS
74154
A—3
Address A-2—
lines Ae
A—O
Stra To pin 14 of
7490 counter
©
O-NWtgoanw
OUT
D
C LAMP
e MONITORS
17-36
PROGRAM
LO address Instruction
byte byte » Mnemonic - Description
sTeP 1
In the circuit shown, you can generate sixteen consecutive output device select
pulses. Wire the circuit using a 74154 decoder chip.
If you have a three-digit octal bus monitor, you may wish to observe the contents
of the bidirectional data bus as you execute the program in the single step mode.
Wire the latch enable (STB) input on the bus monitor to logic 0.
°
.
STEP 2
In the program, use device code 003 at LO = 003. Load the program into read/write
memory. Be sure that the lamp monitor and pin 14 of the 7490 counter are connected
to pin 4 of the 74154 decoder.
STEP 3
Execute the program in the single step mode. Count how many OUT control signal
pulses occur every nine machine cycles, and write your answer in the space below.
You should observe one OUT pulse every nine machine cycles.
1/-37
step 4
It is common to denote a device select pulse by the notation, DS xxx, if it is
a logic 0 (or negative) pulse and by DS xxx if it is a logic 1 (or positive)
pulse. The letters, 'xxx' , denote the three-digit octal device code. The
bar on the top of a functional pulse code is the standard notation for a
logic zero active level.
In the schematic diagram, there is a wire connection between the No. 3 output
channel of the 74154 decoder and the 7490 counter. With the 8080A operating
at full speed, test some of the other decoder outputs and determine if any
other channel generates an output DS 003 pulse. Which channel is it?
Channel 3 at pin 4 on the integrated circuit chip should be the only one to
cause the counter to count at a rapid rate. All others are non-functional for
a device code of 003.
sTeP 5
Now change the instruction byte at LO = 003 to Ol. At which output channel on
the 74154 decoder do you observe the device select pulse? What would be the
proper way to deonte such a pulse, i.e., as DS xxx or DS xxx? What is Upioiocets
We observed the device select pulse at channel 1540 (pin 17). The proper way
to denote this pulse is DS 017.
STEP 6
During the machine cycle when a device select pulse is generated, what is the
logic state of lamp monitor A?
step /
At which machine cycle for the OUT instruction is a device select pulse generated,
the first, second, or third machine cycle?
»
The third machine cycle. The first two machine cycles are fetch cycles, which
input the operation code, 375 , and the device code, <B2> , from the memory
locations in which they are stored.
STEP 8
By varying the instruction byte at LO = 003, you can vary the 74154 decoder output
channel at which a device select pulse appears. For the device code bytes given
in the table below, at which 74154 output channel does the device select pulse
appear. Remember, when you change the program, you must be executing the KEX
monitor routine at 750 kHz.
000
001
002
003 OO
WNrH
010
017
020
025
050
Sed
We observed the following results for the last six device code bytes:
010 8
017 LS: >
020 0 :
025 5
Bild 15}
If you did not observe similar results, please repeat this step.
STEP 9
The 74154 decoder has only sixteen output channels, and you would initially expect
that it could decode only the first sixteen output device codes: 000, 001, 002,
003, 004, . . . 015, 016, and 017. Why do you observe device select pulses for
device codes greater than 017?
J/-39
Because the 74154 decoder circuit does not absolutely decode the 8-bit device code
byte. Only the four least-significant device code bits are decoded. Though you
can generate only sixteen different device select pulses, each unique device select
pulse can be generated in sixteen different ways using stxteen different device
codes. This is not good engineering practice in microcomputer interface design.
You should always attempt to absolutely decode both input and output device codes.
step 10
How would you absolutely decode sixteen out of the 256 possible device codes using
a 74154 decoder and one or more additional chips?
You can use another 74154 chip to enable the first 74154 decoder at the Gl input
pin. Alternatively, you can use a 4-input OR gate to enable the 74154 decoder
at the Gl input pin; address bits A-4, A-5, A-6, and A-7 would serve as inputs
to the OR gate. There are many decoder schemes which might be used.
Remove the 74154 decoder and lamp monttor circuit used in this experiment. The
7490 counter and single-step ctreutt will be used tn a subsequent experiment.
/-4)
EXPERIMENT NO. 6
»
PURPOSE
The purpose of this experiment is to demonstrate how the decoded addresses on the
Dyna-Micro printed circuit board can be used to generate input and output device
select pulses.
D LAMP
B MONITORS
A
Available on
MMD-|! microcomputer
DISCUSSION
You will find five solderless breadboarding pins adjacent to the 74L42 chip
17-4]
in the 1/0 decoder section of the computer printed circuit board. Look for
integrated circuit IC-18 (or Al18). The wiring diagram for the I/0 decoder
section is shown below;
n>
PROGRAM
LO address Instruction =
byte : byte Mnemonic : Description
sTeP 1 ;
Using a single 7402 chip, wire the circuit shown in the schematic diagram, in which
both the IN and OUT control signals are employed as shown. Load the program into
read/write memory.
STEP 2
Execute the program at 750 kHz, then move to single-step operation. What do you
observe on the four lamp monitors?
You should observe that the lamp monitors assocated with the OUT 006 and OUT 007
device select pulses are lit, whereas the other two are off at 750 kHz. These
two lamp monitors are lit once every sixteen machine cycles when the program is
single stepped.
1/-43
STEP 3
Why are the lamp monitors for the IN 004 and IN 005 device select pulses off?
STEP 4
Change all of the OUT instructions to IN instructions in the program. Use
the instruction code, 335 » for IN. Execute the program once again at 750 kHz.
What do you observe?
Now, the lamp monitors for the IN 004 and IN 005 pulses are lit, whereas the
OUT 006 and OUT 007 lamp monitors are unlit. The two input instructions
in the program generate two pulses that are detected by the lamp monitors.
The IN 006 and IN 007 device select pulses are not decoded by the circuit
given in this experiment.
EXPERIMENT NO. 7
PURPOSE
is to demonstrate the use of a device select pulse
The purpose of this experiment
to clear a 7490 counter. a:
Vec 6A 6Y 5A 5Y 4A 4yY
_fwlfa]fez]
1 [nfo] fslfe
pated, sPistietd?
A TY 2A ZY, 3A 3Y GND
7404 <
+5V GND
OUT 007
LAMP
»MONITORS
PROGRAM
LO address Instruction
byte byte Mnemonic Description
sTeP 1
To clear a 7490 decade counter, you will require a positive device select pulse.
Thus, you will be able to use the OUT 007 pulse that you produced in Experiment
No. 6.
Wire the circuit shown. Load the above program into read/write memory. Make
certain that the OUT 007 connection is made between the 7402 gate output and
the 7490 input at pin 2.
STEP 2
Execute the program at 750 kHz, then move to single step operation. The clock
frequency to the 7490 counter should be apo ce ears 10 Hz. We used a 0.05 uF
timing capacitor with our clock Outboard Single step through the program
with a pulser.
STEP 5
What behavior do you observe on the lamp monitors?
We observed a 10 Hz counting rate on the display LEDs until the third machine cycle
of the OUT instruction, at which time a device select pulse was generated and the
counter was cleared to zero. The counting resumed at the end of the third machine
cycle.
STEP 4
Does the instruction, DO which clears the accumulator, have anything to do with
the clearing of the 7490 counter?
No! In this program, it has no effect on the 7490 chip since we have not made
any connection between the bidirectional data bus, DO to D7, and the 7490 chip.
Consequently, the 7490 does not know that the accumulator has been cleared.
You may remove all etreuitry from your SK-10 breadboarding socket except the
single-step and counter circuits, which you will use in a subsequent experiment.
Rev. 9/22/77
7-46
EXPERIMENT NO, 8
PURPOSE »
DATA INPUTS
Vec ‘ A3 82 A2 Al B1 Fl a
7485
+5V GND .
+5V GND
17-417
PROGRAM
LO address Instruction
byte byte Mnemonic Description
sTeP 1
You will use the circuit shown in Experiment No. 4 in this Unit to count the
device select pulses that are produced by the pair of 7485 comparator chips.
What change must you make to the 7490 counter circuit that you retained from
the preceding experiment?
Reconnect the 7490 counter RESET input (pin 2) to logic 0 (GND) and connect
the CLOCK INPUT (pin 14) to OUT 306 from the 7402 2-input NOR gate.
STEP 2
Wire the circuit shown and load the above program into read/write memory.
STEP3
Execute the program at 750 kHz, then move to the single step mode of execution.
Single step through the execution of the program, and explain in the space below
what you observe on the counter's lamp monitor display.
We observed a single count each time the OUT instruction was executed, or one
count every seven machine cycles.
STEP 4
Now change the device code at LO = 002 to 305. Execute the program at 750 kHz,
Rev. 9/22/77
17-48
then single step through it once again. Do you know observe counting on the
output lamp monitors connected to the 7490 chip?
We did not, because the address generated by the OUT instruction no longer
matched the address preset at the comparator circuit.
STEP 5
Could the preset address be changed to correspond to a new software device
code at LO = 002?
Yes.
Change the address byte at LO = 002 to 3/7. Does program execution cause any
counting?
No.
Now rewire BO through B& on the comparator chips so that they are all at logic 1.
Does this cause counting when you execute the program? Why?
Remove the 7485 decoder etreutt from your breadboard,.but save the counter and
single-step ctreuits for the following experiment. ;
.
?
Yes. Now the hardware preset address and the software device code match.
17-49
EXPERIMENT NO. 9
PURPOSE
The purpose of this experiment is to demonstrate the use of a 7430 8-input NAND
gate to absolutely decode the 8-bit address bus device code byte.
Vcc 6A
[14
GNO
7430
1K 10 106 GNO 2K 20 26 2
PROGRAM
LO address Instruction
byte byte Mnemonic Description
002 306 306 Device code for the preset input to the
7476 flip-flop
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pllos
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:
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Bens
rarepao peo]
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upj i A iI E
[21
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=4 tas
=O
Wey
004 317 ahly/ Device code for the clear input to the
7476 flip-flop
STEP 1
If you have a solid-state relay and a fan or other appropriate AC power device,
such as a lamp, we would encourage you to wire the entire circuit shown on the
previous page. Otherwise, wire the circuit up to the buffer to the solid-state
relay, but not including it. Use a 7490 counter, as was done in Experiment No.
4, to count output pulses from the 7476 flip-flop.
STEP 2
Wire the circuit shown jn the diagram and load the above program into memory.
STEP 3
You will single step the execution of the program. Initiate execution at 750 kHz,
the move to the single-step mode. If you are using a solid-state relay, you may
wish to temporarily remove the wire connection between the 7476 flip-flop and the
buffer until you are single stepping the program. Why?
The highest rate at which you can turn on and off the relay is double the line
frequency, or 120 times per second. If you operate the microcomputer at 750 kHz
with the above program, you will be attempting to turn on and off the relay at
a rate that is greater than 10,000 times a second.
step 4
As you execute the program in the single-step mode, explain what you observe.
17-52
We observed a single count each time we made a loop through the program. When
we wired the solid-state relay circuit, we observed that the fan would turn
on when we executed the instruction starting at LO = 001. When we executed
the OUT instruction at LO = 003, the fan would turn off.
We performed the solid-state relay experiment several times, and in each case
observed the result above. This is an important experiment.
STEP 5
What modifications to the program would you have to make in order to execute
it at 750 kHz?
You would need to provide at least two time delay loops to give the solid-state
relay sufficient time to turn on and off. One delay Joop would be located between
the OUT 306 instruction and the OUT 317 instruction; the other loop would be located
immediately after the OUT 317 instruction, but before the OUT 306 instruction.
?
.
Ts
REVIEW
The following questions will help you review device select pulses.
1. Device select pulses can be used to clear, strobe, trigger, etc. integrated
circuit chips. For the chips indicated below, identify the correct pin number--
and whether a positive or negative device select pulse is required--at which the
indicated operation must be performed.
3. How many machine cycles are there for the following 8080A instructions?
OUT <B2>
IN <B2>
MOV C,M
MVI B <B2>
INR A
DCR B
negative device seltct (DS) pulse at pin 1
negative device select pulse at pin 10
positive device select pulse at pin 7, with pin 6 at logic 0
. positive device select pulse at pin 9 ‘
2. A device select pulse will be produced for the following output device code
bytes (in octal code):
005
025
045
065
105
125
145
165
205
225
245
265
305
325
345
365
You are not absolutely decoding the device code byte. If you were, the only device
code that would provide an output on the 74154 decoder chip.would be 005.
sh three
five
. three
three
two
three
two
three
one
ur one
tp
So
moan
18-1
UNIT NUMBER 18
INTRODUCTION
OBJECTIVES
bo Convert an 8-bit instruction code into both octal code and hexadecimal code
with the aid of a table provided in the unit.
g fo) Describe the characteristics of the five condition flags in the 8080A
pare PRBOCenee® chip.
=
Describe the operation of the stack and the instructions that influence
=| o
its contents and the location of the stack.
Rev. 9/22/77
18-2
MICROCOMPUTER PROGRAMMING
Unless you have a background in computer science or possess a special knack for
computer programming, you will probably find machine level and assembly level
programming somewhat tedious and difficult initially. There does not appear to
be any shortcut to learning programming. In due time, you will become sufficiently
familiar with your instruction set and with programming tricks to be able to write
programs of modest size with little effort. You will be able to apply skills that yo
learn with one instruction set to other instruction sets, whether they are for
microcomputers, minicomputers, or even mainframe computers.
For those of you who are interested in high-level languages, you do not have long
to wait. In addition to the MITS BASIC package, a BASIC 8080 software compiler
from the Livermore Laboratory and an 8080 FORTRAN compiler (Control Logic, Inc.)
are due during the summer of 1976. The Livermore compiler is being donated
royalty-free.
The point that we would like to make, however, is that you probably will need to
learn some assembly language programming. Simple programs and subroutines can
be written as easily and quickly in assembly language as they can in a higher
level language; such programs are also executed more quickly, require less memory,
and are probably easier to understand. You will need to learn assembly language
programming in order to understand other assembly programs that receive widespread
distribution. Finally, a knowledge of assembly language programming provides
the basis for understanding and comparing other instruction sets. If you have
someone else do your programming, it will be expensive; if you do it yourself, it
will also be expensive. However, if you can adapt other programs to your
applications, your programming costs will be less.
We would like to list some sources for 8080/8080A programming information that
we have found to be useful: ae
Other chapters discuss the functions of a computer, the 8080 CPU, techniques
of interfacing to the 8080, and the 8080 family of hardware components.
If you are doing serious work with 8080 microcomputers, you should have this
manual,
An excellent manual that discusses such topics as the program counter, stack
pointer, computer program representation in memory, memory addressing,
condition bits, assembly language, and the entire 8080 instruction set.
18-3
For the student who has some experience with 8080 assembly language
programming, this manual will demonstrate a number of very useful
programming techniques.
PAPER TAPE LABELER (8080). Accepts ASCII character from teletype keyboard
and punches corresponding alpha-numeric character on tape.
IBM SELECTRIC OUTPUT PROGRAM (8080). Allows IBM Selectric Model 731 to
be used as an output device.
8080 DIS-ASSEMBLER (8080 PL/M). This program inputs a hexadecimal tape and
generates a symbolic assembly language program suitable for modifications
and/or assembling.
MEMORY DIAGNOSTIC PROGRAM (8080). Writes test bytes in any range of memory
and compares the written bit combination with what is read. Upon detection
of a defective memory location, an error message is printed specifying the
address, reference, and actual values.
MATH (8080). Routines for fixed and floating point arithmetic together with
a demonstration program that performs algebraic evaluation (from left to
right with no operator precedence) and allows unlimited parentheses nesting.
point precision. [NOTE: We have used this program and like it very much.
The entire program requires approximately 2 1/2 K of memory.]
8080 FLOATING POINT PACKAGE WITH BCD CONVERSIGN ROUTINE (8080). Performs
floating addition, subtraction, multiplication, division, fixing, floating,
negation, and conversion from floating point to BCD with exponent.
a x? a 1 OG ap Aol ene
N-BYTE BINARY MULTIPLICATION AND LEADING ZERO BLANKING (8080). The program
performs binary multiplication on two numbers and returns a result that may
be up to 255 bytes in length.
8080 CROSS COMPILER ON THE PDP-11 (8080). Accepts input in a format familiar
to PDP-11 users and produces a fully coded listing, symbol table, and
punched tape for use with the standard loader.
SOURCE PAPER TAPE TO MAGNETIC CASSETTE (8080). Will copy a source paper tape
onto a magnetic cassette. End statement must be followed by a carraige
return. Program will ignore leading blanks.
SUBROUTINE LOG. This subroutine takes the log to any integer base of any
positive floating point number.
18-6
Nat Wadsworth writes well. You can pick up many microcomputer programming
techniques from the above.
6. Zilog Corporation, 2Z80-CPU Technical Manual, Zilog, Inc., 170 State Street,
Los Altos, California 94022, $7.50. ~
You do not obtain many programming hints from this manual, but it is
very interesting to compare the Z80 chip with the 8080A in terms of the
instruction set.
The quality of individual articles vary, but yow will find useful programs
the
and programming techniques discussed in this journal, which is one of
magazines that are aimed at the hobby microcomputer market.
The magazine, which is directed toward radio amateurs, has a 40-page section
entitled I/0 that is devoted to practical uses for microcomputers. Since
hams are very interested in communications, you should find increasing
coverage of digital data communications in this magazine.
18-7
Machine code and assembly language summaries of the 8080 instruction set are
available from a number of different sources:
2. Tychon, Inc., 8080 Octal Code Card, Tychon, Inc., P. 0. Box 242, Blacksburg,
Virginia 24060.
A sliding insert permits you to rapidly find the 8-bit octal instruction
code for an assembly language instruction. Flag status after an instruction
is also indicated.
3. Martin Research, 8080 Instruction Set, 3336 Commercial Ave., Northbrook, Ill. 60062
Single registers in the 8080 microprocessor chip store a single byte, UeGns CLSMe
contiguous bits.
There are two different sets of registers in the 8080 chip: those that we can
address from a program and those that we cannot. The program addressable registers
are shown in the figure on the following page and include the following:
regtster
register
register
register
register
register
SHRRoQawy
~
Two other registers over which, in special cases, you have some control include
Additional registers that are required to allow the 8080A microprocessor chip to
perform its internal operations include two 8-bit temporary registers used singly or
as a pair, W temporary register and Z temporary register; an 8-bit temporary
accumulator in the arithmetic/logic unit; and an 8-bit temporary register in the
arithmetic/logic unit. You cannot address or control the contents of these
temporary registers from a program and will not know when the 8080 uses them.
program counter The 16-bit register in the 8080A microprocessor chip that contains
the memory address of the next instruction byte that must be
executed in a computer program.
general purpose In the 8080A microprocessor chip, 8-bit registers that can
registers participate in arithmetic and logical operations with the
contents of the accumulator.
yoDdIS
JOJUIOg
40481594 wosboig soyunog
UOIL,INI{SU]
p400 sng
y9407/4933ng ssosppy JOyjng
|DUOIJDeUIPIG
DjJDG SMG sseippy
sng
8 siiq 9] $4!q
. ‘
etre. |
DATA BUS
BUFFER/LATCH
(8 BIT) (8 BIT)
INTERNAL DATA BUS INTERNAL DATA BUS
PROGRAM COUNTER
DECIMAL INCREMENTER/DECREMENTER
ADJUST ADDRESS LATCH (16)
TIMING
AND
CONTROL
power [ —> +12Vv
SUPPLIES |——» 45y DATA BUS INTERRUPT HOLD WAIT
WRITE CONTROL CONTROL CONTROL CONTROL SYNC CLOCKS
— > -5Vv
—-. GND
Figure 18-2. Functional block diagram of the 8080A central processing unit (CPU).
Note the internal data bus, which communicates with the external bi-
directional data bus through a data bus buffer/latch located within the
8080A chip.
ii
tae pointer
EE AZ
AGO ®*
(ATreg
fs
LEGLETE?r
g
tneteuction code = & wigue Gdit binary number that encodes 2m operation that the
ZOBA microprocessor chip can perform.
UBHULIS h decoder within the DWA microprocessor chip that decodes the
GLOOCL# 4metruction code into 2 series of actions that the microprocessor
performs.
STRUCTION RESISTER
INSTRUCTION A series
‘ An operation.
DECODER of actions.
t
CLOCK up to 256
decoded outputs.
"Rach operation that the processor can perform is identified by a unique binary
number known as an tustructton code. An eight-bit word used as an instruction
code can distinguish among 256 alternative actions, more than adequate for most
processors."
"The mechanism by which the processor translates an instruction code into specific
processing actions requires more elaboration than we can here afford. The concept,
however, will be intuitively clear to an experienced logic designer. The eight
bits stored in the instruction register can be decoded and used to activate
selectively one of a number of output lines, in this case up to 256 lines. Each
line represents a set of activities associated with execution of a particular
instruction code. The enabled line can be combined coincidentally with selected
timing pulses, to develop electrically sequential signals that can be used top
initiate specific actions. This translation of code into action is performed by
the instruction decoder and by the associated control circuitry."
~
The important point here is that the instruction code is translated into a sequence o
specific actions. The two-phase clock is vital to this process. The actions may res
in the moving of data from memory to the accumulator, or adding the contents of
register B to register A, or complementing the accumulator, or any of the specific
operations contained in the 8080A instruction set. Nevertheless, each specific
operation performed by an 8080A instruction is the result of one or more spectfic
acttons caused by the tnstructiton decoder.
The purpose of this section is not to sub-divide the 8080A instruction set into
categories, but rather to identify the basic types of operations that the chip
actually performs.
o MISCELLANEOUS OPERATIONS
No operation
Halt
Enable the interrupt system
Disable the interrupt system
Complement the accumulator
Set the carry flag
Complement the carry flag
Most of the time, all that the 8080A microprocessor chip does is to move a byte
from one location to another or performs an arithmetic or
logical operation. Rarely, it performs one of the miscellaneous operations.
In other words, the chip does not just compute; it moves bytes around.
18-14
We encourage you to learn as soon as possible the 8080 mnemonics, so that you
can do assembly language programming, read other assembly language programs for
the 8080 , and improve your capability to understand the instruction sets for
other microprocessor chips. The 8080 mmemonics are listed by groups in the
Intel 8080 Microcomputer Systems User's Manual, which we recommend that you
obtain. Here, we will first list the mmemonics in alphabetic order, and then
proceed to describe them in detail. We acknowledge two reference sources for
this material,
Instruction code
LDA <B2> <B3> 072 Load accumulator direct with contents of memory
addressed by <B2> <B3>
LDAX B 012 Load accumulator indirect with contents of memory
addressed by register pair B
LDAX D 032 Load accumulator indirect with contents of memory
addressed by register pair D
LHLD <B2> <B3> 052 Load L and H with contents of M and Mtl, respectively
LXI B <B2> <B3> 001 Load immediate bytes into register pair B
LXI D <B2> <B3> 021 Load immediate bytes into register pair D
Ext B <B2> <B3> 041 Load immediate bytes into register pair H
LXI SP <B2> <B3>061 Load immediate bytes into stack pointer
Not all possible 256 instruction codes are employed by the 8080A microprocessor chip)
Missing codes include the following:
010 08
020 10
030 18
040 20 |
050 28
18-17
060 30
070 38
Sis CB
330 Dg
335) DD
355 ED
375 FD
+ These instructions are not easily translated into hexadecimal notation without
register or other information. This is one reason why we have chosen to work
with octal numbers.
We now shall proceed to describe the 8080 instruction set in detail. We shall use
material from both the Intel 8080 Microcomputer Systems User's Manual and The
uCOM-8 Software Manual, courtesy of the Intel Corporation and NEC Microcomputers,
Inc., respectively. For your use, we provide several pages from the Intel manual
to help you understand the significance of the terms, symbols, and abbreviations
used in the description of each instruction. We shall group the 8080 instruction
set as Intel does:
DATA TRANSFER GROUP: Move data between registers or between memory and
o
registers
OSot .
A computer, no matter how sophisticated, can only are programs available which convert the programming lan-
do what it is ‘‘told” to do. One “‘tells’” the computer what guage instructions into machine code that can be inter-
to do via a series of coded instructions referred to as a Pro- preted by the processor.
gram. The realm of the programmer is referred to as Soft-
One type of programming language is Assembly Lan-
ware, in contrast to the Hardware that comprises the actual
guage. A unique assembly language mnemonic is assigned to
computer equipment. A computer's software refers to all of
each of tha.computer’s instructions. The programmer can
the programs that have been written for that computer.
write a program (called the Source Program) using these
When a computer is designed, the engineers provide mnemonics and certain operands; the source program is
the Central Processing Unit (CPU) with the ability to per- then converted into machine instructions (called the Object
form a particular set of operations. The CPU is designed Code). Each assembly language instruction is converted into
such that a specific operation is performed when the CPU one machine code instruction (1 or more bytes) by an
control logic decodes a particular instruction. Consequently, Assembler program. Assembly languages are usually ma-
the operations that can be performed by a CPU define the chine dependent (i.e., they are usually able to run on only
computer's Instruction Set. one type of computer).
~
Each computer instruction allows the programmer to
initiate the performance of a specific operation. All com-
THE 8080 INSTRUCTION SET
puters implement certain arithmetic operations in their in-
struction set, such as an instruction to add the contents of The 8080 instruction set includes five different types
two registers. Often logical operations (e.g., OR the con- of instructions: af
tents of two registers) and register operate instructions (e.g., e Data Transfer Group—move data between registers
increment a register) are included in the instruction set. A or between memory and registers
computer's instruction set will also have instructions that
e Arithmetic Group — add, subtract, increment or
move data between registers, between aregister and memory,
decrement data in registers or in memory
and between a register and an I/O device. Most instruction
sets also provide Conditional Instructions. A conditional e Logical Group — AND, OR, EXCLUSIVE-OR,
instruction specifies an operation to be performed only if compare, rotate or comp!ement data in registers
certain conditions have been met; for example, jump to a or in memory
particular instruction if the result of the last operation was e Branch Group — conditional and unconditional
zero. Conditional instructions provide a program with a jump instructions, subroutine call instructions and
decision-making capability. return instructions
By logically organizing a sequence of instructions into e Stack, 1/O and Machine Control Group — includes
a coherent program, the programmer can ‘tell’ the com- 1/O instructions, as well as instructions for main-
puter to perform a very specific and useful function. taining the stack and internal control flags.
The computer, however, can only execute programs
whose instructions are in a binary coded form (i.e., a series Instruction and Data Formats:
of 1’s and 0's), that is called Machine Code. Because it Memory for the 8080 is organized into 8-bit quanti-
would be extremely cumbersome to program in machine ties, called Bytes. Each byte has a unique 16-bit binary
code, programming languages have been developed. There address corresponding to its sequential position in memory.
Data in the 8080 is stored in the form of 8-bit binary ®@ Immediate — The instruction contains the data it-
integers: self. This is either an 8-bit quantity or a
DATA WORD 16-bit quantity (least significant byte first,
most significant byte second).
PaaS
Dee DewDet Dy pepe iD, Le Unless directed by an interrupt or branch instruction,
MSB LSB the execution of instructions proceeds through consecu-
tively increasing memory locations. A branch instruction
When a register or data word contains a binary num-
can specify the address of the next instruction to be exe-
ber, it is necessary to establish the order in which the bits
cuted in one of two ways:
of the number are written. In the Intel 8680, BIT 0 is re-
ferred to as the Least Significant Bit (LSB), and BIT 7 (of @ Direct —The branch instruction contains the ad-
an 8 bit number) is referred to as the Most Significant Bit dress of the next instruction to be exe-
cuted. (Except for the ‘RST’ instruction,
(MSB).
byte 2 contains the low-order address and
The 8080 program instructions may be one, two or
byte 3 the high-order address.)
three bytes in length. Multiple byte instructions must be
stored in successive memory locations; the address of the @ Register indirect — The branch instruction indi-
cates a register-pair which contains the
first byte is always used as the address of the instructions.
address of the next instruction to be exe-
The exact instruction format will depend on the particular
cuted. (The high-order bits of the address
operation to be executed.
are in the first register of the pair, the
Single Byte Instructions
low-order bits in the second.)
The RST instruction is a special one-byte call instruc-
D7! | Do Op Code tion (usually used during
interrupt sequences). RST in-
cludes a three-bit field; program control is transferred to
Two-Byte Instructions the instruction whose address is eight times the contents
SS eee Do | Op Code of this three-bit field.
Byte One | D7
* Multiplication
DDD or SSS_ REGISTER NAME
re “Is exchanged with”
111 A
000 B mar The one’s complement (e.g., (A))
001 (G3 n The restart number O through 7
010 D
NNN The binary representation 000 through 111
011 E
for restart nymber O through 7 respectively.
100 H
101 Le
rp One of the register pairs:
Description Format:
B represents the B,C pair with B as the high-
The following pages provide a detailed description of
order register and C as the low-order register;
the instruction set of the 8080. Each instruction is de-
D represents the D,E pair with D as the high- scribed in the following manner:
order register and E as the low-order register;
ur The MAC 80 assembler format, consisting of
H represents the H,L pair with H as the high- the instruction mnemonic and operand fields, is
order register and L as the low-order register; printed in BOLDFACE on the left side of the first
SP represents the 16-bit stack pointer line.
register. . The name of the instruction is enclosed in paren-
RP The bit pattern designating one of the regis- thesis on the right side of the first line.
ter pairs B,D,H,SP: . The next line(s) contain a symbolic description
RP REGISTER PAIR of the operation of the instruction.
on
6. The last four lines contain incidental informati
num-
about the execution of the instruction. The
ber of machine cycles and states required to exe-
cute the instruction are listed first. If the instruc-
as in a
tion has two possible execution times,
sep-
Conditional Jump, both times will be listed,
data ad-
arated by a slash. Next, any significant
dressing modes (see Page 4-2) are listed. The last
by
line lists any of the five Flags that are affected
the execution of the instruction.
This group of instructions transfers data to and from registers and memory.
Condition flags are not affected by any instruction in this group.
MoV rl, r2
MOV tM
of the memory address
The MOV r,M instruction transfers data from M (the contents
register pair H,L) to the specified destinatio n register D,
specified by the
or the accumulator, A.
which may be any of the single registers B, C, D, H, or L
the contents
You duplicate the contents of the memory address into a register;
of memory remain unchanged.
18-22
eee ey
een
Cycles: 2
States: 7
Addressing: reg. indirect
Flags: none
MOV M,r
fo ee eee
Cycles: 2
States: 7
Addressing: reg. indirect
Flags: none 4
The MOV M,r instruction transfers data from the specified source register S to
M (the memory address specified by the register pair H,L). The source register
may be any of the single registers B, C, D, E, H, or L or the accumulator A. The
register contents are duplicated in memory; the contents of the register remain
unchanged.
MV] r,data
o| 0 D D D 1 | 1 0
data
Cycles: 2
States: 7
Addressing: immediate
Flags: none
18-23
The MVI r,data instruction transfers data from the second byte of the two-byte
instruction to the specified destination register D (or r). The term immediate
refers to the fact that the data byte is contained within the multi-byte
instruction. The specified destination register may be any of the single
registers B, C, D, E, H, or L, the accumulator A, and M (the contents of the
memory address specified by the register pair H,L). When the destination is M,
you have the instruction MVI M,data, which is discussed below. The data can be
any 8-bit binary number between 00000000 and 11111111.
MV] M,data
ee ee ee ee
data
Cycles: 3
States: 10
Addressing: — immed./reg. indirect
Flags: none
The MVI M,data instruction transfers data from the second byte of the instruction
to M (the memory address specified by the register pair H,L). The data can be
any 8-bit binary number between 00000000 and 11111111.
LXI rp,data 16
P Ge gatnG 1
low-order data
high-order data
Cycles: 3
States: 10
Addressing: immediate
Flags: none
13-24
instruction causes a 16-bit data quantity contained in the second
The LXI rp,data
pair specified
and third bytes of the instruction to be loaded into the register
by RP. RP can be any of the double registers HL, DE, or BC or the stack pointer,
y. The second
which are represented by the mnemonics H, D, B, and SP, respectivel
bits of
instruction byte is loaded into the LO registers L, E, C, or the LO eight
the stack pbinter; the third instruction byte is loaded into the HI registers
H, D, B, or the HI eight bits of the stack pointer. The 16-bit data word can vary
from 0000000000000000 to 1111111111111111, in binary notation.
The following diagrams illustrate some of the characteristics of the MOV, MVI,
and LXI instructions. Only two sets of MOV rl,r2 instructions are shown.
| eee ee
i M l
ee wee ewe eo ~~
Loses
Note that LXI rp,data is equivalent to two MVI r,data instructions. Thus,
LXI B
<B2>
<B3>
is equivalent to
MVI B
<B2> (corresponds to <B3> tn the LXI B instruction
MVI C
<B2> (corresponds to <B2> in the LXI B instruction
Counter
H
ct
PCHL
Program
SN SPHL
Stack Pointer
STA addr
po ae (na ene
low-order addr
| high-order addr
Cycles: 4
States: 13
Addressing: direct
Flags: none
9/22/77
18-26
LDA addr
T lang | 0 | 1 ] 0
low-order addr
high-order addr
Cycles: 4
States: 13
Addressing: direct
Flags: none
The LDA addr instruction permits you to load the accumulator with the contents
of the memory location specified by bytes <B2> and <B3> in the instruction. You
need not use the H,L register pair. The LO addres byte is <B2> and the HI address
~
byte is <B3>.
LHLD addr
low-order addr
high-order addr
Cycles: 5
States: 16
Addressing: direct
Flags: none
Rev. 9/22/77
18-27
bytes <B2> and <B3> in the instruction, 7t.¢e., addr. ‘The H register is loaded with
the memory byte located at addr + 1. Thus, you perform a 16-bit transfer of a
memory address to the register pair H,L. Once you learn XCHG, you will observe
that the section of code,
LHLD
<B2>
<B3>
XCHG
is functionaily equivalent to
EXT
<B2>
<B3>
MOV E,M
INX H
MOV D,M
The first section of code requires 20 states for execution; the second section of
code requires 29 states.
XCHG
Cycles: 1
States: 4
Addressing: register
Flags: none
The XCHG instruction causes the contents of the register pairs D,E and H,L to be
exchanged. To be specific, the contents of registers D and H are exchanged, and
the contents of registers E and L are exchanged, This instruction permits you
to use register pair H,L as a memory address while another address is held in
register pair D,E. You can modify the contents of register pair D,E without changing
register pair H,L. For example, register pair H,L may specify a memory location
that you use to modify register pair D,E. Two XCHG instructions in sequence,
XCHG
XCHG
is equivalent to a no operation.
18-28
SHLD addr
low-order addr
high-order addr
Cycles: 5
States: 16
Addressing: direct
Flags: none
The SHLD addr instruction causes the contents of the L register to be stored at
the memory location given by bytes <B2> and <B3>in the instruction, 7.e., addr.
The contents of the H register are stored in the memory location, addr + l.
In other words, you perform a 16-bit transfer of an address byte in register
pair H,L to two successive memory locations, addr and addr + 1. This instruction
is useful in creating a group of memory locations that contain address information
rather than data. As with most 8080A instruction, byte <B2> is the LO address byte
and byte <B3> is the HI address byte of addr.
XCHG
SHLD
<B2>
<B3>
LXI H
<B2>
<B3>
MOV M,E
INX H
MOV M,D
LDAX TP
The LDAX rp instruction permits you to load the accumulator with the contents of
the memory location addressed by a register pair other than register pair H,L.
Thus, with LDAX B, you use register pair B,C to supply the 16-bit memory address;
with LDAX D, you use register pair D,E to supply the address. The section of
code,
18-29
LXI D
<B2>
<B3>
LDAX D
“iol Vil
<B2>
<B3>
MOV A,M
iL alee ei 1 ca
Cycles: 2
States: 7
Addressing: reg. indirect
Flags: none
STAX ©P
0 | 0 R | ie | 0 | 0 1 0
Cycles: 2
States: 7
Addressing: reg. indirect
Flags: none
The STAX rp instruction permits you to store the contents of the accumulator in the
memory location addressed by either register pair B,D or register pair D,E. The
section of code,
LXI B
<B2>
<B3>
STAX B
Rev. 9/22/77
18-9)
LXI H
<B2>
<B3>
. MOV M,A
The condition flags are not affected by any of the instructions in the following
list:
MOV rl1,r2
MOV r,M
MOV M,r
MVI r, data
MVI M, data
LXI rp, data 16
STA addr
LDA addr
XCHG
LHLD addr
SHLD addr
LDAX rp =
STAX rp
These instructions comprise the data transfer group in the 8080A microprocessor.
ARITHMETIC GROUP
ADD ©
1 0 0 0 0 S S S
Cycles: 1
States: 4
Addressing: register
Elags: © 2:5, PCY AG
Rev. 9/22/77
18-3]
The ADD r instruction causes the contents of the source register S to be added
to the contents of the accumulator. The source register can be any of the
general purpose registers B, C, D, E, H, L, the accumulator A, or M (the
contents of memory as addressed by register pair H,L). The ADD M instruction is
described below. The instruction affects all four of the testable flag bits:
Carry, Parity, Zero, and Sign. The Auxiliary Carry flag is also affected.
ADDM
Cycles: 2
States: 7
Addressing: reg. indirect
Flags: Z,S,P,CY,AC
The ADD M instruction causes the contents of the memory location M, which is
addressed by register pair H,L, to be added to the contents of the accumulator.
The memory contents remain unchanged after the addition. The instruction affects
all five flags and has two machine cycles.
AD] data
1 1 0 | 0 0 a 1 0
data
Cycles: 2
States: 7
Addressing: immediate
Flags: Z,S,P,CY,AC
The ADI data instruction causes the data present in the second byte of the
instruction to be added to the contents of the accumulator. The instruction
affects all five flags.
18-32
ADCr (Add Register with carry} ADC M (Add memory with carry)
(A) ~~ (A) + (r) + (CY) (A) <— (A) + ((H) (L)) + (CY)
The content of register r and the content of the carry The content of the memory location whose address is
bit are added to the content of the accumulator. The contained in the H and L registers and the content of
result is placed in the accumulator. the CY flag are added to the accumulator. The result
is placed in the accumulator.
1 0 0 0 1 S S S aia aT
tak
es |
1 aly 0 ar 0 ! 0 1 1 1 0 |
Cycles: 1
States: 4 Cycles: 2
Addressing: register States: 7
Flags: 2.S,P.CY,AC Addressing: reg. indirect
Flags: 2Z,S,P.CY,AC
To quote the yCOM-8 Software Manual: "In order to perform add and subtract
operations, some special arithmetic instructions are required. Multiple digit
arithmetic requires that two items be monitored and saved somewhere. These two
items are the sum of the digits as they are added, and the presence or absence
of a carry bit. When a carry bit is produced, it’must be added to the sum of
the next digits. Similarly, with subtract operations, the existence of a borrow
must be detected so it can be deducted from the difference of the next digits.
The Add with Carry and Subtract with Borrow instructions provide simple monitor-
ing and saving of carry bits, making multi-digit addition and subtraction quite
straightforward. ADC r, ADC M, and ACI data are the Add with Carry instructions.
ADC r causes the contents of the source S to be added to the sum of the
accumulator contents and the carry bit." .
The ADC r and ADC M instructions are similar to the ADD r and ADD M instructions;
the only difference is that the carry bit is added to the least-significant bit
in the 8-bit accumulator byte. All flags are affected by these instructions.
Memory location M is addressed by the contents of register pair H,L.
AC] data
Cycles: 2
States: 7
Addressing: immediate
Flags: Z,S,P,CY,AC
18-33
The ACI data instruction causes the 8-bit data quantity present in the second byte
of the instruction to be added to the sum of the ac¢cumulator contents and the
carry bit. The instruction affects all five flags.
1 0 0 1 0 1 1 0
Cycles: 1
States: 4 Cycles: 2
Addressing: register States: 7
Flags: Z,S,P,CY,AC Addressing: reg. indirect
Flags? “ZS, PCY AC
The SUB r instruction causes the contents of the source register S to be subtracted
from the accumulator. The source register can be any of the general purpose
registers B, C, D, E, H, and L, the accumulator A, or M (the contents of memory
as addressed by register pair H,L). All five flags are affected by the execution
of this instruction. If you wish to clear the accumulator, the single instruction,
SUBA
SUI data
Cycles: 2
States: 7
Addressing: immediate
Flags: 2Z,S,P,CY,AC
The SUI data instruction causes the 8-bit data quantity specified in the second
18-34
SBBr (Subtract Register with borrow) SBBM “(Subtract memory with borrow)
(A) <— (A) —(r) — (CY) (A) ~<— (A) — ((H) (L)) — (CY)
The content of register r and the content of the CY The content of the memory location whose address is
flag are both subtracted from the accumulator. The contained in the H and L registers and the content of
result is placed in the accumulator. the CY flag are both subtracted from the accumula-
Tr on re tor. The result is pla
placed iin the accumulator
lator.
1 0 0 1 U 5 S S T T i T
1 0 0 1 1
Cycles: 1
States: 4 Cycles: 2
Addressing: register States: 7
Flags: Z,S:P°CY,AG Addressing: — reg. indirect
Flags: 2Z,S,P,CY,AC
from the
The SBB r instruction causes the contents of the squrce S to be subtracted
difference of the accumulator contents and the borrow bit. The source register can
A;
be any of the general purpose registers B, C, D, E, H, and L; the accumulator
or M, the contents of memory addressed by register pair H,L. All five flags are
affected by the SBB r and SBB M instructions.
SBI data
accumulator.
data
Cycles: 2
States: 7
Addressing: immediate
Flags: Z,S,P,CY,AC
The SBI data instruction causes the 8-bit data quantity specified in the second
instruction byte to be subtracted from the difference of the accumulator contents
and the borrow bit. All five flags are affected.
18-35
Some examples of the various addition and subtraction operations would be appropriate.
Consider the following program: :
ADD B
ADD C
Carry bit
Note carefully the behavior of the carry bit in this situation. If there is no
carry out of the most significant bit (MSB) in the accumulator, the carry bit is
cleared; it there is a carry out of the most significant bit in the accumulator
during the addition, the carry bit is set. When you added B to the accumulator,
you had a carry. When you added the contents of C to the sum, there was no carry.
The carry from previous operations is not preserved, or "carried forward."
Now let us contrast the above results with the behavior of the following section
of code:
ADC B
ADC C
Assume the same initial values for registers A, B, C, and the carry bit. You
would obtain the following results:
Carry bit
SUB B
SUB C
for the same initial values of registers A, B, C, and the carry bit. Note that
if you perform a borrow out of the MSB of the accumulator, the carry bit is set;
if no borrow occurs, the carry bit is cleared. You thus should observe the following:
18-36
Carry -bit
SBB B
SBB C
Carry bit
When we perform the SBB C operation, we subtract the contents of register C from
the difference between the borrow bit and the contents of the accumulator:
The ADC r and SBB r instructions are used whenever you perform double or triple
precision arithmetic operations. A double precision arithmetic operation is one
which is performed on two 16-bit quantities to yield a 16-bit result. A triple
preciston is one which is performed on two 24-bit quantities to yield a 24-bit
result. The above examples of addition and subtraction operations are courtesy
of NEC Microcomputers, Inc. in their uCOM-8 Software Manual.
DAA ?
iy oles re oa es 1 1
Cycles: 1
States: 4
Flags: Z,S,P,CY,AC
18-37
To quote the uCOM-8 Software Manual: "In order to perform operations in binary
coded decimal (BCD), one special instruction is needed. When the 8080A CPU
performs an arithmetic operation, it produces the result in binary. When working
in BCD this does not produce the correct result. To remedy this, a DAA instruction
is used. DAA stands for Decimal Adjust Acccumulator, which is exactly what DAA
does. The DAA instruction treats the 8-bit Accumulator as two 4-bit Accumulators.
Through the use of a non-testable flag known as the Auxiliary Carry, the DAA
operation adjusts the result of a binary addition operation to packed BCD."
"For addition, the DAA instruction causes the following operation. If the Auxiliary
Carry is set to one or the least significant ntbble (LSN) is greater than 9, six
is added to the least significant nibble. Then, if the Carry flag is set to one
or the most significant nibble is greater than 9, six is added to the most signif-
icant nibble (MSN)." The term, nibble is defined as,
The least significant nibble (LSN), most significant nibble (MSN), Accumulator,
Auxiliary Carry flag (ACy), and Carry flag (Cy) can be represented as shown below:
ACCUMULATOR
SS ee ee”
MSN ACy LSN
Carry Auxiliary
bit Carry bit
With the Auxiliary Carry, if the instruction causes a carry out of bit 3 and into
bit 4 of the resulting value, the Auxiliary Carry flag is set; otherwise it is
reset. In the above example, there is no carry out of bit 3 and into bit 4,
so the Auxiliary Carry bit is zero after the operation.
The DAA command finds ACy reset to 0 and LSN = 1101. Because the LSN is greater
than nine, six is added to it and the result is 0011 and ACy set to 1. Because the
MSN is greater than nine, both six and the ACy is added to it to yield a result of
0001. The final decimal adjusted result after the DAA operation is,
i: - 1 33 Decimal number
18-38
to the decimal number, 113. The DAA operation can be written
which is equivalent
as follows:
Carry Auxiliary
bit Carry bit
Thus.woee Soleo.
If you are doing considerable amounts of BCD manipulation, you would be interested
in the yCOM-8 chip in preference to the 8080A. However, such only would be the
case if you require the full speed of the microcomputer. With additional instruc-
tions, the 8080A can easily accomplish the same task of producing a packed BCD
format after a subtraction.
Cycles: 1 0 0 1 1 0 1 0 0
States: 5
Addressing: register Cycles: 3
Flags: Z,S,P,AC States: 10
Addressing: reg. indirect
Flags) EZ.SiPsAG
18-39
The DCR r instruction causes a one to be subtracted from the destination register
D. The destination register can be any of the general purpose registers B, C, D,
E, H, and L; the accumulator A; or M, the contents of memory as addressed by
register pair H,L. Only four of the five flags are affected; the carry flag
remains unchanged.
PUM). Cycles: 1
fla tele [stots ty Cycles: 1
States: 5 States: 5
Addressing: register Addressing: register
Flags: none Flags: none
DAD ©P
According to the NEC Manual: "While the INX and DCS instructions allow incre-
menting and decrementing register pairs, the DAD, Double Add, instruction allows
adding register pairs together. DAD rp causes the register pair specified by
RP to be added to the contents of the HL register pair, with the result remaining
in the HL pair. The Carry Flag is the only status flag affected by the DAD
instruction. The instructions INX, DCX, and DAD allow the calculation of table
lookup." Also used for indexed addressing and file data manipulation.
To quote the COM-8 Software Manual: ''CMP r and CMP M are used to compare two data
quantities without altering them. CMP r compares the contents of the accumulator
with one of the single registers B, C, D, E, H, and L; the accumulator A; or M,
the memory location addressed by the H,L register pair. The instruction does not
9/22/77
13-41]
affect any of the data registers, but affects the four flag bits Carry, Zero,
Sign, and Parity. The compare instructions actually perform an internal sub-
traction of the source S$ from the accumulator. The flags are set on the basis
of what would have been the result of the subtraction. Thus Zero is set if the
quantities were equal, Sign is set if the result was negative (the most
significant bit is logic 1), Parity is set if the result has even parity, and
Carry is set if there is a borrow out of bit 7 (source data greater than
Accumulator data)."
The Compare instructions are best used for unsigned arithmetic comparison (numbers
in the range of 0 to 255,,), also called logical or character comparisons. For
this case, the results for the Zero and Carry flags may be interpreted as follows:
a xX Accumulator = register
xX a Accumulator < register
uf al Accumulator < register
0 0 Accumulator > register
X 0 Accumulator > register
Thus, the relations { = , < , > } may be tested using a single jump instruction,
while { < , > } require two. Note that if the operands are reversed, > replaces
< and < replaces >)"
CP] data
Cycles: 2
States: 7
Addressing: immediate
Flags: 2,S,P,CY,AC
18-42
the contents of
The CPI data instruction is an immediate operation which compares
the accumulator with the 8-bit quantity in the second byte of the instruction.
produce useful
The instruction affects all five flags, but only four of the flags
results. The flags are set or cleared on the basis of what would have been the
result of the subtraction. ‘The contents of the accumulator remain unchanged.
See the preceding discussidn of the CMP r instruction for additional details.
rather than
It can be argued that the CMP r and CPI data instructions are logical
arithmetic operations. In view of the fact that an arithmetic operation--subtractio:
is performed, we would include it in the group of arithmetic operations. The
objective of the compare instructions is to produce decisions that are reflected
in the logic states of the flag bits.
LOGICAL GROUP
Cycles: 1 [ay 0 1 0 Io 1 1 0
States: 4 ir
Addressing: register Cycles: 2
Flags: 2Z,S,P,CY,AC States: 7
Addressing: reg. indirect
Flags: Z,S,P,CY,AC
The ANA r instruction performs a parallel bit-by-bit logical AND of the contents of
accumulator and the contents of the source register S. The source register can
be any of the general purpose registers B, C, D, E, H, and L; the accumulator
A; or M, the contents of the memory location addressed by the register pair H,L.
For example, the ANA B operation performs a bit by bit logic AND operation with
the contents of register B and the contents of the accumulator. The special case ot!
ANA A
clears the Carry Flag and causes the Zero flag to be set if the result
is zero, cleared if the result is not zero. All of the flags are affected by
the ANA r instruction. Since A * A= A, the data in the accumulator is not changed
This is a "trick" to clear the carry flat or simply test for zero in the accumulato
18-43
ANI data
1 | 1 ! 1 | 0 o | ] ine | 0
data
Cycles: 2
States: 7
Addressing: immediate
Flagsaue Zo CYAG
The ANI data instruction performs a bit by bit logical AND of the contents of the
accumulator with the contents of the second byte of the instruction. All flags
are affected by the instruction.
Cycles: 1 ] — ] ea (as ]
[ 0 1 1 0 1 1 0 |
States: 4
Addressing: register
Cycles: 2
Flags: 2Z,S,P,CY,AC
States: 7
Addressing: reg. indirect
Flags: 2Z,S.P.CY,AC
The ORA r instruction performs a parallel bit-by-bit logical OR of the contents of the
accumulator and the contents of the source register S$. The source register can
be any of the general purpose registers B, C, D, E, H, and L; the accumulator A;
or M, the contents of the memory location addressed by the register pair H,L.
The command,
ORA A
which has the octal instruction code 267; is a convenient way to clear the carry
flag without affecting anything else. Both ORA r and a related two-byte instruction,
ORI data, clear the Carry Flag and cause the Zero flag to be set if the result
is zero, cleared if the result is not zero.
18-44
OR] data
data
Cycles: 2
States: 7
Addressing: immediate
Flags: Z,S,P,CY,AC
The ORI data instruction performs a bit by bit logical OR of the contents of the
accumulator with the contents of the second byte of the instruction. All flags
are affected by the instruction.
XR] data
The XRI data instruction performs a bit by bit logical Exclusive-OR of the contents
of the accumulator with the contents of the second byte of the instruction. All
flags are affected by the instruction.
XRI data (Exclusive OR immediate)
18-45
(A) ~— (A) 7 (byte 2)
The content of the second byte of the instruction is
exclusive-OR‘d with the content of the accumulator.
The result is placed in the accumulator. The CY and
AC flags are cleared.
data
Cycles: 2
States: 7
Addressing: immediate
Flags: Z,S,P,CY,AC
To quote the NEC Microcomputers, Inc. uCOM-8 Software Manual: '"'The above logic
instructions will be used to implement a programming technique known as masking.
Masking is a technique by which bits of an operand are selectively modified for
use in a later operation. There are three general types of masking,
The first two approaches are called exclusive maskingand the third approach is
called tnclustve masking. For example, assume that the accumulator contains
the following value,
Bie: (Pate ee eee a)
To test bit 3 for a zero or one and simultaneously clear the other bits, the
accumulator is masked with 00001000. By using the instruction,
ANT
010
the accumulator will contain zeros with the Zero flag set if bit 3 had been a
zero, and it will contain 010, in octal code, with the Zero flag cleared if bit
3 had been one."
"In order to set bit 3 to one and leave the other bits alone, the same bit
pattern is used and the instruction,
ORI
010
"In order to set bit 3 to zero and leave the other bits alone, the accumulator
is ANDed with 1111011, the complement of the mask of the first example. With
the instruction,
ANI
367
the accumulator result is 11010110. These are the most commonly used bit manip-
ulation operations, since masking is accomplished in one step. Many others
18-416
are possible, but they often require more than one instruction for implementation."
ROTATE INSTRUCTIONS
»
RAR:
RRC:
RAL:
RLC:
18-417
RAL (Rotate left through carry) RAR (Rotate right through carry)
(Anti) <= (Ap) a{CY) —— (Az) (An) =— (Ant) ; (CY) ~— (Ag)
(Ag) ~— (CY) (AZ) == (CY)
The content of the accumulator is rotated left one The content of the accumulator is rotated right one
position through the CY flag. The low order bit is set position through the CY flag. The high order bit is set
equal to the CY flag and the CY flag is set to the to the CY flag and the CY flag is set to the value
value shifted out of the high order bit. Only the CY shifted out of the low order bit. Only the CY flag is
flag is affected. affected.
ee
ia Silat
eee:
aed | |
Slike
wie | ey
Cycles: 1 Cycles: 1
States: 4 States: 4
Flags: CY Flags:, CY
The RAL instruction, or Rotate Accumulator Left, causes the accumulator to rotate
all bits one position to the left through the carry bit, i.e., a 9-bit rotate.
Bit 7 transfers to the Carry flag, the Carry bit transfers to bit 0, bit O transfers
to bit 1, bit 1 transfers to bit 2, and so on, as shown on the preceding page.
The RAR instruction, or Rotate Accumulator Right, causes the accumulator to rotate
aul bits one position to the right through the carry bit, i.e., a 9-bit rotate.
Bit 0 transfers to the Carry flag, the Carry bit transfers to bit 7, bit 7
transfers to bit 6, and so on, as shown on the preceding page.
The RLC instruction, or Rotate Left Circular, rotates the accumulator one bit to
the left and into the Carry flag, as shown in the diagram on the preceding page.
The RRC instruction, or Rotate Right Circular, rotates the accumulator one bit to
the right and into the Carry flag, as also shown on the preceding page.
In both of these instructions, the original information appearing in the Carry flag
iselost.
18-48
CMA
[0 0 ! 1 0 | 1 v4 1 1 |
Cycles: 1
States: 4
Flags: none
The CMA instruction complements the contents of the accumulator without affecting
any of the flag bits. For example, if the accumulator contained 11010001, the
CMA
reer 1 1 i 1 i! al
Cycles: 1 .
States: 4 Cycles: 1
Flags: CY States: 4
Frags: CY
The STC instruction sets the Carry flag to logic 1; the CMC instruction complements
the Carry flag. No other flag bits are affected.
BRANCH GROUP
This group of instructions alters normal sequential program flow. Condition flags
are not affected by any tnstruction in thts group. The two types of branch
instructions are unconditional and conditional. Unconditional transfers simply
perform the specified operation on register PC, the program counter. Conditional
transfers examine the status of one of the four process flags--Zero, Sign, Parity,
or Carry--to determine if the specified branch operation is to be executed. The
conditions that may be specified are as follows:
18-49
CONDITION CCC
JMp addr
Main program
1 a 1 0 T 9 | 0 0 i
low-order addr
high-order addr
Cycles: 3
States: 10
Addressing: immediate
Flags: none
Sub — program
The program coumter is the 16-bit register in the 8080A microprocessor chip that
contains the memory address of the next instruction byte that must be executed
in a computer program. The JMP addr instruction is simply a byte transfer instruc-
tion, in which the second and third instruction bytes are transferred directly to
18-50
The behavior of the JMP instruction can be understood with the aid of the diagram
shown on the preceding page. The first JMP instruction, @, is a backwards jump
that creates a loop. JMP@® and JMP@) transfer program control to the sub-progran.
The exit from the sub-program is designated by the JMP @®
instruction.
low-order addr
. high-order addr
Cycles: 5
States:? 17
Addressing: immediate/reg. indirect
Flags: none
Ret (Return)
(PCL) ~— ((SP)),
Subroutine No. |
(PCH) ~— ((SP) + 1).
(SP) ==» (SP) +2:
The content of the memory location whose address
is specified in register SP is moved to the low-order
eight bits of register PC. The content of the memory
location whose address is one more than the content
wD m =f of register SP is moved to the high-order eight bits of
register PC. The content of register SP is incremented
by 2.
Subroutine No. 2 7 <—
peasy ; : Cycles: | 37 = -
States: 10
Addressing: reg. indirect
Flags: none
Rev. 9/22/
18-5]
Many times you may want to branch out of a main program but return to it later.
To do so, you must not only know your new destination, but you must somehow also
remember your original location. To accomplish this, you have two types of
instructions, call subroutine and return from subroutine. Here we shall discuss
the unconditional instructions CALL addr and RET. To quote the NEC Microcomputers,
Inc. manual: "The call instruction transfers control to a subroutine. The
instruction CALL addr saves the incremented program counter on the pushdown
stack and places the address in the program counter. The pushdown stack is a
block of read/write memory addressed by a special 16-bit register known as the
Stack Pointer which can be loaded by the user (LXI SP, data 16). The stack operates
as a last-in-first-out memory (LIFO), with the Stack Pointer register addressing
the most recent entry into the stack. The Return instruction causes the entry at the
top of the stack to be placed into the Program Counter. Thus a CALL instruction
transfers program control from the main program into the subroutine and a RET
instruction transfers control back to the main program."
The location of the stack is usually at the higher memory addresses in the available
memory of an 8080A-based microcomputer. In the diagram below, the stack is some
distance from the main program or subroutines.
Memory address
H (bs
000 O00
interrupt
service
routines
ooo 100
Main
program
OO! 300
Subroutines
003 300
18-52
high-order addr
Cycles: 3
States: 10
Addressing: immediate
Flags: none
The value of CCC that corresponds to each of the conditions has been shown several
pages back. The behavior of two of the conditional instructions, JNZ and JZ, can
be understood with the aid of the diagram below:
In the JNZ instruction, the jump occurs only if the 8-bit result or an arithmetic
or logical operation is Not Zero. The decision symbol,
previous’ instruction
which is used in flowcharting, indicates that what happens next depends upon the
state of the Zero flag. For JNZ, a jump occurs only if the Zero flag is cleared,
i.e., at logic 0. For JZ, a jump occurs if the 8-bit result is equal to zero; in
such a case, the Zero flag is at logic l.
Rees 2s eee:
low-order addr
high-order addr
Gycless c/5
States: 11/17 w«
Addressing: | immediate/reg. indirect
Flags: none
The conditional instructions, CZ, CNZ, RZ, and RNZ are depicted schematically
in the diagrams given below. Remember, Z means that the Zero flag must be at
logic 1 for a call or returm to occur; otherwise, program control passes to the
next instruction. NZ means that the Zero flag must be at logic 0 for a call or
returm to occur; otherwise, program control passes to the next instruction.
Subroutine Subroutine
18-56
ieee CNC te
eee
(oa
ee
Subroutine
1857.
RST 2
RSTn (Restart)
((SP) — 1) ~— (PCH)
((SP) = 2) ~— (PCL)
(SP) ~— (SP) —2
(PC) ~— 8* (NNN)
The high-order eight bits of the next instruction ad-
dress are moved to the memory location whose
address is one less than the content of register SP.
The low-order eight bits of the next instruction ad-
dress are moved to the memory location whose
address is two less than the content of register SP.
The content of register SP is decremented by two,
Control is transferred to the instruction whose ad-
dress is eight times the content of NNN.
"O00
SaaS teat hO) OS SiGe bs AON Sr 22) al
[ofofo o[ofofofolojojnin
Program Counter After Restart
To quote the uCOM-8 Software Manual: "The EI (Enable interrupt) and DI (disable
interrupt) instructions provide control over the acceptance of an interrupt re-
quest. With this control established, the next problem to be resolved is how does
the external device indicate to the processor where the desired interrupt routine
is located. The 8080A accomplishes this identification by allowing the device to
supply one instruction when the interrupt is acknowledged. Although any 8080A
instruction can be specified, only two are of practical value: a Call instruction,
CALL, and a Restart instruction, RST. . . . A RST instruction is actually a spec-
ialized type of CALL. The instruction RST n is a call to one of eight locations
in memory specified by an integer expression in the range, 0 through 7 in octal
code, indicated by N. The locations specified by the integers 0 through 7 are
listed below.
A RST instruction causes the incremented program counter to be pushed onto the
18-58
stack exactly as a CALL instruction does. It then loads the program counter with
HI = 000 and LO = ONO, where N is 0 through 7. Thus, RST 4 causes the program
= 040 to be entered into
counter to be pushed onto the stack .and HI = 000 and LO
the program counter."
.
of interrupt
"Since the 8080A has only eight RST instructions, any additional levels
must be implemented using CALL instructions. This means a CALL addr instruction
to
must be supplied by the interrupting device, which is somewhat more difficult
implement in hardware because CALL is a 3-byte instruction. However, once imple-
mented, a direct call to a routine is slightly faster than a Restart and subsequent
jump operation. Although this is not a major factor, this difference in response
speed should be considered when determing how to implement interrupt service
routines. The primary benefit realized by using the CALL approach is that n-way
interrupt vectoring is achieved in hardware, eliminating the need for software
in low order memory (for RST processing). This frees those memory locations for
use by user programs and removes a constraint from the system memory design."
PCHL =
Cycles: 1 >
States: 5
Addressing: register
Flags: none
The PCHL instruction causes the program counter to be loaded with the contents of
the HL register pair. Program execution then continues at the point designated
by the content of HL. In effect, this is a jump instruction, but since the HL
register pair can be operated upon arithmetically, it allows the implementation
of a variety of calculated jumps. The instruction sequence,
LXI H
<B2>
<B3>
PCHL
is identical in function to
18-59
This group of instructions performs I/0, manipulates the Stack, and alters
internal control flags. Unless otherwise specified, condition flags are not
affected by any instructions in this group.
To quote the yCOM-8 Software Manual: '"TIwo special instructions enable program-
mers to save and restore the registers using the stack, PUSH and POP. PUSH rp
causes the register pair specified by RP to be placed at the top of the stack.
The stack is a special portion of read/write memory designated by the user and
treated as a last-in-first-out (LIFO) memory through the use of a 16-bit Stack
Pointer. A PUSH operation causes the Stack Pointer to decrement by one and store
the most significant register (the HI register) in memory at this new location
specified by the Stack Pointer. The Stack Pointer is then decremented again and
the least significant register (the LO register) is then stored in memory at that
address. For a POP operation, the data at the memory location addressed by the
Stack Pointer is moved into the least significant register (the LO register, which
can be C, E, or L); the Stack Pointer is incremented and the data at the new memory
location is loaded into the most significant register (the HI register, which can
be B, D, or H). The Stack Pointer is then incremented again."
"For both PUSH and POP operations, the register pair, RP, may be one of the three
double registers BC, DE, or HL (identified as B, D, and H, respectively) or the
contents of the Flag register and the Accumulator, indicated by PSW (which stands
for program status word)."
The PUSH and POP instructions are represented schematically in the figure on the
following page. In this diagram, SP is the original stack pointer location before
the PUSH or POP instruction.
18-60
Accumulator
Flags
HUEY
HUW
A
Or
A
Sy
18-61
PUSH PSW (Push processor status word) POP PSW (Pop processor status word)
((SP) — 1) ~— (A) (CY) ~— ((SP))o
(SP) 2) =< (CV) SR) = 2)q =< 1 (P) ~— ((SP))o
(S23) =A =), US) Ale) Se (AC) ~=— ((SP))q4
((SP) — 2)4 ~— (AC) , ((SP) —2)5 =— 0 (Z) =— ((SP))g
((SP) — 2)g ~— (Z), ((SP)—2)7 ~<— (S (SSSR 7,
(S23) == (S12) = (A) ~— ((SP) + 1)
The content of register A is moved to the memory (SP) ital (SP) i
location whose address is one less than register SP. The content of the memory location whose address
The contents of the condition flags are assembled is specified by the content of register SP is used to
into a processor status word and the word is moved restore the condition flags. The content of the rnem-
to the memory location whose address is two less ory location whose address is one more than the
than the content of register SP. The content of reg- content of register SP is moved to register A. The
ister SP is decremented by two. content of register SP is incremented by 2.
oe ie a ey rg (a Oy olen es
Cycles: 3 Cycles: 3
States: 11 States: 10
Addressing: reg. indirect Addressing: reg. indirect
Flags: none , Flags: 2,S,P:CY_AC
FLAG WORD
The letters, PSW, stand for processor status word, which is the contents of the
accumulator and the five status flags. We refer you to the description of the
PUSH rp and POP rp instructions on the preceding pages. The flag register, F,
is regarded as the most significant register and the accumulator, A, is regarded
as the least significant register. The program status word is important because
it save the actual machine status as determined by the five flag bits. When it
is restored, machine operation can resume in the correct state, regardless of
how the subroutine which interrupted affected the flags.
The stack pointer originally was located at HI = 003 and LO = 303. After the
CALL subroutine instruction, the two program counter bytes are pushed onto the
stack and the stack pointer moves to HI = 003 and LO = 301. ‘Note that the HI
program counter byte goes on the stack first, but comes off the stack last.
A succession of four PUSH instructions load the stack with the contents of the
six general purpose regster, the accumulator, and the flag register. After all
of this, stack pointer (SP) location is HI - 003 and LO = 271, the top
filled location on the stack.
Once the subroutine has been executed, there is the problem of removing the
contents of the stack and placing them back into the 8080A microprocessor chip.
The section of code, located at the end of the subroutine, that accomplishes this is
POP PSW
POP H
POP D
POPSB
RET
In each case, the LO byte comes off the stack first. Recall that in three-byte
instructions, the LO byte is always the second byte of the instruction. Thus,
the 8080A chip is consistent in its handling of 16-bit address words. Once the
contents of the stack have been popped off, the stack pointer resumes its original
location of HI = 003 and LO = 303. s
Registers can be pushed and popped in any order. However, the program counter is
almost always pushed first and popped last. The caution that *you must observe is
that you must pop registers in the reverse order with which you pushed them. For
example, with the stack configuration shown on the following page, if you executed
the following section of code at the end of the subroutine,
POP PSW
POP B
POP H
POP D
RET
you would encounter problems with the execution of the main program. The original
register contents would not be returned to their original locations. The chip woulc
attempt to execute the program, but there is not much chance of a useful result.
If you do not need to push registers on a stack during a subroutine call, do not
do so. Store only that information on the stack which is needed by the 8080A chip
when it resumes the main program.
18-43
Top of stack
SP 003 27\
003 (Ape) L
Register
rene
003 274
om
003 275
003 276
003 “ATBTL
003 300
Program Counter
003 301 (LO byte)
Program Counter
003 302 (H| byte)
003 304
003 305
003 306
The Stack
XTHL
Cycles: 5
States: 18
Addressing: reg. indirect
Flags: none
The XTHL instruction is used to exchange the contents of the HL register pair
with the top pair of items on the Stack. The contents of the top location, the
one addressed by the stack pointer SP,are exchanged with the contents of register
L. The stack pointer is incremented, and the cottents of memory addressed by this
new value of SP, are exchanged with the contents of register H.
SPHL
SPHL (Move HL to SP)
(SP) ~— (H) (L) ‘
The contents of registers H and L (16 bits) are moved
to register SP. 3
a as i sae ie Cp oe
Cycles: 1 ¥
States: 5
Addressing: register
Flags: none
The SPHL instruction is used to load the stack pointer register with the contents
of the register pair H,L. The contents of L are placed in the LO eight bits of
the stack pointer, and the contents of H are placed in the HI eight bits of the
stack pointer. As pointed out in the NEC Microcomputers, Inc. manual: "The SPHL
instruction can be used to load the stack pointer with a value which has been
computed using the double resgier arithmetic operations available with the HL
register pair. This should always be done with care, since it is easy to lose
track of where the stack pointer is pointing, with subsequent loss of stack conten
OUT port
The OUT port instruction moves the 8-bit contents of the accumulator to the output
port specified by the second byte of the instruction. Two hundred and fifty-six
18-65
unique output ports can be selected. During the third machine cycle of the instruc-
tion, the device code appears on the address bus, an OUT control pulse is generated,
and the contents of the accumulator appear on the external bidirectional data bus.
1 1 To Ta To Le ae.
port
Cycles: 3
States: 10
Addressing: direct
Flags: none
IN port
IN port (Input)
(A) ~<— (data)
The data placed on the eight bit bi-directional data
bus by the specified port is moved to register A.
Cycles: 3
States: 10
Addressing: direct
Flags: none
The IN port instruction permits the 8080A chip to read the data present at the
input port given by the second byte of the instruction. Two hundred and fifty-six
unique input ports can be addressed. During the third machine cycle of the
instruction, the device code for the input device appears on the address bus, an
IN control signal appears on the control bus, and information appearing on the
bidirectional data bus also appears in the accumulator.
EI and Dp]
Cycles: 1 Cycles: 1
States: 4 States: 4
Flags: none Flags: none
18-66
HLT ~
HLT (Halt)
The processor is stopped. The registers and flags are
unaffected.
Lc a! een ee og
iGyclesy 91 %
States: 7
Flags: none
?
.
The HLT instruction causes the processor to suspend operation until the 8080A
chip receives a RESET signal or receives an interrupt request signal (INT). The
processor accepts the INT request regardless of the condition of the internal
interrupt flip-flop. After processing the interrupt, instruction execution
continues at the next location after the Halt command.
NOP
0 o fo alo ls 0 0
Cycles: 1
States: 4
Flags: none
18-67
The NOP instruction does absolutely nothing except consume a location in memory
and take up four states during program execution. It is used for program
debugging, in which extra NOP instructions are placed in a program for
subsequent
modification. When deletions are made to a program, NOPs should be inserted in
their
place.
HE
With the aid of material in the Intel 8080 Microcomputer Systems User's Manual
and the NEC Microcomputers, Inc. wCOM-8 Software Manual, we have provided a
detailed description of the individual instructions of the 8080A microprocessor
chip. We are grateful to both the Intel Corporation and NEC Microcomputers, Inc.
for their kind permission to let us use information in their manuals. If you
are a serious user of the 8080A chip, you should have both manuals in your possession.
18-68
INSTRUCTION SET
NOTES: 1. DDD or SSS — 000 B — 001 C — 010 D — 011 E — 100 H — 101 L— 110 Memory — 111 A.
2. Two possible cycle times, (5/11) indicate instruction cycles dependent on condition flags.
4-15
18-€9
INTRODUCTION TO THE EXPERIMENTS
The following experiments provide a number of interesting programs that you may
need if you are working with digital instrumentation.
EXPERIMENT NO. 1
PURPOSE
The purpose of this experiment is to load and execute a BCD Input and Direct
Conversion to Binary Routine, No. 80-147 in‘the Intel Microcomputer User's
Library. ‘The program was developed by M. H. Gansler.
PROGRAM
LO Memory Instruction
address byte Mnemonic Description
004 O17 017 Mask ‘byte that masks out the most
significant BCD digit
010 360 360 Mask byte that masks out the least
significant BCD digit
DISCUSSION
The program starts with the two-digit BCD number in the accumulator. The program
can be a subroutine; substitute a RET instruction for the HLT instruction at
memory address LO = 023. The above program can be located anywhere in memory.
We located the origin of the program at HI = 003 and LO = 000.
step 1
Load and execute the above program for the two-digit decimal number 56. The
BCD equivalent is 01010110, or 56 in hexadecimal and 126 in octal. What binary
number do you observe?
STEP 2
Change the BCD number at memory address HI = 003 and LO = 001 to the numbers given
in the table below. Compare your results with the results that we observed.
1 00000001
10 00001010
20 00010100
50 00110010
iss 01001011
80 01010000
90 01011010
99 01100011
EXPERIMENT NO, 2
PURPOSE
The purpose of this experimeat is to load and execute a 16-digit BCD addition
subroutine, in which two BCD numbers are added together to produce a result
that is less than or equal to 9,999,999,999,999,999. This program is listed
and described in considerable detail in the uCOM-8 Software Manual and is
given here courtesy of NEC Microcomputers, Inc. The program is started at
memory location HI = 003 and LO = 024,
PROGRAM
LO memory Instruction
address byte Mnemonic Description
ADD16: 032 365 PUSH PSW Push the program status word onto the
stack [NOTE: Make certain that you
have loaded the stack pointer before
you execute this program.]
LOOP2: 037 032 LDAX D Load the accumulator from the memory
location addressed by register pair
D,E
DONE2: 054 Z1 ' POP B Pop contents of register pair B,C off of
stack
055 1 POP PSW Pop the program status word off of stack
DISCUSSION
This program starts with a 16-digit BCD augend in LO memory addresses 340 through
347, with the least significant BCD digit in location 347 and the most significant
BCD digit in location 340. The 16-digit BCD addend is initially in LO memory
addresses 350 through 357, with the least significant BCD digit in location 357 and
the most significant BCD digit in location 350. The terms, gddend and augend, are
defined as follows:2
Program execution starts at HI = 003 and LO = 024. The sum replaces the augend.
step 1
Load the above program into memory. Load the augend, 1,000,000,000,000,099, and
the addend, 8,000,000,000,000,001, into memory. Execute the program. What is
the sum, which appears starting at LO memory address 340? NOTE: Don't forget to
add a three-byte LXI SP instructton, perhaps at HI = 008 and LO = 021, to set
the stack potnter tf you are not using a MMD-1 microcomputer.
Rev. 9/22/77
18-75
STEP 2
Add the following BCD numbers and compare your results with those that we observed.
STEP 3
Change the byte at LO = 035 to ((2, which corresponds to the addition of two
four-digit BCD numbers. Perform the following additions:
EXPERIMENT NO, 3
PURPOSE
The purpose of this experiment is to load and execute a Binary to BCD Subroutine,
No. 80-67 in the Intel Microcomputer User's Library. The program was developed
by Niels S.+Gundestrup of the Geophysical Isotope Laboratory in Denmark.
LO memory Instruction
address byte Mnemonic Description
BNBCD: 230 365 PUSH PSW Push contents of program status word on
stack
?
Rev. 9/22/77
Loe
DISCUSSION
This program starts with a 16-bit binary number in register pair D,E. The number
is converted into a five BCD digit number that is stored starting at HI = 003
and LO = 340. The most significant BCD digit is stored at this location, and
the remaining four digits in subsequent locations. The least significant BCD digit
is stored at LO = 344. The program BNBCD starts at HI = 003 and LO = 230; however,
the 16-bit binary number must exist in register pair D, and the location of the
most significant digit in register pair H. We have used LXI instructions to set
this information in the registers before BNBCD is executed.
The output can either be as decimal numerals or as 8-bit ASCII code, with the most
significant bit (the parity bit) at logic 1. A slight error in the original
program has been corrected to permit the LSD to be stored in ASCII code.
18-79
The original contribution to the Intel User's library is shown on the following
pages. Note the style of the cross-assembled program, the program comments
(which follow the semi-colon on each line), and the fact that both the memory
addresses and the instruction bytes are listed in hexadecimal code. This listing
gives you important clues concerning the operation of the program.
step 1
Load the program into memory. Set the bytes at LO = 267 and LO = 277 to 000.
Load 377 into both LO = 223 and LO = 224. These two instruction bytes correspond
to the 16-bit binary number, 1111111111111111, which has a decimal value of
65,535. If you are not using a MMD-1 microcomputer, remember to set the stack pointer.
STEP 2
Execute the program. Reset the microcomputer and determine the contents of
memory locations LO = 240 through LO = 244. What sequence of decimal numbers do
you observe in these locations?
We observed 6 5 5 3 5, as expected.
STEP 3
Determine the five-digit BCD equivalent of the following 16-bit binary numbers,
which should be loaded at memory locations LO = 223 and LO = 224 before you
execute the program. Check your results with ours.
Rev. 9/22/77
18-8) step 4
A program to convert a 16-bit binary word to a 5 digit BCD number is quite useful.
Given below is a hexadecimal listing of a program that starts at HI = 001 and
LO = 000. We have loaded it into EPROM and can use it as a subroutine.
2. Type God
BCD in 1001-1005,
PROM EQU @
RAM EQU NOT PROM
STPNT EQU 10FFH
ORG 50H
31FF19 LXI SP»STPNT
219110 LXI Hs1@Q1H
CDOG01 CALL BNBCD ~
CF RST 1 x
C3560 JMP $-4
ORG 10@H
Q_9Z
Q7-OD
On the following five pages, we provide an extensive listing of the 256 instruction
codes in the 8080 microprocessor instruction set. This listing provides the
following information:
You may wish to make a Xerox or IBM copy of this listing and keep it handy. We
have found the listing to be of particular value when we attempt to convert
an octal listing into hexadecimal, or vice versa.
000 00 No operation
ool Ol <B2> <B3> Load immediate into register pair B and C
002 02 Store A indirect into M addressed by B and C
003 03 Increment contents of register pair B and C by 1
004 04 Increment register B by 1
005 05 Decrement register B by 1
006 06 <B2> Move immediate into register B
007 07 Rotate A left
010 08
O11 09 Add contents of B,C to H,L and store in H,L
012 OA Load A indirect from M addressed by B and C
013 OB Decrement contents of register pair B and C by-1
014 0c Increment register C by 1
015 OD Decrement register C by l
016 OE <B2> Move immediate into register C
017 OF Rotate A right
020 10
021 it <B2> <B3> Load immediate into register pair D and E
022 12 Store A indirect into M addressed by D and E
023 13 Increment contents of register pair D and E by 1
024 14 Increment register D by 1
025 aS Decrement register D by l
026 16 <B2> Move immediate into register D
027 ily) Rotate A left through carry
030 18
031 19 Add contents of D,E to H,L and store in H,L
032 1A Load A indirect from M addressed by D and E
033 1B Decrement contents of register pair D and E by 1
034 1¢ Increment register E by 1
035 1D Decrement register E by l
036 1E <B2> Move immediate into register E
037 1F Rotate A right through carry
040 20
041 Pal <B2> <B3> Load immediate into register pair H and L
042 22 <B2> <B3> Store L and H into M and Mtl, where M = <B2> <B3>
043 23 Increment contents ofs register pair H and L by 1
044 24 Increment register H by l
045 25 Decrement register H by 1
046 26 <B2> Move immediate into registerH
047 27 Decimal adjust A
050 28
051 29 DAD H Add contents of H,L to H,L and store in H,L
052 2A LHLD <B2> <B3> Load L and H with contents of M and Mtl, respective
053 2B DCX H Decrement contents of register pair H and L by 1
054 2C INR L Increment register L by l
055 2D DCR L Decrement register L by l
056 2E MVI L <B2> Move immediate into register L
057 2F CMA Complement A
060 30
061 SH LXI SP <B2> <B3> Load immediate into stack pointer
062 32 STA <B2> <B3> Store A direct into M addressed by <B2> <B3>
063 38 INX SP Increment register SP by l
064 34 INR M Increment contents of M by 1
065 35 DCR M Decrement contents of M by 1
066 36 MVI M <B2> Move immediate into M addressed by H and L
067 37, STC Set carry flip-flop to logic 1
<Bl> 0_9
OCTAL HEX MNEMONIC DESCRIPTION sie
070 38 --- =o
071 39 DAD SP Add stack pointer contents to H,L and store in H,L
072 3A LDA <B2> <B3> Load A direct with contents of M addressed by <B2> <B3>
073 3B DCX SP Decrement register SP by 1
074 3C INR A Increment register A by 1
075 3D DCR A Decrement register A by 1
076 3E MVI A <B2> Move immediate into register A
077 3F CMC Complement carry flip-flop
100 40 MOV B,B Move contents of register B to register B
101 41 MOV B,C Move contents of register C to register B
102 42 MOV B,D Move contents of register D to register B
103 43 MOV B,E Move contents of register E to register B
104 44 MOV B,H Move contents of register H to register B
105 45 MOV B,L Move contents of register L to register B
106 46 MOV B,M Move contents of M to register B
107 47 MOV B,A Move contents of register A to register B
110 48 MOV C,B Move contents of register B to register C
Tay 49 MOV C,C Move contents of register C to register C
112 4A MOV C,D Move contents of register D to register C
Ada is} 4B MOV C,E Move contents of register E to register C
114 4C MOV C,H Move contents of register H to register C
TS 4D MOV C,L Move contents of register L to register C
116 4E MOV C,M Move contents of M to register C
ey 4F MOV C,A Move contents of register A to register C
120 50 MOV D,B Move contents of register B to register D
LPAI oy MOV D,C Move contents of register C to register D
122 52 MOV D,D Move contents of register D to register D
123 53 MOV D,E Move contents of register E to register D
124 54 MOV D,H Move contents of register H to register D
125 55 MOV D,L Move contents of register L to register D
126 56 MOV D,M Move contents of M to register D
27 57 MOV D,A Move contents of register A to register D
130 58 MOV E,B Move contents of register B to register E
137. 59 MOV E,C Move contents of register C to register E
132 5A MOV E,D Move contents of register D to register E
133 5B MOV E,E Move contents of register E to register E
134 5G MOV E,H Move contents of register H to register E
135 5D MOV E,L Move contents of register L to register E
136 5E MOV E,M Move contents of M to register E
137 5F MOV E,A Move contents of register A to register E
140 60 MOV H,B Move contents of register B to register H
141 61 MOV H,C Move contents of register C to register H
142 62 MOV H,D Move contents of register D to register H
143 63 MOV H,E Move contents of register E to register H
144 64 MOV H,H Move contents of register H to register H
145 65 MOV H,L Move contents of register L to register H
146 66 MOV H,M Move contents of M to register H
147 67 MOV H,A Move contents of register A to register H
150 68 MOV L,B Move contents of register B to register L
yl 69 MOV L,C Move contents of register C to register L
152 6A MOV L,D Move contents of register D to register L
153 6B MOV L,E Move contents of register E to register L
154 6C MOV L,H Move contents of register H to register L
155 6D MOV L,L Move contents of register L to register L
156 6E MOV L,M Move contents of M to register L
157 6F MOV L,A Move contents of register A to register L
18-86 <B1>
OCTAL HEX DESCRIPTION
SINGLE-BYTE INSTRUCTIONS
TWO-BYTE INSTRUCTIONS
ADL <B2> 306 IN <B2> 333 MVI B_ <B2> 006
ACI <B2> 316 OUT <B2> B23 MVI C <B2> 016
SUI <B2> 326 MVI D <B2> 026
SBI <B2> 336 ; MVI E <B2> 036
ANI <B2> 346 MVI H <B2> 046
XRI <B2> 356 MVI L <B2> 056
ORI <B2> 366 MVI M <B2> 066
CP <B2> 376 MVI A <B2> 076
THREE-BYTE INSTRUCTIONS
JNZ <B2> <B3> 302 CNZ <B2> <B3> 304 LXI B <B2 <B3> 001
JZ <B2> <B3> 312 cZ <B2> <B3> 314 LXI D <B2 <B3> 021
JNC <B2> <B3> 322 CNC <B2> <B3> 324 Lx ne <B2) <Bs> 041
ate <B2> <B3> B32 CE <B2> <B3> 334 LXI SP <B2 <B3> 061
JPO <B2> <B3> 342 CPO <B2> <B3> 344
JPE <B2> <B3> 352 CPE <B2> <B3> 354 STA <B2> <B3> 062
JP <B2> <B3> 362 CP <B2> <B3> 364 LDA <B2> <B3> 072
JM <B2> <B3> Shiv CM <B2> <B3> 374 SHLD <B2> <B3> 042
JMP <B2> <B3> 303 CALL <B2> <B3> 315 LHLD <B2> <B3> 052
REVIEW
The following questions will help you review the 8080A instruction set.
1. Which flags do the following instructions influence when they are executed.
Use the following abbreviations: Zero flag = Z; Carry flag = C; Parity flag = P;
Sign flag = S; and Auxiliary Carry flag = AC.
a. JMP
b POP B
ce. INX D
d. STAX D
e. RSTn
if LXI SP
g RET
h. SHLD
i. LHLD
j. DAA ©
k EI
1. XTHL
m. PCHL
n. DAD B i
o. CMC ;
De CMP Rts.
2. The stack pointer is initially HI = 004 and LO = 000. You call a subroutine
and then execute the following instructions in the order given:
PUSH D
PUSH H
PUSH PSW
PUSH B
At what memory locations in the stack do the contents of the internal registers
appear? Answer this question for each register.
3. What instructions can you use to control the location of the stack?
List them.
byte vs bit
byte vs word
jump vs call
PUSH vs POP
accumulator vs ALU
increment vs decrement
increment vs ADD
IN vs OUT instructions
EL vs DI instructions
carry vs borrow
1. a. none
b. none
c. none (this is very important)
d. none es
e. mone
f. none*
g. none
hy “none
i. none
j. all flags affected
k. none
1. none
m. none
n. Carry flag only
©, Carry flag only
p. all flags affected
De LO address Contents
byte (register)
In addition, all POP, PUSH, subroutine call, and subroutine return instructions
influence the location of the stack. i:
4, a. In the 8080A chip, a register is one of the general purpose registers (8 bits)
or the accumulator. A register pair is a 16-bit register that is treated
as a unit and consists of two general purpose registers, such as B and C, or
D and E.
b. These days, one byte consists of eight bits. A bit is a single binary decision
c. A byte is a sequence of adjacent binary digits operated upon a unit but
usually shorter than a computer word, which may consist of two or more
bytes.
d. A memory address is a sequence of adjacent binary digits that define a
single memory location. A word is a sequence of binary digits that are
treated as a unit, and may represent data, instructions, or other binary
quantities besides memory addresses.
e. In an 8080A microcomputer, the HI address byte is the eight most significant
bits in the 16-bit memory address word; the LO address byte is the eight
least significant bits.
f. Both are branch instructions. However, in a call instruction, the contents
of the program counter are saved before the instruction is executed. In
a jump instruction, the program counter is ignored.
13-93
Both refer to branch instructions in the 8080A instruction set. In a
conditional branch instruction, whether or not the branch occurs depends
upon the logic state of the selected flag. An unconditional branch
instruction ignores the logic states of all flags.
For an OR gate, when both inputs are at logic 1, the output is also logic l.
For an Exclusive-OR gate, when both inputs are at logic 1, the output is
at logic 0. In other respects, the two gates are the same in their logic
characteristics.
The zero flag is set only when the result of an arithmetic/logical instruction
is zero. The sign flag refers to the logic state of the most significant
bit in the result, not to the total word or byte. The flags refer to
different things.
The carry flag refers to a carry out of the most significant bit in an
8-bit result in the 8080A microprocessor. The auxiliary carry flag
refers to a carry out of bit D3 (the fourth bit) in the result.
A PUSH instruction adds two bytes to the stack and decrements the stack
pointer. A POP instruction removes two bytes from the stack and increments
the stack pointer.
The accumulator is a single register in the arithmetic-logic unit (ALU),
which contains other digital circuitry required for performing arithmetic
and logic operations.
The data byte never gets loaded in the program counter. An address byte
does.
Octal code is an eight-state code. Hexadecimal code is a sixteen-state
binary code. The first eight states of the two codes are identical.
To increment means to increase by one. To decrement means to decrease by one.
To increment means to increase only by one. In an ADD operation, the addend
is limited by the byte or word length; it is not limited to unit.
The IN instruction inputs data from an external device into the accumulator.
The OUT instruction outputs data from the accumulator to an external device.
The ADC instruction is an ADD instruction in which you also add the contents
of the carry flag.
The byte being transferred in a MVI instruction is contained within the
program as the second byte of the instruction. The byte being transferred
in a MOV instruction is originally present in a register or in a specific
memory location.
The MVI instruction transfers one program byte to one register. The LXI
instruction transfers a pair of program bytes to a register pair,
The EI instruction enables the interrupt flag and permits the 8080A chip
to be interrupted. The DI instruction disables the interrupt flag and
prevents the 8080A chip from being interrupted.
Both instructions clear the accumulator and the carry flag.
Both refer to the logic state of the carry flag, but carry refers to the
state of the flag after an addition operation whereas borrow refers to the
flag after a subtraction operation.
Machine code is represented as binary, octal, or hexadecimal digits.
Mnemonic code is represented as alphanumeric characters, usually alphabetic
characters. Mnemonic code is easier to remember, but must be converted into
machine code before it can be executed by a microcomputer.
The H register pair serves as a pointer address for all instructions that refer
directly to memory location M. Though the B register pair can serve as a
memory address, it has fewer instructions associated with it when it is used
as a pointer address. ADD M, SUB M, INR M, DCR M, XRA M, ORA M, CMP M, etc.
are some of the instructions that employ the H register pair as a pointer address.
The instruction register stores the 8-bit operation code in an 8080A chip.
The instruction decoder decodes this 8-bit quantity into a series of actions.
13-94 MICROCOMPUTER USER’S
= | LIBRARY SUBMITTAL FORM
intel 4004 4040 8008 8080 CL 3000 (use additional sheets if necessary)
4
Program
Title
Function
Required
Hardware
Required
Software
Input
Parameters ~
Output
Results
98-034C
Courtesy of the Intel Corporation, Santa Clara, California 95051
13-95
INSTRUCTIONS FOR PROGRAM SUBMITTAL TO MCS USER’S LIBRARY
2. A source listing of the program must be included. This should be the output listing of a compile or assembly,
Extra information such as symbol table or code dumps is not necessary.
a: A test program which assures the validity of the contributed program must be included. This is for the user’s
verification after he has transcribed and assembled the program in question.
4. A source paper tape of the contributed program is required. This insures that a clear, original copy ofthe
program is available to photo-copy for publication in a User’s Library update publication.
Intel Corporation
User's Library
Microcomputer Systems
3065 Bowers Avenue
Santa Clara, California 95051
MCS877-475-2K ; , 3
4 Courtesy of the Intel Corporation, Santa Clara, California 95051
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19-1
UNIT NUMBER 19
INTRODUCT
ION
OBJECTIVES
A digital bus is a path over which digital information is transferred, from any
of several sources to any of several destinations. Only one transfer of infor-
mation can take place at any one time. While such a transfer is taking place,
all other sources that are tied to the bus must be disabled. The verb, to bus,
means to interconnect several digital devices, which either receive or transmit
digital information, by a common set of conducting paths, called a bus, over
which all information between such devices is transferred.
THREE-STATE BUSSING
In a bus system, the optimum gate should have two digital output states (logic 0
and logic 1) and a third disconnected or isolated state. That such should be the
case can be easily seen from the following truth table:
Input Gating 4
data signal Output *
0 enable 0
7 enable 1 at
0 disable Disconnected from bus
il disable Disconnected from bus
In other words, the third stateis a condition in which the gate is "disconnected"
fromthe bus~and no input data appears on the bus—fvrom-thte Spectfie gate.
The solution pioneered by National Semiconductor Corporation is the rri-sTate ©,
or three-state, output. It is appropriate to quote from their catalogue, "Digital
Integrated Circuits," a description of the TRI-STATE concept:
"This unique TRI-STATE concept allows outputs to be tied together and then
connected to a common bus line. Normal TTL outputs cannot be connected
owing to the low-impedance logical "1" output current which one device
would have to sink from the other. If however on all but one of the
connected devices both the upper and lower output transistors are turned
off, then the one remaining device in the normal low impedance state
will have to supply to or sink from the other devices only a small amount
of leakage currents. =... “
"Tt is possible to connect as many as 128 devices to a common bus line and
still have adequate drive capability to allow fan-out from the bus."
To summarize the above, a TRI-STATE device has three possible output Statesmen 1G)
N fogical “O" state, (2) A logical "I" state, and (3) A high impedance output state
that is, in effect, disconnected from the bus line. All three-state devices
have an input pin called an enable/disable input, which permits the logic devices
either to behave normally or to exist in the high impedance state. When
a TRI-STATE
enabled, a TRI-STATE device behaves as a normal TTL device; when disabled,
device behaves as if it is, in effect, disconnected from the circuit.
enable 0 X = irrelevant
if enable i
xX disable High impedance
enable /disable
input
In Figure 19-2, we show a simple four-device one-line bus system that is based
upon the use of a single 74126 three-state buffer chip. We recognize the circuit
as a bus system since the outputs of gates A through*D are connected together.
With standard 7400-series TTL chips, it is not possible to do so unless the chips
have special output circuits, either three-state or open collector, that permit
bussing.
DCBA
Figure 19-2. A simple four-device one-line bus based ‘upon the use of four 74126
three-state buffers.
2
“
If we assume that gates A through D in Figure 19-2 are enabled by a logic 1 input,
the operation of the circuit should be clear. Only one buffer gate may be enabled
at any instant of time; the reamining buffer gates must be disabled. Thus, digital
information from only one of the four buffers appears on the single-line bus at
any give instant of time. Information from the remaining three buffers is blocked
since the corresponding buffers are disabled. The following truth table applies
to the operation of this circuit:
Output Comments
"illegal" for thts ctreutt sinee they permit information from more than one buffer
to appear on the stngle-line bus. In addition, tf you attempt to implement any of
these "illegal" tnput conditions, you will most likely burn out the three-state
chip!
Typical bus systems consist of multi-line busses, as shown in Figure 19-3, rather
than single-line busses. Other than the fact that the gating inputs enable or
disable four buffer gates at a time, this circuit is identical to that shown in
Figure 19-2. For example, the truth table is essentially the same:
As was previously the case, all other input conditions are "illegal" since they
permit information from more than one device to appear on the bus.
To digital device
enable/disable
input
The pin configuration for a 74125 chip, as given in the Texas Instruments Incorporate
"The TTL Data Book for Design Engineers," is shown below:
2 2A 2¥ GND
74125
8093
2 3 5 6 9 8 12 i
l 4 10 13
Based upon our experience, we recommend the use of this chip in preference to the
74126. When an enable/disable input is not connected, the corresponding 74125
buffer is disabled.
19-7
The pin configuration for the 74126 three-state quad buffer chip is shown below:
The power inputs are at pins 7 and 14, and there are four independent buffers on
the chip,
The 8095 three-state hex buffer chip contains six buffers that are enabled simul-
taneously from the output of a 2-input NOR gate. The truth table and pin config-
uration are:
8095
e
Currently, the dominant bussing technology, that which is used in most microprocessor
chips, is three-state. A very common circuit configuration that is found within
microprocessor chips is the three-state latch/buffer, which is shown in Figure
19-4. It consists of a 7475 D-type latch and a three-state output buffer that
requires a logic 1 enable input. The following truth table applies:
Enable —
Data a
three state
output buffer.
Clock
CLR
Many of the new programmable interface chips, such as the Intel Corporation 8251,
8253, 8255, 8257, and 8259 employ the three-state latch/buffer circuit in 8-bit
internal programmable registers.
Rev. 9/22/77
Ie
Although several chips in the 7400-series, including the 74125, 74126, and 74200,
have three-state outputs, most of the three-state devices are available from
National Semiconductor Corporation, with second sourcing by Texas Instruments and
others. Given below is a partial listing of the TRI-STATE devices that are
available. Note that TRI-STATE is a registered trademark of National Semiconductor.
Many of the above chips are available from James Electronics, 1021 Howard Avenue,
San Carlos, California 94070.
19-10
INTRODUCTION TO THE EXPERIMENTS
PURPOSE
The purpose of this experiment is to demonstrate the operation of a single 74125
bus buffer with three-state output.
Voc 4c
ae nfo] {+L a]
Vesetarssch cal) MSS
ie ae Seti | | UP
LOGIC LAMP
SWITCHES MONITORS
A
PULSER
step 1
Wire the circuit shown. The 74125 chip contains four independent bus buffers.
You will use only one of them.
STEP 2
Set logic switch A to a logic 1 state. Apply power to the breadboard. Is the
lamp monitor lit or unlit?
eZ
The lamp monitor is unlit, which indicates that the buffer is disabled or burned out.
STEP 3
Now press the pulser button in. Does the lamp monitor become lit?
STEP 4
With the pulser pressed in, vary the logic switch setting between logic 1 and logic
0. What do you observe on the lamp monitor?
~,
The lamp monitor indicates the state of the logic switch as long as the buffer
is enabled.
STEP 5
Is the truth table given below the correct one for the operation of the 74125
buffer? If not, write the correct truth table.
PURPOSE
The purpose of this experiment is to bus four different sources of data onto a
single-line bus.
ab el ma shies
i eee ie
U Pores
1c 1A ny 2c 2A 2Yv GND
74125
8093
LAMP
MONITORS
74l258
SWITCHES
19-14
sTeP 1
Wire the circuit shown. What is the purpose of the 7442 decoder chip?
The purpose of the 7442 chip in the circuit is to enable only one buffer at a
time.
STEP 2
Select in turn output channels 0, 1, 2, and 3 from the 7442 decoder and write
down what you observe the lamp monitor output to be in each case.
STEP 3 ~ >
What occurs when you choose channels 4 through 9 on the 7442 chip? Do you observe
any lamp monitor output?
We observed that the lamp monitor output remained at logic 0. The reason was that
all four 74125 buffers were disabled.
Keep in mind that in any three-state bus system, only a single data input to the
bus must be enabled at any given tnstant of time. In this experiment, the 7442
decoder ensures the fact that only one 74125 buffer is enabled at a time. The
use of decoders for such a purpose is common in three-state bus systems.
19-15
EXPERIMENT NO, 3
PURPOSE
Wie ge 3
IneoRI Wien Span fog. eerons oa 0G
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wL_faLfelLfu] fr
step 1
Study the circuit diagram carefully. Observe that two 74126 buffer chips are
required. The enagle/disable inputs from each chip are tied either to the "0"
or "1" output on a single pulser. Why is only a single pulser used?
To ensure the fact that only one input device is enabled at any given instant of
time.
STEP 2
Wire the circuit and then apply power to the breadboard. Which counter, the 7490
decade counter or the 7493 binary counter, is enabled?
The 7490 decade counter is enabled, since a logic 1 enable input is required to
enable the 74126 buffers.
doe)
SCHEMATIC DIAGRAM OF CIRCUIT
+5V GND
741268
2
PS
ae
D
Cc 7-SEGMENT
DISPLAY
DUAL
PULSER
STEP 3
Press the pulser button in. Which counter is now enabled?
The 7493 binary counter. Is there any possible way in which both counters can
be simultaneously enabled in the above circuit?
19-17
EXPERIMENT NO, 4
PURPOSE
The purpose of this experiment is to test a simple latch/buffer circuit based
upon a 7475 D-type latch and a 74125 three-state buffer.
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LOGIC
SWITCHES A
LAMP
MONITORS
PULSER Enable
step 1
shown above. Adjust the clock output so that the clock frequency
Wire the circuit
is approximately 1 Hz.
18
STEP 2
The truth table for the operation of the circuit can be summarized as follows:
0 0 Previously latched D
0 0 ab Previously latched D
i 0 0 0
iL 0 it ih
0 il xX High-impedance state
1 alt xX High-impedance state
X = irrelevant
A logic 1 state.
STEP 3
Enable both the 7475 latch and the 74125 buffer. What do you observe on the lamp
monitor?
?
~
STEP 4
Now disable the 74125 buffer. What happens to the lamp monitor output?
It becomes logic 0. The 74125 buffer output is now in its high impedance state.
STEP 5
Enable the 74125 buffer, but this time enable or disable the 7475 latch. Is it
possible to latch either the logic 0 or logic 1 data input at D (pin 2)?
Yes, it is possible to operate the 7475 latch independent of the 74125 buffer.
REVIEW
The following questions will help you review three-state devices and three-state
bussing techniques.
2. In what types of digital devices might you find a bus? List at least three
such devices.
5. List different types of digital devices, @.g., gates, latches, etc., that
are available from National Semiconductor Corporation with three-state outputs.
6. What happens in a three-state bus system when two or more sources of bus
data are simultaneously enabled?
9-20
ANSWERS
1. A digital bus is a set of common conducting paths over which digital informa-
tion is transferred. Only one transfer of information can take place at any one
time. While such a transfer is taking place, all other sources that are tied to
the bus must be disabled. The fundamental purpose of @ bus is to minimize the
number of interconnections required to transfer information between digital
devices. 9
2. Busses are present: (a) within integrated circuit chips such as the 8080A
microprocessor chip and the 8251, 8253, 8255, 8257, and 8259 programmable interface
chips; (b) on printed circuit boards that contains collections of integrated
circuit chips between which information must be bussed; and (c) in digital instruments
such as minicomputers, microcomputers, frequency meters, digital voltmeters, and
the like.
0 enable 0
it enable il
xX disable High impedance X = irrelevant
4, Such a circuit can act in several different ways: (a) as a latch that stores
input data but does not output it to a bus; (b) as a simple three-state buffer that
does not latch input data; and (c) as a latch that stores input data and outputs
it to a bus. ~
6. Two things occur: (a) the receiver of information on the bus becomes confused,
since it cannot interpret the bus information, and (b) the three-state buffers
eventually burn out. ;
2)
UNIT NUMBER 20
INTRODUCTION
OBJECTIVES
3 o Sketch several simple latch circuits that are useful for accumulator
output in an 8080A-based microcomputer.
iy o Sketch one or two simple three-state buffer circuits that are useful
for accumulator input in an 8080A-based microcomputer.
loo Explain how device select pulses are employed to achieve the objective
of accumulator input/output.
WHAT IS INPUT/OUTPUT?
When the term, tnput/output, or I/O, is employed, we usually mean that one
or more data bytes are transfgrred between an input/output device [see Unit Number
16] and the microprocessor chip. The important concepts associated with this data
transfer are summarized in Figure 20-1 through 20-3.
All mterocomputer tnput/output oceurs eight bits at a time over the 8080A bidirec-
tional data bus. As shown in Figure 20-2, the only path over which data can be
transferred into the 8080A chip is the bidirectional data bus, DO through D7,
which is an 8-bit three-state bus. =
+5V GND
Two -phase
clock.
8-bit bidirectional
data bus.
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20-5
Synchronization pulses are required to control all data transfers to and from the
8080A microprocessor chtp. For accumulator I/0, they are called device select
pulses [see Unit Number 17] while for memory I/0 they are called address select
pulses. In accumulator I/0, the two-byte IN and OUT’instructions permit you to
select and synchronize the operation of 256 different input "devices" and 256
different output "devices," as shown in Figure 20-3. For an 8080A-based micro-
computer, such pulses have a duration of about one clock period and can be either
positive or negative pulses depending upon the decoding scheme used. Typically,
such pulses are generated as negative device select pulses from a decoder chip
[see Unit Number 17] and must be inverted if positive device select pulses are
required.
The reference point for the terms "input" and "output" is the microprocessor chip.
The 8080A chip outputs data to an "output" device, and inputs data from an "input"
device. This rule holds in all cases.
6 interrupt signal
from input or
output devices.
256 different
256 different
device select
device select
pulses to
pulses to
input devices. output devices.
Figure 20-3. Schematic diagram illustrating the role of device select pulses in
accumulator 1/0.
MICROCOMPUTER OUTPUT
The basic technique that you use to output data from the accumulator to an output
device is quite simple: you generate, via software and hardware, a stngle output
device select pulse and use it to enable a latch chip at the instant when the
xecumulator data appears on the bidirectional data bus. The 8080A microprocessor chip
is responsible for the entire synchronization process. The latch chip plays a
passive role in the data transfer process and latches data only when instructed
to do so by a device select pulse. Depending upon the type of latch chip used,
either a positive or a negative device select pulse is used to latch the data.
Recall Experiment No. 4 in Unit Number 17, im which you used a 74154 decoder
chip to gemerate sixteen different negative device select pulses [Figure 20-4].
To 7490 counter
|
OUT O-NWwfa~aMArnwWUO-NWan
or
IN
LAMP
MONITORS
Figure 20-4. Schematic circuit diagram of the use of a 74154 decoder chip to
generate sixteen different negative device select pulses.
It is such pulses that you use, either directly or with inversion, to latch
microcomputer data into chips such as the 8212, 74100, 7475, 74198, T4175 10%
74193.
Typical microcomputer output circuits include those based upon the 8212 chip
(Figures 20-5 and 20-6);
20-7
8212
7 H
D6 6
DS F LAMP
D4 E MONITORS
D3 D
D2 Cc
DI B
a A. C LAMP
ps2 MONITORS
OUT 000 DSi
MD
no =] ies)
Rev. 9/22/77
Cah i epee
|L
Figure 20-7. Pin configuration of the 7/4100 eight-bit D-type latch chip.
: C 7-SEGMENT
F DISPLAY
E
D D
C C 7-SEGMENT
B B DISPLAY
A A
D
C 7-—SEGMENT
OUT 000 : DISPLAY
Figure 20-8. Microcomputer output latch circuit based upon the use of a 74100
D-type latch. The output is provided as a three-digit octal word.
ENABLE
10 20 20 12, GND 30 30 4a
w|_[r5| [ra] fr] fr2|_fn [wo] Js
] T
at
7 8
4D 40
7475
Figure 20-9. Pin configuration of the 7475 four-bit D-type latch chip.
Rev. 9/22/77
29-9
+5V GND
n LAMP
F MONITORS
E
OUT 000
MONITORS
DO
+5V GND
Figure 20-10. Microcomputer output latch circuit based upon the use of a pair of
7475 four-bit D-type latches.
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lap i2fis Taf LF ina if{u] 2
74198
Figure 20-11. Pin configurations of the 74198 eight-bit shift register and the
74175 four-bit latch. Both chips contain positive-edge triggered flip-flops
of the 7474 type.
Rev. 9/22/77
20-10
+5V GND
H
G
ia LAMP
Is MONITORS
D
Cc
B
A
LAMP
OUT 000 MONITORS
Figure 20-12. Microcomputer output latch circuit based upon the use of a 74198
eight-bit shift register.
+5V GND
D7
MONITORS
OUT 000
D
¢ LAMP
B MONITORS
A
+5V GND
Figure 20-13. Microcomputer output latch circuit based upon the use of a pair of
74175 latch chips.
Rev. 9/22/77
20-1
—
LCL
74192, 74193
Figure 20-14. Pin configurations of the 74192 and 74193 up/down counter chips,
which each contain an internal 4-bit latch of the 7475 type.
+5V GND
D7
D6 LAMP
MONITORS
OUT OOO
LAMP
DI MONITORS
DO
+5V GND
Figure 20-15. Microcomputer output latch circuit based upon the use of a pair of
74193 up/down counter chips. This circuit demonstrates how you would
pre-load a count into an up/down counter directly from the accumulator
in an 8080A-based microcomputer. You would not normally use such a chip
as a general purpose latch.
Rev. 9/22/77
When using the 8212 chip as an output latch, you should make certain that the
clear input, CLR, at pin 14 is tied to logic 1 when not in use.
The characteristics of different TTL subfamilies and the concepts of fan-in and
fan-out have been previously described in Unit Number 10. Such considerations
are extremely important when you construct microcomputer output circuits. Thus,
the fan out of an 8080A microprocessor chip is 1.2, which means that a single
output pin can drive (sink) a maximum current of only 1.9 mA. The fan-in of a
normal 7400-series input is 1.6 mA, so it should be clear that you should always
employ output devices that have a much Lower fan-in whenever you make a direct
connection to an 8080A output pin.
Many low-power chips can be tied to the output busses from a microprocessor chip
provided only that such busses are not overloaded.
You should also concern yourself with the fan-out of a low-power chip that is
connected to an 8080A bus. If output signals must travel over a distance that
is greater than several inches, it is good policy to buffer the latch outputs.
Latch and flip-flop outputs are inherently sensitive to drive problems. The
fan-out of a 74LS output is only 5 while that for a 74L output is 2.25.
The technique that you use to input data from an external device into the
accumulator is analogous to the technique used for microcomputer output: you
generate, via software and hardware, a single input device select pulse and use
tt to enable a three-state buffer at the instant when a direct path is opened
up between the btdtrecttonal data bus and the acewnulator. As with microcomputer
output, the 8080A chip is responsible for the entire synchronization process.
The three-state buffer chip plays a passive role in the data transfer process
and applies data to the data bus only when instructed to do so by a device
select pulse. Either a positive or negative device select pulse is used to
enable the buffer, depending upon the type of buffer used. Typical three-state
buffer chips are the 8212 and 8095. The 8255 programmable peripheral interface
chip has become popular as an input buffer.
Typical microcomputer input circuits include those based upon the 8095 or 8212
chips, as shown in Figures 20-16 through 20-18. The 8212 eight-bit latch/buffer
chip has been previously shown in Figure 20-5 as an output latch. It should be
emphasized that only one three-state buffer input to an 8080A-based microcomputer
must be enabled at any gtven time. A1l input device select pulses should be
absolutely decoded, which means, for accumulator I/0, that all eight bits of
the device code should be used to uniquely identify the desired input device.
If a non-existent device is called to input data, usually the byte, 377 5 eee
be input to the accumulator.
LOGIC
SWITCHES
LOGIC
SWITCHES
+5V GND
Figure 20-17. Microcomputer input circuit based upon the use of a pair of 8095
three-state buffer chips. The logic switches can be replaced by any
eight-bit source of TTL data.
DATA-7 H H oS
DATA-6 G G D6
DATA-5 FE F D5
DATA-4 E E D4
DATA-3 D D D3
DATA-2 C C D2
DATA-| B B DI
DATA-O A A DO
(2) rc za
8212
Figure 20-18. Microcomputer input circuit based upon the use of an 8212 latch/
buffer chip.
Rev. 9/22/77
20-15
ACCUMULATOR 1/0 INSTRUCTIONS
There are only two 8080A accumulator I/O instructions, which transfer data between
the accumulator and external I/0 devices concurrent with the generation of the
IN and OUT synchronization pulses:
323 <B2> OUT Output the accumulator contents to the output latch selected
by the device code in the second byte. This instruction is
executed in ten clock cycles, or 13.33 us for an 8080A-based
microcomputer operating at 750 kHz.
B55 <B2> IN Input into the accumulator the contents of the digital device
and three-state buffer circuit selected by the device code in
the second byte. This instruction is executed in ten clock
eveles, or 13533, is) fora 750) kez clock rate.
In this Unit, in contrast to Unit Number 17, the device select pulses generated
by the above instructions are used to transfer information to and from the
accumulator.
A simple program to input the logic switch data in Figure 20-17 into the accum-
ulator and then immediately output it to output latch 000 shown in Figure 20-10
is as follows:
LO memory Instruction
address byte Mnemonic Description
This program will input the logic switch data into the accumulator, then output
the accumulator data to an output latch, and finally halt.
SECOND PROGRAM
To continuously input and output the data acquired by input device 004, change the
HALT instruction to a JMP instruction that loops back to HI = 003 and LO = 000.
LO memory Instruction
address byte Mnemonic Description
THIRD PROGRAM
To store the input data into a memory location and update the memory contents
each time a new eight-bit data point is input, you would use the following program:
LO memory Instruction
address byte Mnemonic Description
This program is similar to the second program, but this time a STA <B2> <B3>
instruction has been added to permit you to store the accumulator contents into
memory location STORE, which is at HI = 003 and LO = 200. After the program comes
to a halt, examine location STORE to see if the input logic switch data from
device 004 is present. Change the switch settings, execute the program again, and
20-17
again, and once more examine memory location STORE. You may ask, How can data be
stored when it has previously been sent out to output latch 000? At first glance,
it appears that the input data has been "used up" when it is output to latch 000.
The answer is that when a data byte is transferred from one location to another,
it is copted to the new location. The original data is still present and is not
"used up." This general rule holds for almost all data transfers in a microcomputer
system, from register to register, register to memory, memory to register,
accumulator to output device, etc.
FOURTH PROGRAM
LO memory Instruction
address byte Mnemonic Description
When you execute this program, you will be able to determine the encoding for each
of the fifteen keys on the MMD-1 microcomputer. The sixteenth key is RESET, which
is hardwired directly to the 8224 chip. The encoding of the keys can be summarized
as follows:
Input data byte
* FIFTH PROGRAM .
This program adds one to the contents of the accumulator, decimal adjusts the
accumulator contents, and then outputs the binary-coded:decimal result, 2.é.,
two BCD digits packed in an 8-bit data byte, to output port 002.
LO memory Instruction
address byte Mnemonic Description
When you execute this program, you will observe the BCD numbers 00 through 99 at
output port 002. Once the port reaches 9919, it returns to 00 and repeats the
slow counting process. As a programming tip, we would like to point out that you
should not use the INR A instruction to increment the accumulator immediately
before a DAA instruction. The ADI 001 instruction accomplishes the same result,
and properly adjusts the carry and auxiliary carry bits so that the DAA operation
can be properly performed.
2)-2)
The acewnulator I/O ports that you wire in Expertment Wo. 1 will be used, with
very little modtfication, tn Experiment Nos. 1 through 3 in Untt Number 21.
Do not remove the 7475 and 8095 I/O port cireutts from your breadboard.
9.9
221
EXPERIMENT NO. 1
A SIMPLE MICROCOMPUTER INPUT-OUTPUT CIRCUIT
PURPOSE
The purpose of this experiment is to test the behavior of a simple microcomputer
input-output circuit based upon the 8095 three-state buffer and the 7475 latch.
ENABLE
10 20 20 12 GNO 30 3a 40
10 10 2D ENABLE Vcc 30 40 40
34
7475
D7
MONITORS
OUT 003
MONITORS
20-2
+5V GND
LOGIC
SWITCHES~
LOGIC
SWITCHES
vA
\
nw
/ |
+5V GND —
\
7 \
ee
PROGRAM
LO memory Instruction
address byte Mnemonic Description
step 1
This experiment provides you with experience in the wiring both of an input port
and also an output port. If you only wish to have experience wiring the input
Rev. 9/22/77
port, do not wire the 7475 latch circuit and skip to Step 7 below.
On a breadboard that has sufficient room for four 16-pin integrated circuit chips,
wire the 7475 output port and the 8095 input port. Note the use of the 2-input 7402
NOR gate contained within the 8095 chip as a device select pulse generator. Use the
circuit in Experiment No. 6 in Unit Number 17 to generate the OUT 003 pulse. The
input port can also be wired with the aid of a LR-29 Outboard.
STEP 2
Load the program into memory starting at HI = 003 and LO = 000.
STEP 3
Set the logic switches all to logic 1. Execute the program at the full microcomputer
speed. What do you observe at output port 003?
STEP 4
With the microcomputer operating at full speed, return each logic switch, one at
a time, to logic 0. While doing so, explain what you observe on the output port
lamp monitors.
STEP 5
Set the eight logic switches to HGFEDCBA = 11110101, or 365 in octal code. Execute
the program at the full microcomputer speed, and then switch to single-step oper-
ation using a circuit such as that described in Experiment No. 2 in Unit Number 17.
Wire a bus monitor circuit such as that described in Experiment No. 1 in Unit Number
17. The latch enable input should be at logic 0.
STEP 6
Single step through the execution of the program and verify the following sequence
of bytes that should appear on the bus monitor. Note that you are executing a
continuous loop, so you should always be able to start at the beginning through
the application of several single-step pulses.
Rev. 9/22/77
20-24 Data bus byte
that appears
on the
bus monitor Comments
003 FETCH machine cycle for byte <B2> of the OUT instruction
that is the device code of the output port
000 FETCH machine cycle for byte <B2> of the JMP instruction.
This is the LO address byte of memory location START.
003 FETCH machine cycle for byte <B3> of the JMP instruction.
This is the HI address byte of memory location START.
°
As you continue to single step the microcomputer, the above “sequence of bytes on
the data bus will be repeated. The important point here is the fact that you can
actually observe the transfer of data between the accumulator and an input or
output device. When you work with more complex interface circuits, you may wish to
have a bus monitor and single-step circuit to verify that the proper data is being
transferred at the proper time.
sTeP /
If you do not wish to wire a 7475 latch circuit and if you have a MMD-1
microcomputer, you can take advantage of the fact that there are three
7475-based output ports on the board. The device codes for these ports are 000,
001, and 002. We recommend that you use output port 002, which requires a change
in the instruction byte at LO = 003 to (Q2. Make this change in the program.
20-25
STEP 8
Set the eight logic switches to logic 1. Execute the program at the full micro-
computer speed. What do you observe at output port 002?
STEP 9
With the microcomputer operating at full speed, return each logic switch, one at
a time, to logic 0. While doing so, explain what you observe on the output port.
sTeP 10
Set the eight logic switches to HGFEDCBA = 11110101, or 365 in octal
code. Execute
the program at the full microcomputer speed, and then switch to
single-step
operation using a circuit such as that described in Experiment No.
2 in Unit Number
17. Wire a bus monitor circuit similar to that described in Experiment No.
1 in
Unit Number 17. The latch enable input should be at logic 0.
step 11
Single step through the execution of the program and verify the sequence of bytes
given in Step 6 of this experiment. Keep in mind that the FETCH machine eyele for
the output instruction device code places the byte 002 on the data bus instead of
003. Why?
You have changed the output port device code from 003 to 002 in Step 7. Therefore,
device code 002 must appear on the data bus during the FETCH machine cycle.
DISCUSSION
This experiment integrates much of what you have learned so far: the generation
and use of device select pulses, accumulator input-output, and 8080A programming
for input-output operation. A simple three-state input port and latch output port
have been constructed and used under software control.
I0_96
20-20
EXPERIMENT NO. 2
MICROCOMPUTER INPUT-OUTPUT ON THE MMD-1 MICROCOMPUTER
PURPOSE
.
PROGRAM
LO memory Instruction
address byte Mnemonic Description
STEP 1
the
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input/output
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MMD-1
20-28
Note the following:
o The: I/O decoder circuit consists of a 74L42 decoder chip and 7402 2-input
NOR gates. For further details, consult Figure 17-7 and the associated
text as well as Experiment No. 5 in Unit Number’ 17.
* Output port 000, which consists of 7475 latches IC26 and 1C27
* Qutput port 001, which consists of 7475 latches IC24 and IC25
* Output port 002, which consists of 7475 latches IC28 and IC29
o There is one 5-bit input port, which is ultimately connected to the keyboard
o The pair of 74148 priority encoder chips and the 7400 2-input NAND gate
provide the circuitry to decode fifteen keys on the keyboard. When
a single key is pressed, the input to the 74148 corresponding to that key
goes to a logic 0 and output GS on the 74148 chip goes to a logic 0.
The three-bit octal code for the pressed key appears at output pins A, B,
and C on the 74148 chip. Remember that the sixteenth key, RESET, is a
hardwired function and generates no code.
STEP 2
Load the program into memory starting at HI = 003 and LO = 000.
STEP 3
Execute the program at the full microcomputer speed. When you do not press any
key on the keyboard, which bits are lit on output port 002?-
Bits D4, D5, and D6 are at logic 1; the remaining five bits are at logic 0.
STEP 4
Press any key on the keyboard except the RESET key. Is it true that bit D7 on
output port 002 always goes to a logic 1 when any of the remaining fifteen keys
is pressed?
Yes. The reason is that this is the bit that indicates to the KEX monitor
program that a key has been pressed. Once the microcomputer detects that a key
29-29
has been pressed, it then proceeds to determine which key was pressed. In the
routine that accomplishes this task, there is a 10 ms time delay to eliminate
the common problem of contact bounce. The keyboard input program from KEX is
listed at the end of this experiment.
STEP 5
So far, you have observed that bits D4, D5, and D6 remain at logic 1 no matter
which key is pressed and that bit D7 goes to logic 1 whenever a key is pressed.
You now must determine the function of the remaining four bits, DO through D3.
Press keys 0 through 7 in sequence and observe the bit pattern at the output
port 002 bits DO through D2. What do you observe?
The bit pattern at DO through D2 corresponds to the three-bit code for the keys
0 through 7. Thus, key 5 will have the three-bit code, 101.
STEP 5
Pressskeysun,) li GiiS,. 45 B, and C and explain what you observe at bit D3 on
the output latch. Also explain the significance of bits DO through D2 when
these keys are pressed.
WRPHrMAANYNDUEWNHO
BPE
PREP
PRP
ERR
RR
EB RPP
RB
RP
PRR
PRP
PELRP
RPP
PRE
PPERP
RRP
PER
EE PREREFFRFRODOCOCOOC0O0
PREPRFPROCDCORRFFROGOCO
FPROORFORRPOORHFOO
FORPOCOFRFOCOFRFOFROFROFRO
20-30
step /
When keyboard keys are activated, the code is input and then output from the
8080A chip to the latched LEDs. It is important to remember that this data
transfer process is under software control. ;
Change the device code byte at LO = 001 to 005 in the program, then execute
it at 750 kHz. Does it operate as it has previously? Why?
No. The device address for the input instruction has been changed so that the
keyboard is no longer selected.
Memory Instruction
address byte Mnemonic Comments
000 345 346 /Mask out all bits but key code
000 346 017
The following translation table converts the code generated by key closures to
the code used by the main KEX program.
000 277 365 TIMOUT, PUSH PSW /Save accumulator and flags
The above programs have been written in the way they would appear as output from
the Tychon, Inc. 8080A resident assembler/editor program.
EXPER MENT IMENT NO, 3 29-33
CHARACTERISTICS OF THE DAA INSTRUCTION
PURPOSE
The purpose of this experiment is explore some of the characteristics of the DAA
instruction.
PROGRAM
LO memory Instruction
address byte - Mnemonic Description
We mean an 8-bit number that is composed of two 4-bit BCD digits, one occupying
the four most significant bits and the other occupying the four least significant
bits.
STEP 2
Load the program into read/write memory starting at HI = 003 and LO = ooo.
Execute the program. Observe what happens immediately after the BCD count
in output port 002 reaches 9910- Summarize your observations in the space
below.
We observed that the counts immediately following 99 were 00, 01, 02, 03, 04,
OB, Og O25 OB4 Wa WO a 9 045 In other words, the output port "rolled over"
and started to count up from 00 once again. This typeof behavior is what we
would expect. i
STEP 3
Now change the following instruction bytes in the program: :
Execute the program, as modified above, and explain what you observe on output
port 002 immediately following 9949:
codes) 005615 ‘255235784, E5,°46, 47,08, 69, D059 31,92, etc. The least
significant BCD digit was correct, but the most significant BCD digit varied
in anunpredictable manner.
STEP 4
Why did you observe a problem when the INR A instruction replaced the ADI 001
instruction? After all, both increment the accumulator contents by one.
The ADI 001 instruction affects both the auxiliary carry and carry flags,
depending upon the result of the operation. In contrast, the INR A tnstructton
affeets only the auxiltary carry flag. In order for the DAA instruction to
operate properly, both the carry and auxiliary carry must respond properly
to an arithmetic instruction that immediately precedes the DAA instruction.
Such is not the case for the INR A instruction.
step 5
Consider the following initial steps in the program:
Once this addition has been performed, the time delay routine executed, and the
sum output to port 002, the microcomputer execution is halted through the use
of the following instruction byte,
The terms, augend and addend, have been defined by Graf? in the following manner:
In the above program section in this Step, must the data bytes AUG and ADD be
binary numbers or packed BCD numbers? The answer to this question is crucial to
2-56
o If the four steps are not followed by a DAA instruction, the data bytes
AUG and ADD are treated as 8-bit binary numbers and a straight binary
addition is performed to yield a binary number as a sum.
o If the four steps are followed by a DAA instruction, the data bytes AUG
and ADD are treated as 8-bit packed BCD numbers and a BCD correction
is automatically performed within the 8080A to yteld a packed BCD number
as a sum.
This is a very important distinction and one that you must remember. With the
8080A microprocessor chip, you can, in essence, perform simple BCD arithmetic,
which means that the augend, addend, and sum are all considered to be packed
BCD numbers. You should remember, though, that the 8080A and almost all other
computers are binary processors. All data is treated as binary 1s and Os.
Codes such as ASCII, EBCDIC, and BCD are transparent to the computer. To
perform BCD math requires careful attention to programming and the careful use
of the Decimal Adjust Accumulator (DAA) instruction. It should not be considered
as a binary-to-decimal converter!
STEP 6 .
Change the instruction bytes at LO memory addresses 000, 002, and 020 to those
indicated in Step 5. Perform the following additions between the BCD data
bytes AUG and ADD, and compare the SUM that you observe on output port 002 with
that given in the table below.
10 00 10
10 10 20
10 US 25
15 19 34
27 28 55
33 48 81
38 75 13*
99 99 98*
STEP 7
Eliminate the DAA instruction by substituting the following NOP instruction byte:
Perform the following additions between AUG and ADD and compare the SUM that you
observe on output port 002 with that given in the table below.
10 00 10
10 10 20
10 > 25
1 19 2E
By 28 4F
35 48 7B
38 Us AD
99 99 32*
Note that the AUG and ADD column entries are given in hexadecimal code (hex) rather
than in octal or decimal code. One of the objectives of this experiment is to
give you some practice in converting decimal and hexadecimal quantities into
octal code, and vice versa.
Rev. 9/22/77
20-38
You should conclude that when an addition of two numbers is not immediately followed
by a DAA instruction, the data bytes AUG and ADD as well as the SUM must be con-
sidered as regular 8-bit binary numbers. The microcomputer is now performing
binary arithmetic, but the sum has not been corrected to give a BCD answer.
This experiment demonstrates, that you can input and output either binary or
packed BCD data and perform either binary or’ BCD additions using such data.
We have simunlated the input of BCD data through the use of the MVI A
instruction.
20-39
REVIEW
The following questions will help you review accumulator input/output techniques.
2. What differences exist between chips used for microcomputer output and those
used for microcomputer input? Explain why the chips for the two different
uses must differ in function.
3. Why is the output drive capability of a microprocessor chip and the fan-in
characteristics of interface chips important in microcomputer output circuits?
4. Based upon the information presented in the Fifth Program and Experiment No. 3,
explain the characteristics of the DAA instruction in the addition of a pair of
8-bit numbers.
20-40
ANSWERS
In microcomputer input, the objective is to input stable TTL data into the
microprocessor chip during the interval of time when the external input device
has control over the data bus. At all other times, the input device should
not influence the data bus. Such objectives are accomplished using a three-state
8-bit buffer.
4. In the absence of a DAA instruction, when two 8-bit numbers are added using
an ADD, ADC, ADI, or similar instruction, the sum of the two numbers is in
binary and the augend and addend are assumed to be binary quantities. When
a DAA instruction immediately follows an ADD, ADC, .or ADI instruction, the
augend, addend, and sum must all be considered to be 2-digit packed BCD numbers.
In other words, you can perform pure binary addition or pure BCD addition
depending upon whether the DAA instruction is absent or present.
UNIT NUMBER 21
INTRODUCTION
OBJECTIVES
Terminology: The memory I/O processes will be called read and write
rather than input and output. The decoded signal that
strobes a memory I/O device will be called an address
select pulse rather than a device select pulse.
The advantages of memory I/O techniques can be clearly seen from a comparison of
Tables 21-1 and 21-2. Data transfer can be between the I/O device and any of the
seven general purpose registers within the 8080A chip. If the 16-bit memory
address has been previously stored in register pair H, then the data transfer
can be quicker if either a MOV r,M or MOV M,r instruction is used. In principle,
many more devices can be addressed by memory I/O techniques than by accumulator
I/O techniques. Finally, two-byte data transfers in a single instruction are
possible using the SHLD and LHLD instructions.
An important point is that memory I/O and accumulator I/O techniques are not
fundamentally different from each other. In each case, a control signal indicates
whether the operation is one of input or output. Also, in each case the address
bus must be decoded to identify a specific I/0 device. Finally, in each case the
actual data transfer occurs in a machine cycle during the execution of the
instruction. For accumulator I/0, this machine cycle generates with the aid of
a status latch the control signals IN and OUT; for memory I/0, the signals MEMR
and MEMW are generated instead. You can observe the data transfer over the
bidirectional data bus with the aid of a bus monitor [see Experiment No. 1 in
Unit Number 17].
We have observed during our work with memory I/O techniques that it is easy to be
careless when they are used. Most problems can be attributed to the lack of
absolute decoding of the entire 16-bit address bus. When addressing a memory
I/O device, it is not sufficient to decode bits AO to A9, since these same bits
are used in any 8080A-based microcomputer system that has at least 1K of addres-
sable memory. Therefore, if you wish to use memory I/O techniques, you should
plan to decode some of the highest bits on the address bus, specially bits A13
to Al5.
To generate a memory I/O address select pulse, you need two types of information
from the 8080A microcomputer:
In other words, as with accumulator I/O, during the generation of a memory 1/0
address select pulse, both the address bus and the control bus are active. It
is your responsibility to properly decode the signals on these two busses to
produce unique address select pulses that can be used to transfer data between
the external memory I/0 device and the internal registers of the 8080A.
Figure 21-1 provides a commonly used decoding technique for memory I/O address
select pulses. Note the resemblance between this figure and Figure 17-2 in
Unit Number 17. The 74154 decoder is enabled by two signals: the complement of
the A-15 address bus bit, and either MEMR or MEMW. The truth tables for the chip
enable process are given in Table 21-3. Observe that the 74154 decoder_is enabled
only when address bus bit A-15 is at logic 1. Data is input only when MEMR is
at logic 0 and output only when MEMW is at logic 0. When no memory data is being
transferred, both MEMW and MEMR are at logic l.
O-Nwtaaroa
©O-NUpa
LAMP
MONITORS
Figure 21-1. Decoder circuit for the generation of sixteen different memory mapped
address select pulses. The HI address byte is 200 and the LO address
byte ranges from 000 to 017, in octal code. This is not an absolute
decoder circuit for the 16-bit address bus.
2ee)
ras
Table 21-3. Truth tables for the decoder circuit shown in Figure 21-1.
0 0 disabled 0 0 disabled
0 1 disabled 0 it disabled
1 0 generate read pulse i 0 generate wrtte pulse
1 I: disabled ip 1 disabled
In Figure 21-2, ten of the sixteen address bus bits are decoded by a pair of
74154 decoders. For the circuit shown, sixteen memory I/0 address select pulses
are produced, starting at HI = 300 and LO = 000 and terminating at HI = 300 and
LO = 017. The 74154 decoder No. 2 is enabled only when both A-14 and A-15 are
at logic 1. Any one of the sixteen output pins on decoder No. 2 can be used to
enable the G2 input of decoder No. l.
+5V GND
Device select
pulse 300 004
LAMP
MONITORS
+5V GND
Figure 21-2. Decoder circuit that generates sixteen different memory I/O address
select pulses starting at memory address HI = 300 and LO = 000. Ten of
the sixteen address bus bits are decoded by this circuit, which is not
an absolute decoder.
A final decoding technique is similar to that employed in Figure 17-8 in Unit
Number 17. The high address bits are input into a 74L30 eight-input NAND gate,
which decodes the eight bits into a single unique logic 0 state. For example,
if A8 through A1l5 are input into a 74L30 gate, a logic 0 output will be
produced only when A8 = A9 = Al10 = All = Al2 = AI3>= Al4 = AI5 = 1. This output
can then be used to enable other decoder chips such as the 74154 or 7442.
The Intel Corporation "8080 Microcomputer Systems User's Manual" provides inter-
esting diagrams that demonstrate how to use address bus bit A-15 to distinguish
between memory and a memory I/O device. In accumulator I/0, four control signals
are generated either by the 8228 chip [Figure 21-3] or by equivalent circuitry:
MEMR, MEMW, IN, and OUT. These signals permit you to distinguish between a memory
location and an I/O device. In memory I/0, it can be observed from Figure 21-4
that only MEMR and MEMW are used to address both memory and memory I/O devices.
In the figure, address bit A-15 is gated with these two control signals to
produce two new control signals, MEMIOR and MEMIOW,that are used only with 1/0
devices.
TO
\- MEMORY
DEVICES
—— MEMR
TO MEMORY
= DEVICES
MEMW
SYSTEM
CONTROL
SYSTEM = (8228) IN EAGT
CONTROL | MEMIOR | foie
(6228) TO I/O DEVICES - Devices
—— OUT MEMIOW,
Figure 21-3. Control signals used Figure 21-4. Control signals used in one
in accumulator I/0. Thts figure type of memory I/0% This figure courtesy
courtesy of Intel Corporatton, of Intel Corporatton, Santa Clara, Calt-
Santa Clara, California. All fornia. All rights reserved.
rights reserved.
The effect of the use of address bit A-15 is to subdivide the 65K of memory into
two 32K blocks, one for memory and the other for memory I/O devices. This is
shown in Figure 21-5. Im contrast, in normal accumulator I/0, only 256 input
or 256 output devices can be addressed, but the maximum size of the memory can be
as large as 65K.
The accumulator I/O and memory I/O techniques discussed in this and previous units
do not exhaust the available possibilities. Rather than use a 74154 decoder, the
individual bits in the 8-bit device code could be decoded directly to select six
I/O devices each of which requires a 2-bit port select code [Figure 21-6]; this
type of accumulator I/O is very useful when you have only a few I/0 devices.
The same technique can be applied in memory I/0, as shown in Figure 21-7. In the
figure, you can select up to thirteen different memory I/0 devices each of which
requires a 2-bit port select code. Bit A-15, as in Figure 21-4, is used to
distinguish between memory and a memory I/O device. Finally, if you wish to restrict
Rev. 9/22/77
|
the 32K memory I/O block in Figure 21-5 to a smaller region of memory, you can
simultaneously decode several of the higher bits on the address bus. For example,
if you use a pair of 7420 4-input NAND gates in Figure 21-4 rather than the 2-input
NAND gates shown, you can decode address bits A-13, A-14, and A-15 and restrict
the memory I/O memory block to 8K and expand the memory block to 57K.
CCUMULATOR 1/0
= =A
0) 65K |
| |
MEMCRY
° N qaa
VO
f PORT SELECTS
|
MEMORY 1/0 | |DEVICE SELECTS
|
c= MEMORY 1/0.
Figure 21-5. Memory block comparison Figure 21-6. Example of the use of the
between accumulator I/O and memory 8-bit device code in accumulator I/0
1/0. Courtesy of Intel Corporation, to address six devices each of which
Santa Clara, Caltfornita. All rights requires a 2-bit port code. Courtesy
reserved. : of Intel Corporatton, Santa Clara,
Caltfornta. All rights reserved.
PORT SELECTS
DEVICE SELECTS
Figure 21-7. Example of the use of the 16-bit memory address word in memory I/0
to address thirteen different memory I/0 devices each of which requires a
2-bit port code. Courtesy of the Intel Corporation, Santa Clara, California.
All rights reserved.
2Z1F6
MEMORY MAPPED 1/0 INSTRUCTIONS
There are twenty-two 8080A instructions that permit you to transfer data between
the internal registers and external memory devices. These external devices can
be either semiconductor memory, Z.e., read/write memory, ROMs, EPROMs, etc., or
else they can be input-output devices that are addressed as if they were memory
locations. ‘Implied in any memory-reference instruction is a 16-bit memory address
that uniquely identifies a memory. byte. This memory address is contained either
in register pair H, register pair B, register pair D, or else in bytes <B2> and
<B3> of the instruction itself.
All thirty-three memory reference instructions are summarized below. They are
sub-divided according to the location of the memory address word.
w= LDAX D 032 Load the accumulator with the contents of memory location M
given by the contents of register pair D
21-10
ADDRESS OF MEMORY LOCATION M IS CONTAINED IN SECOND AND THIRD INSTRUCTION BYTES
LHLD 052 Load register L with the contents of memory location M defined
<B2> <B2> by instruction bytes <B2> and <B3>; load register H with
<B3> <B3> the contents of the succeeding memory location, Mtl. [NOTE:
This is a two-byte data transfer in a single instruction].
The SHLD and LHLD instructions differ from the remaining thirty-one memory reference
instructions in the fact that two data bytes are transferred,
As with the IN and OUT instructions, the 8080A microprocessor has a machine cycle
during which data transfer occurs between the memory location and the internal
registers. The machine cycle is called either a MEMORY READ or a MEMORY WRITE
cycle, during which the following occurs:
o The external bidirectional data bus and the internal data bus
within the microprocessor chip are opened to permit direct data
communication between one of the internal general. purpose
registers and the I/0 device, whether input or output.
The SHLD instruction differs from the others in the fact that two successive
MEMORY WRITE machine cycles are executed by the 8080A. With the LHLD instruction,
two successive MEMORY READ machine cycles are executed. In all other cases, only
one machine cycle, either a MEMORY READ or a MEMORY WRITE, is executed.
FIRST PROGRAM
LO memory Instruction
address byte Mnemonic Description
In this program, we have made the assumption that there exists no memory at
location HI 200 and LO = 000. For most 8080A-based microcomputers, this is an
excellent assumption.
If you would execute this program in the single-step mode, you would observe the
following bytes, in succession, on the bidirectional data bus:
Data bus
byte Comments
The program increments the contents of the accumulatot during each loop. Also,
it outputs the accumulator contents to the memory I/O device, HI = 200 and
LO = 000. ‘The decoder circuit shown in Figure 21-1 would be used.
Input-output circuits that employ memory I/O addressing are identical to those
shown for accumulator I/O in Unit Number 20. The only difference is the type
of select pulse used. We provide several examples here to demonstrate the
similarity, and then refer the reader to the preceding Unit.
A memory output circuit that is based upon the 74198 8-bit shift register is shown
in Figure 21-3. The address select pulse is a MEMW pulse coded for memory address
HI = 200 and LO = 000, as would be generated by the circuit of Figure 21-1. A
related circuit is based upon a pair of 7475 D-type latches, and is shown in
Figure 21-4. This time, however, the memory address of the output latch is
HI = 200 and LO = 001. Seven-segment displays are used for two different purposes
in these two output circuits. For the 74198 shift register, we assume that the
output is a pair of packed BCD digits, whereas for the 7475 chips, we assume that
the output is in 8-bit binary, which we decode as three octal digits.
+5V GND
2 7-SEGMENT
2 DISPLAY
Cc
B
2 7- SEGMENT
Address select ) DISPLAY
pulse MEMW
200 000
Figure 21-3. Microcomputer output circuit based upon the use of the memory I/0
technique applied to a 74198 8-bit shift register chip. The memory
address of this output port is HI = 200 and LO = 000, 7t.e., address bit
A-15 is used to identify this chip as a memory I/O port.
+5V GND 00
mh 7-SEGMENT
ne DISPLAY
D4
7- SEGMENT
DISPLAY
Address select
pulse MEMW _JL
200 OOl
D
C 7-SEGMENT
B DISPLAY
A
D3
D2
DI
DO
+5V GND
Figure 21-4. Microcomputer output circuit based upon the memory I/O technique
applied to a pair of 7475 D-type latches. The memory address of this
output port is HI = 200 and LO = O01.
The third and final circuit is a microcomputer input circuit based upon the 8212
8-bit latch/buffer chip. The address select pulse is generated from the MEMR
control signal and the 16-bit address bus, and has a memory address of HI = 200
and LO = 002. Otherwise, the circuit is identical to that shown in Figure 20-18.
The resemblance between these figures and the corresponding ones for accumulator
I/O in Unit Number 20 should be clear. In fact, Figures 20-18 and 21-5 are
identical except for the identification of the select pulse. We refer the reader
to Figures 20-6 through 20-17 for other useful microcomputer input/output circuits
that can be adapted to memory 1/0.
m
PWNOOMNOAT
fe} rc DD
Figure 21-5. Microcomputer input circuit based upon the memory I/0 technique
applied to an 8212 8-bit latch/buffer chip. The memory address of this
input port is HI = 200 and LO = 002. ~
SECOND PROGRAM
A program that is, during execution, identical to the First Program is as follows:
LO memory Instruction
address byte Mnemonic J Description
000 O41 START, LXI H Load register pair H with the following
two bytes
2
Rev. 9/22/77
THIRD PROGRAM
A third way to accomplish the desired result of the first and second programs is
through the use of a STAX instruction:
LO memory Instruction
address byte Mnemonic Comments
Note that this time the identification of the output memory location M is contained
within register pair B. Otherwise, the program execution is identical to that for the
first and second programs.
FOURTH PROGRAM
The D register pair can also be used to identify the memory location M. Thus:
LO memory Instruction
address byte Mnemonic Description
This program is essentially the same as the Third Program. It should be observed
that STAX H is the equivalent to MOV M,A.
FIFTH PROGRAM
Memory I/O input programs are as simple as the output programs described above.
Consider a system in which both the input and output ports have the same memory
address, namely, HI = 200 and LO = 000. The following program will permit you to
monitor the input data:
LO memory Instruction
address byte Mnemonic Description
003 01? LOOP, LDAX B Load the accumulator from the input
port M identified by the contents of
register pair B
If the memory address M is contained in register pair D rather than register pair
B, you would substitute LDAX D and STAX D for the instruction bytes at LO = 003
and LO = 004.
SIXTH PROGRAM
A program that, when executed, provides the identical result observed in the
Fifth Program is as follows:
LO memory Instruction
address byte Mnemonic Description
003 V6 LOOP, MOV A,M Load the accumulator with the contents
of input port M
As with the Fifth Program, the input and output ports have the same memory loca-
tion, HI = 200 and LO = 000. What distinguishes data transfer between the two
ports, which are shown in Figure 21-6, is the way in which the internal data bus
within the 8080A operates and also the existence of the different control signals,
MEMR and MEMW. We present Figure 21-6 as a circuit that has educational value
but not as one that you would wire in a microcomputer interface system. Why not?
The answer is that you need not wtre an 8212 input port in order to monitor the
output from the 8212 output port in Figure 21-6. We recommend that you store
the output contents in an internal register or a read/write memory location
before or after you output the 8-bit word to the 8212 output port.
+ 5V GND
H H D7
G G D6
& F D5
E E 04
D D D3
Cc Cc D2
B B Dl
A A DO
CLR
Figure 21-6. Memory I/O interface circuit that demonstrates that an input port and
an output port can have the same memory address. In general, you will
identify the two ports in this figure by different memory addresses.
SEVENTH PROGRAM
It is not necessary to input and output data to and from the accumulator, as was
done with all of the above programs. For example, in the Sixth Program, we could
exchange data with register E. This is shown below.
LO memory Instruction
address byte Mnemonic Description
Rev. 9/22/77
21-19
OO1 O01 001 L register byte, the LO address byte
of memory location M
EIGHTH PROGRAM
Consider the following program:
LO memory Instruction
address byte Mnemonic Description
1. The ease with which the I/O device code can be changed.
2. The speed with which four bytes of data can.be input into an 8080A
chip. 2
These advantages must be weighed against two possible disadvantages of memory I/0
techniques:
2. The loss of memory area when it is subdivided into memory and memory
I/0 blocks.
The following simple experiments illustrate memory mapped I/O techniques. More
extensive memory mapped I/0 experiments are provided in Unit Number 22.
The memory mapped I/O ports that you wire in Experiment No. 1 will be used tn all
of the expertments in this untt.
1-9 EXPERIMENT NO, 1
SIMPLE MEMORY MAPPED INPUT-OUTPUT PORTS
PURPOSE
The purpose of this experiment is to test the behavior of a simple memory mapped input
output circuit based upon the 8095 three-state buffer and the 7475 latch.
ENABLE
10 20 20 12. GNO 30 30 40
[16] [rs] [ra] fi] fr2]_fn|_fro
1A 1B NC 1c 10 AY: GND a A : F Oo
7420 7475
+5V GND
D7
D6 LAMP
MONITORS
Address select
pulse MEMW
200 004
LAMP
DI
DO
MONITORS
+5V GND
21-25
+5V GND
LOGIC
SWITCHES
LOGIC
SWITCHES
+5V GND
PROGRAM
LO memory Instruction
address byte Mnemonic Description
003 106 START, MOV B,M Read into register B the contents
of memory input port 200 003
~ A fy} N |
Se
STEP 1
Wire the circuits shown. To generate the two memory address select pulses
required, use either a decoder or use. the 74L20 4-input NAND gate circuits
shown below, which do not absolutely decode the 16-bit address bus and thus are
only demonstration circuits. , Don't forget the +5 Volt’ (pin 14) and GND (pin 7)
power inputs to the 74L20 chip. :
If you plan to acquire address bit A15 directly from the 8080A chip, we recommend
that you use a 74L20 chip rather than a 7420 in order to minimize fan-in. The
control signals MEMR and MEMW must be inverted befote being input into the 74L20.
The write pulse, 200 004, must be inverted prior to being input into the pair of
7475 latches. Address bit Al5 is available as pin 1 on chip Al3 on the MMD-1 computer.
STEP 2
Load the program into memory. Execute the program. Change the logic switch
settings and observe the output at output port 200 004. What happens.
_
®
?
.
When the data is input into the microcomputer, where is it temporarily stored?
In register B.
STEP 3
What changes to the program are necessary if you desire to input and output data
to and from register E?
Rev. 9/22/77
225
All that is necessary is a change in the instruction bytes at LO memory address
003 and 005:
Make these changes and demonstrate the operation of the new program.
sTeP 4
What would happen if you changed the instruction byte at LO memory address 005 to
but left the instruction byte at LO memory address 003 unchanged? Would program
execution change?
Yes. No longer would it be possible to input the logic switch data and then
output them to the memory output port. The problem is that such data is input
to register E where nothing further happens. Data output is from register B,
which is not changed by the modified program. We observed an output of 000 when
we tried this experiment.
STEP 5
Make the following program changes:
003 116 START, MOV C,M Read into register C the contents
of memory input port 200 003
»
‘
’
We observed a correspondence between the logic state of the output port and the
logic switch setting.
STEP 6
Now change the instruction byte at LO memory address 005 to a NOP instruction:
There no longer is a correspondence between the data at the memory input and
output ports. The reason is that we have eliminated the MOV instruction that
transfers the data byte from register C to register D, from which it is output.
sTeP 7
What registers may be used when the memory mapped 1/0 technique is used? Which
registers are involved with accumulator 1/0?
°
.
Memory mapped I/O may use any of the general purpose registers, including A, B,
C, D, E, H, or L, as the source or destination of data. Accumulator I/0 is
restricted to register A as the source or destination of data.
Save the 7475 and 8095 I/O port etrcuits and continue to the following experiment.
Var
EXPERIMENT NO, 2
MEMORY MAPPED I/O TO AND FROM THE ACCUMULATOR
PURPOSE
The purpose of this experiment is to test various memory reference instructions that
transfer data between input-output ports and the accumulator.
Use the memory input and output ports described in Experiment No. l.
PROGRAM NO, 1
LO memory Instruction
address byte Mnemonic Description
000 072 LOOP, LDA Load the accumulator from the input
port identified by the following
memory address
PROGRAM NO, 2
000 Load register pair B with the follow-
into two bytes
PROGRAM NO, 3
000 O41 LX£ Load register pair H with the follow-
ing two bytes
003 V6 LOOP, MOV A,M Load accumulator from input port iden-
tified by the contents of register
pair H
~
004 Ou4 INX H Increment register pair H
sTeP 1
In this experiment, you are provided with three different types of memory reference
instructions that can be used to transfer data between the accumulator and external
input-output devices. Even though the data transfer instructions have different
mnemonics, Program Nos. 2 and 3 are similar.
We assume that you have already wired the circuit described in Experiment No. 1.
Memory address pulses can be generated using the simple 74L20 gate circuits
provided in Step 1 of this experiment. Keep in mind, however, that the pair
of 7475 latches require a positive select pulse; thus, the output from the 74L20
chip must be inverted.
STEP 2
Load and execute Program No. 1. Change the logic switch settings at the 8095
Rev. 9/22/77
VAM
(74365) input port. What do you observe on the LED lamp monitors connected to
the two 7475 latches that comprise the memory output port?
You should observe a one-to-one correspondence between memory input and memory
output data. The response should be "instantaneous."
STEP 3
By changing the address bytes at LO memory addresses 004 and 005, would it be
possible for you to output the memory input data to one of the three lamp
monitor output ports on the MMD-1 microcomputer? Please explain your answer.
It would not be possible to convert any of the output ports on the MMD-1 micro-
computer to memory output ports ‘simply by modifying a pair of memory address
bytes in Program No. 1. The three output ports on the MMD-1 are hard-wired as
accumulator output ports. If you wish to convert them to memory output ports, you
would need to make a number of wiring changes on the printed circuit boards.
In addition, you would have to make a number of changes to the KEX monitor
program. We do not suggest that you do this.
The point we wish to make here is that both hardware and software are required
to determine the nature of an input-output port, i.e., whether it is a memory
I/O port or an accumulator I/O port.
sTeP 4
Load and execute Program No. 2. Change the logic switch settings to the memory
input port and note the correspondence between such settings and the output
from the pair of 7475 latches.
Why are the INX B and DCX B instructions needed in this program?
The memory input port has an address of 200 003, whereas the output port has an
address of 200 004. We use the INX B and DCX B instructions to change the
address existing in register pair B prior to the LDAX B or STAX B instruction.
In this way, we are able to address both ports. Memory I/O allows us to use
instructions which can modify a memory address. This is difficult to implement
with accumulator I/0.
step 5
and execute Program No. 3. Again change the logic switch settings to the
Load
21-50
memory input port and note the correspondence between such settings and the output
appearing on the eight lamp monitors.
What differences do you observe in the execution of this program when compared to
the execution of Program Nos. 1 and 2?
»
STEP 6
Comment on the differences and similarities of the LDAX B and MOV A,M instructions.
Both instructions are similar inthat the memory address is contained in a register
pair and that it is this addressthat specifies the memory address of the memory
input port. The only difference between the two instructions is the identity of
the register pair. For LDAX B, register pair B contains the address, whereas for
MOV A,M, register pair H contains the address.
STEP 7
Comment on the differences and similarities of the STAX B and MOV M,A instructions.
Both instructions are similar in that the memory address is .cbntained in a register
pair and that it is this address that specifies the memory address of the memory
output port. The only difference between the two instructions is the identity of
the register pair. For STAX B, register pair B contains the address, whereas for
MOV M,A, register pair H contains the address.
STEP 8
Why might you prefer the use of a STA or LDA instruction in preference to a STAX,
LDAX, MOV A,M, or MOV M,A instruction?
Save your 7475 output and 8095 (74365) input circuits for the next two experiments.
PURPOSE
The purpose of this experiment is to test the behavior of the INR M, DCR M, and
MVI M instructions on a typical memory output port.
PROGRAM NO. 1
LO memory Instruction
address byte Mnemonic Description
PROGRAM NO. 2
STEP 2
Load and execute Program No. 1. What do you observe on the output port lamp
monitors?
STEP 3
Change the value of the data byte at LO = 004 and execute the program once again.
For example, try the data byte 333. What do you observe on the output port now?
If you would repeat this process with other data bytes, you should conclude that
there is a one-to-one correspondence between the immediate data byte at LO = 004
and the output data on the output port once the program has been executed. When
a MVI M, MOV r,M or MOV M,r instruction is used, the address of the memory
location must be stored in registers H and L. They are loaded at the start of
the program with an LXI H instruction. ‘
STEP 4
Load and execute Program No. 2. What do you observe on the output port? What
did you expect to observe, the byte at LO = 004?
We observe an output byte of 000. You probably should observe the same thing.
We initially expected to observe the output byte, 112. The reasons why we did
not observe such a result are discussed in the next Step.
STEP 5
What operations must the microprocessor execute in order to successfully perform
an INR M instruction?
tahyhaere?
21-55
First, the current contents of memory location M must be input into the 8080A.
Next, they must be incremented by one. Finally, the incremented value must be
output back to memory location M. In other words, with a typical read/write
memory location, the INR M performs both a read and a write.
STEP 6
In memory mapped I/0, in order for you to successfully execute an INR M
instruction, what conditions must exist at the I/O port?
The port must be similar to that shown in Figure 21-6, i.e., you must be able
to read from and write into the port. Such a condition exists naturally in
read/write memory, but may not exist in memory mapped I/0 interface circuits.
STEP /
Why did we observe 000 as an output byte in Step 4 of this experiment?
We attempted to read from a non-existent memory location, 200 004, and input
the "default"' data byte 377 (due to the data bus floating to all logic 1s),
which was incremented and written into the memory output port as 000. The INR M
and DCR M instructions are unusual in that both a read and write operation
occur on a data byte.
STEP 8
If the 8095 (74365) three-state input port is still connected, change the
address decoding to the following:
74L20
Now the input port and output port have the same address. Change the instruction
bytes at LO = 003 and LO = 004 in Program No. 2 to NOP, 000. Set a value on the
logic switches and execute Program No. 2. What output appears on the lamp monitors?
PURPOSE
The purpose of this experiment is to demonstrate the execution of an AND operation
between a memory input port and the accumulator.
PROGRAM
LO memory Instruction
address byte Mnemonic Description
sTeP 1
Wire the memory input circuit shown in Experiment No. 1 if it is not already wired
on your breadboard.
STEP 2
Load and execute Program No. 1 with logic switch A at logic 0. Now set the
logic swtich to logic 1. What happens at output port 000?
STEP 3
Change the mask byte at LO = 004 to one of the following: 200, 100, 040, 020,
010, 004, or 002. Set all eight logic switches to logic 0. Execute the program
once again and test each logic switch until you detect the one that is not
masked. How do you know when you have found the right one?
sTeP 4
You can also test the other memory reference instructions, including
206 ADD M
216 ADC M
276 SUB M
236 SBB M
256 XRA M
266 ORA M
276 CMP M
The CMP M instruction does not affect any data or the contents of the accumulator
register. It only sets and clears flags.
STEP 5
Why would it be useful to be able to perform an arithmetic or logical operation
between a memory mapped input port and the contents of the accumulator?
Lira
a following questions will help you review memory mapped I/O techniques.
/2./ List several differences between accumulator I/O and memory mapped 1/0?
For example, what control signals are used, what instructions are used,
and what registers are used in the two I/O techniques?
3.) What is meant by the "absolute" decoding of the address bus in memory mapped
1/0?
4/ Why is absolute decoding of the address bus in memory mapped I/O important?
5. In this and preceding units, we have used the terms "device select pulse"
and "address select pulse." What is the difference between these two terms?
6. We have heard it stated that the reason one uses memory mapped I/O techniques
is to be able to transfer data between more devices than with accumulator I/0?
Do you agree? If so, why? If not, why not?
ANSWERS
1. Memory mapped input/output is a term associated with 6800, 8080A, and other
8-bit microcomputer systems. The I/O instructions are memory reference
instructions and the data transfer occurs, in the case of the 8080A chip,
between the I/O device and wany of the general purpose registers within the
8080A chip.
2. Im accumulator I/0, the control signals are IN and OUT, whereas in memory
mapped I/0, the control signals are MEMR and MEMW. Accumulator I/0 employs
only two 8080A instructions, IN and OUT. Memory mapped 1/0 employs any
memory reference instruction, e.g., MOV r,M, MOV M,r, MVI M, STAX rp, LDAX rp,
ANA M, ORA M, ADD M, and others. In accumulator I/0, data transfer occurs
between the I/O device and the accumulator register. In memory mapped 1/0,
data transfer occurs between the I/0 device and any of the general purpose
registers, such as B, C, D, E, H, L, or the accumulator.
3. All sixteen bits of the address bus are decoded using a suitable decoder
network so that each memory mapped 1/0 device is uniquely identified and cannot
be confused with a memory location in read/write memory or EPROM or accidently
addressed when program execution goes awry.
5. A device select pulse is generated when you apply the 8-bit device code from
the address bus and either IN or OUT, which are control signals, to a suitable
decoder circuit. An address select pulse is generated when you apply the 16-bit
address bus and either MEMR or MEMW, which are memory reference control signals,
to a suitable decoder circuit.
6. No, we do not agree. In most cases, 256 different input and 256 different
output devices or device select pulses are more than adequate for a microcomputer
system that includes an 8080A chip. A better reason for using memory mapped 1/0
techniques is to permit direct data transfer between the I/0 device and all of
the general purpose registers within the 8080A chip. In addition, the contents
of a memory mapped input port, can be added to, subtracted from, compared with,
or logically operated on the contents of the accumulator. a
22-1
UNIT NUMBER 22
INTRODUCTION
OBJECTIVES
Ce Define data logging and discuss the most important considerations in the
\\
V} development of a data logging system.
It should be clear that a microcomputer can be a data logger. Data from an instrumer
can be input into the accumulator and then stored in memory. At a later time, this
stored information can be read out in a variety of ways. Data logging will become
a common application for microcomputers.
Perhaps the most important questions that you should ask when you plan to log data
from an instrument are the following: (1) How many data points do you wish to log?
(2) How much time will it take to log all of these points? (3) How much digital
information is contained in a single data point? (4) What do you wish to do with
the logged data once it has been acquired? (5) Do you need short term or long
term data storage? We shall now discuss these questions.
Read/write memory is not, in general, suitable for the long term storage of data.
For one reason, read/write memory is volatile; if a power failure occurs, all of
the data will be lost. Core memory is not volatile, but on the other hand it is
relatively expensive and generally not suited for long term storage of data unless
the amount of data stored is limited. The best data storage devices, as indicated
above, include cassette tape and floppy disks. A high-quality tape cassette can
store as much as 500,000 bits of information on a single cassette that costs no
more than $10. Hardware costs for floppy disks are decreasing every year. The
development of highly sophisticated LSI interface chips for floppy disks should
reduce costs still further. Such chips will soon be available from Intel, Texas
Instruments Incorporated, and Motorola.
Rev. 9/22/77
L275
HOW MUCH INFORMATION IN A SINGLE DATA POINT?
A typical data point is usually a three- or four-BCD digit number that also contains
both a decimal point, or range, as well as a sign. Usually, the decimal point or
range is fixed and the sign is positive, but such is not always the case. New
digital devices are increasingly incorporating an autoranging capatiliby, which
means that the digital instrument decides where to place the decimal point.
Plan on a data point that contains at least sixteen bits of digital information.
To obtain the total memory capacity required, multiply sixteen by the number of
data points. Thus, for one hundred data points, 1600 bits of read/write memory
would be required. Frequency meters typically have many more bits per data point.
For example, a seven-digit frequency meter has at least 28 bits per data point.
Some logged data is only "raw" data that must be manipulated and interpreted in
order to produce a useful final result. One example would be the conversion of
a digital voltage to force. In such cases, the logged data will require mathe-
matical computations that should be performed soon after the data is acquired.
With data that requires additional mathematical treatment, we recommend that
you keep the data in digital electronic form until it can be treated. Read/write
memory, magnetic tape, and magnetic disk are all suitable for such a purpose.
The printing of data is a form of long-term data storate. It certainly is the
least expensive type of long term storage around, but you pay a penalty in that
you must consume time to convert it back to digital electronic signals.
If the clock in Figure 22-1 operated at a frequency of 1 Hz, you would Store one
or two values in all sixty-four memory locations. The proper way to perform the
above experiment is to use a clock input that has a frequency of at least
20 kHz. We obtained useful results using a clock that had a frequency of 90 kHz.
+5V GND
D7
D6
D5
8-BIT D4
INPUT
D3
BUFFER
D2
Dl
DO
rwadnoomneot
CLOCK
or Input device
+5V GND
Figure 22-1. Simple data logging circuit that employs a pair of cascaded 7490
decade counters.
points
It is not often that you will need to log data at a rate of 54,000 data
per second. A more common situation is a data logging rate of one byte per second.
a time delay
The only change required in the First Program is the insertion of
Thus:
loop that has a duration of approximately one second.
LO memory Instruction
address byte Mnemonic Description
It will require 1.0000345 seconds to log each data point, or a total of 64.0022
seconds to log all sixty-four data points. Clearly, the additional time required
to perform the DCR, IN, CALL, INX, and JNZ instructions is negligible when compared
to the one-second time delay. A 10 ms time delay subroutine will permit you
to log data at rates between 23.4 data points/minute and 99.7 data points/second
simply through a change in the value of the timing byte at LO = 012.
THIRD PROGRAM: OUTPUT FROM A DATA LOGGER
Let us assume that you have stored sixty-four data points in read/write memory
starting at HI = 003 and LO = 100 and now wish to output each point at the
rate of one data point/second to an appropriate latch circuit such as that shown
in Figure 20-6, 20-10, 20-12, or 20-13. What type of program is required? The
answer to this question is that a program that is almost identical to the Second
Program is needed. Only three instruction bytes in the Second Program need to be
modified:
Otherwise, the Second Program can be used as written. For example, in the second
program, you have already provided instruction bytes to (a) identify the memory
location M, (b) establish the number of data points located in read/write memory,
(c) initiate a one-second time delay between each data point, and (d) halt after
all sixty-four data points have been output. As a dividend, you can repeatedly
execute the modified Second Program, which we shall now call the Third Program,
starting at HI = 003 and LO = 000. The Third Program is now an output program that
does not modify the contents of read/write memory.
straight
While the concept of using input devices to input eight bits of data is
forward, once you have input the data you can perform interesting programming
tricks to take advantage of the power of the 8080A chip. For example, assume
that the input data byte is the 8-bit ASCII code froma standard ASCII keyboard
that has TTL output. Each time a new ASCII byte is input, it is tested to determine
ASCII
whether or not it is the ASCII equivalent to the letter "E", which has an
code of 305. If it is an "E", the ASCII byte is output and also stored in read/write
memory. If not, the. program will immediately loop back to the IN instruction and
input 2 new ASCII byte. The simple flow chart for this program is shown in
Figure 22-2.
LO memory Instruction
address byte Mnemonic Description
010 425 OUT Output the ASCII code for the letter
Mi yt
The compare immediate, CPI, instruction at LO = 003 and LO = 004 permit you to
compare the ASCII byte 305 with the contents of the.accumulator without alterning
the accumulator contents. Only the flags are changed. If the ASCII byte for
the letter "E" and the accumulator contents are ideftical, the zero flag is set
to logic 1; otherwise, the zero flag is reset (cleared) to logic 0. The condition
of the zero flag is then tested by the JNZ instruction to determine whether or not
to continue looping. 2
We have observed that the compare instruction is subtle and, on occasion, difficult
to use properly. As indicated in Unit Number 18, the two flags that are tested |
after a compare instruction, such as CPI, are the zero flag and the carry flag.
Four different conditional jump instructions can be inserted at LO = 005 in the
above program. The questions that are implied by such instruction bytes can be
summarized as follows:
Instruction byte
at LO = 005 Implied question
We have tested the Fourth Program using each of the above four conditional branch
instructions. With the ASCII code equivalents to the letters "D", "E", and "F",
the program worked as expected.
Figure 22-2. Flow chart for the Fourth Program, which tests an input character
to determine whether or not it is the ASCII character "E". When an "E"
is input, the program outputs the character, stores it, and then comes
to a halt.
22-1)
In the second program in this Unit, a one second time delay loop was used to slow
down the rate at which the microcomputer logged data from an input device. The
use of such a loop represents a very inefficient application of a microcomputer,
since the microcomputer could perform other‘useful functions during the one second
interval. » Other methods of generating one second time delays include the
following:
o A real time clock based upon a high frequency crystal oscillator circuit.
If the microcomputer has no other functions to perform between data points, the
use of a wait loop is quite acceptable.
Rev. 9/22/77
es ah
INTRODUCTION TO THE EXPERIMENTS
Some of the above experiments employ more expensive integrated circuit chips. We
encourage you to be careful when using such chips.
DLE she:
(SNS
EXPERIMENT NO, 1
LOGGING FAST DATA POINTS
PURPOSE
The purpose of this experiment is to operate a simple 8080A-based data logger that
can log data at high data rates.
7490
+5V GND
D7
ox
] D6
F D5
8-BIT ¢ D4
INPUT
BUFFER D D:
c D2
B DI
A DO
CLOCK
or Input device
PULSER select pulse
IN 004
+5V GND
1Z
PROGRAM
LO memory Instruction
address byte Mnemonic : Description
sTeP 1
Study the schematic diagram of the circuit. Observe that a pair of cascaded 7490
decade counters are input into an input buffer. Two buffer circuits are given in
Unit Number 20, Figures 20-17 and 20-18. We would recommend the use of the pair
of 8095 chips since they are less expensive and, in our experience, less subject to
being damaged. Obtain the negative device select pulse from one of the decoder
circuits described in Unit Number 17.
Wire the circuit required for this experiment. The clock frequency should initially
be extremely slow, approximately 1 Hz.
STEP 2
Load the program into read/write memory starting at HI = 003 and LO = 000.
STEP 3
Execute the program at the full microcomputer speed.
Now go to memory location HI = 003 and LO = 100 and step through read/write memory
up to HI = 003 and LO = 200. What do you observe? Why?
‘
We observed a reading of 120, in octal code, for all of the memory locations starting
at LO = 100 and ending at LO = 177. Such a reading corresponds to an 8-bit binary
word of 01010000, which is equivalent to the decimal number 50 in packed BCD. The
microcomputer executed the program so quickly that only a single output from the
pair of 7490 decade counters was input into all memory locations.
STEP 4
What do we mean by the term, "packed BCD"?
Binary coded decimal (BCD) is a four-bit binary code for the decimal digits 0 through
9. Two BCD digits comprise a total of eight bits, which can be input as such into
an 8-bit microcomputer such as the 8080A. By "packed BCD," we mean that an eight-bit
data point contains two four-bit BCD digits.
STEP 5 .x
Execute the program at the full microcomputer speed several times. Observe what
data you input starting at memory location HI = 003 and LO = 100. What do you
conclude? 3
In each case, we input only a single pair of BCD digits into read/write memory.
STEP 6
We concluded previously in this Unit that it required 37 cycles to log a single
8-bit data point. If a microcomputer is operated at a clock rate of 750 kHz,
how much time is required to log a single point? What is the data logging rate,
in bytes/second?
22-15
At 750 kHz, a cycle lasts for 1.333 microseconds. Thus, 37 cycles corresponds to
49.3 microseconds and a data rate of 20.27 kHz.
sTeP /
If the clock input to the pair of 7490 counters has a frequency of 20 kHz, what
can you conclude about the data stored in read/write memory starting at HI = 003
and LO = 100?
100 106 46
101 107 47
102 110 48
103 ala 49
104 120 50
105 20 Sill
106 22 52
107 123 53
110 124 54
Bean 125: eS)
PZ 126 56
STEP 8
20 kHz or
Set the clock frequency of the clock input to the 7490 counters to
slightly less. Frequencies ranging between 5 kHz and 20 kHz would be quite
acceptable. Execute the program once. Observe the data stored starting at
HI = 003 and LO = 100. What do you conclude?
The 7490 counter was stored sequentially in sixty-four read/write memory locations
starting at HI = 003 and LO = 100. Our first data point was octal 070 and our
last data point was octal 166.
STEP 9
If 49.33 microseconds are required to log a single data byte, and if the first
data byte is 070 and the final data byte is 166 from a two-decade counter circuit,
what is the frequency of the counter?
2»
The total time required to log 64 data bytes is 49.33 us + 64 points = 3157.12 us.
The number of counts between the first and last data byte is,
In other words, a total of 118 - 56 = 62data bytes were logged during 3.15712 ms.
The input clock frequency is therefore,
19.64 kHz
sTeP 10
Calculate the input clock frequencies to your 7490 decade counter circuit using
the calculation procedure described in the above step.
We obtained the following results, where the counts are given in decimal:
09
20
ce
36
Rev. 9/22/77
22-17
EXPERIMENT NO, 2
LOGGING SLOW DATA POINTS
PURPOSE
The purpose of this experiment is to operate a simple 8080A-based data logger that
can log data at low data rates.
PROGRAM
LO memory Instruction
address byte Mnemonic Description
step 1
The circuit is identical to that used in the preceding experiment. Load the new
program into read/write memory starting at HI = 003 and LO = 000.
STEP 2
Execute the program. Remember that it will now require one second per data point,
or a total of 64 seconds before all data points are logged and the program comes
to a halt. Your clock input to the 7490 counters should be approximately 1 Hz.
Go to memory location HI = 003 and LO = 100 and step through read/write memory.
What do you observe?
STEP 3
Now make the following changes to the above program and wire
up an output port 002
if one is not already available on your microcomputer.
STEP 4
Repeat steps 2 and 3 as often as you desire. Each time you wish to input data
into the memory, you must make certain that the proper instruction bytes are
present at memory locations LO = 005 through LO = 007.
STEP 5
Rather than modifying the program each time, it probably would be more convenient
to load a separate output program starting at HI = 003 and LO = 030. Assuming
that you would do so, what would the addresses of LOOP and LOOP1 be?
LOOP would be at HI = 003 and LO = 035 and LOOP1 would start at HI = 003 and LO = 043.
EXPERIMENT NO, 3
DETECTING AN ASCII CHARACTER
PURPOSE
The purpose of this experiment is to wire an interface and execute a program that
demonstrates how to detect the ASCII character, "E".
LOGIC
SWITCHES
LOGIC
SWITCHES
+5V GND
PROGRAM
LO memory Instruction
address byte Mnemonic 4 Description
007 325 ; OUT Output the ASCII code for the letter
"E", which is contained in the
accumulator
sTeP 1
Wire the interface circuit shown in the schematic diagram. Load the program
in read/write memory starting at HI = 003 and LO = 000.
STEP 2
Set the logic switches to the 8095 three-state buffer chips to the ASCII
equivalent of the letter "D", i.e., 304 in octal code or 11000100 in binary.
Fxecute the program at the full microcomputer speed. What happens?
In our case, nothing happened. Output port 002 did not exhibit 305.
Rev. 9/22/77
22-22
STEP 3
Set the logic switches to- 306 while the microcomputer is running. Make certain
that you do not set it to 305, even momentarily! Any change yet?
No. The reason is that so far a 305 input has not been. detected. Such being
the case, the program continues to loop back to START.
STEP 4
Now change the logic switches to 305. What happens?
The ASCII code fo "E", 305, is output to port 002 and the microcomputer comes
to a halt. It does so in response to the query posed by the instruction byte
at LO = 004:
STEP 5
Change the instruction byte at LO = 004 to
Set the logic switches to 305 and execute the microcomputer at its full speed.
What do you observe?
The program continues to loop. During each loop, it detects the character "E".
STEP 6
Now set the logic switches to 304 and execute the program once more. What happens?
STEP /
You may also wish to substitute either of the following instruction bytes at
LO = 004:
Oye
See the text in this unit for a discussion of these two instruction bytes.
22-214
EXPERIMENT NO, 4
WIRING A BUS MONITOR
PURPOSE
The purpose of this experiment is to wire a pair of circuits that you may find
useful in subsequent experiments: (1) a three-octal-digit bus monitor, which
permits yqu to monitor all information that passes over the bidirectional data
bus, and (2) a latched 7490 counter, which permits ae to detect and count
different types of synchronization pulses.
FUNCTION
REAR VIEW PIN (082-7
eee 5082-7340
and 7302 Hexadecicnal
Numeric lexadecima
co oP oR aD }+—
1 Input 2 Input 2
| LUMINOUS
()] L INTENSITY 2 Input 4 Input 4
32 CATEGORY
rey Pap 33
aif
Input 8 Input8
Nie ot 4 Decimal
| |
Blanking
+ DATE CODE _| point control
t PIN 1 KEY > Latch |_Lateh
as enable enable
fe 6 Ground Ground
y Vee Vee
Input Input
— ~
HP 5082-7300
Latch Enable
+ 5V GND
Latch Enable
step 1
Wire the circuits shown above, preferably on a single SK-10 socket. You will find
them useful as monitors of device select pulses and control signals as well as
the data that appears on the bidirectional data bus.
STEP 2
The Hewlett-Packard 5082-7300 display contains a four-bit latch of the 7475 type
that is enabled by a logic 0 STROBE pulse. What does this mean?
The 7475 latch is a D-type latch that follows the input when the latch is enabled.
Thus, a logic 0 applied to the HP 5082-7300 means that the output will be the
same as the input as long as the STROBE input remains at the logic 0 state.
Latching of input data occurs on the positive edge of the STROBE input pulse.
STEP 3
A variety of control and other signals can be used as the STROBE input to the
HP 5082-7300 latch/displays that are connected to the bidirectional data bus,
DO through D7. List some of these signals and explain what information they
permit you to latch from the data bus.
Rev, 9/22/77
22-25
Some useful signals include:
We shall call the three-digit circuit that latches the bidirectional data bus,
DO through D7, a bus monitor, since it permits you to monitor all information
that appears on the data bus. You will use this monitor in subsequent experiments,
so save it.
STEP 4
The second circuit in this experiment consists
of sa Hewlett-Packard latch/display
wired to the output of a 7490 counter. What is the function of this circuit?
PURPOSE
o—_-© 98,
e———— ODE
00, o }
Dl, oO
+—_ ¢———_-o 0,
DORIS <j
-——*
PIN NAMES
: a rg ; }— 0B,
; =
|| Diy Dt, DATA BUS
ieee OB; | BIDIRECTIONAL
| DATA INPUT
00,0
;
Ie
q | BieN cs
0 [0 jo-oe
DO,-00,| DATA OUTPUT d [0 |p8 = Do
1 IGHINEED Ate
i pen |1 DATAIN ENABLE [fasaiealtsis | |
| DIRECTION CONTROL
cs CHIP SELECT
DIEN
LOGIC
SWITCHES DISPLAY +,
LATCH/
eo 22/iT
22-28
PROGRAM
LO memory Instruction
address byte Mnemonic Description
sTeP 1
Wire the circuit shown. Load the program in read/wrtte Memory starting at HI = 003
and LO = 000.
STEP 2 2
Execute the program. What do you observe on output port 002 and also the latch/
display as you change the logic switches from 0000 to 1001?
The least significant four bits in output port 002 and the latch/display exhibit
the same reading as the logic switch input to the 8216 chip. The most significant
four bits in output port 002 all remain at logic 1. The program reads the logic
switch data using the MOV A,M instruction, and then outputs the accumulator contents
to the 8216 latch/display using the MOV M,A instruction. Finally, the OUT 002
instruction outputs the accumulator contents to the output port.
22-29
A a el
Do BOee Ue Cc a
Fill in the following truth tables for the DIEN and CS inputs to the 8216 chip.
0
ib
The first truth table indicates whether or not the chip is enabled:
i 0 Chip enabled
0 if Chip disabled (high impedance state)
The second truth table indicates the direction of data transfer through the chip:
Not allowed
Memory read
Memory write
Memory write
The final truth table summarizes the operation of the 8216 chip:
In other words, when MEMR and CS are both at logic 0, the 8216 serves as an
input port. When MEMW and CS are both at logic 0, the 8216 serves as an output
port. MEMR and MEMW cannot both be at logic 0 since the 8080A microprossor
cannot read and write at the same time. The MEMW = MEMR = O state is never
observed by external control logic:
STEP 4
Is this chip useful as an I/O port?
PURPOSE
The purpose of this experiment is to demonstrate the use of the 8255 programmable
peripheral interface chip as an accumulator I/O port.
LOGIC
SWITCHES
LOGIC
SWITCHES
LAMP
MONITORS
LAMP
MONITORS
PROGRAM
LO memory Instruction
address byte ~ Mnemonic Description
DISABLE FUNCTION
x< x x x< DATA BUS = 3-STATE
= =
a
oO oO ILLEGAL CONDITION
The pin configuration and block diagram for the 8255 chip are:
PIN CONFIGURATION
8255 BLOCK DIAGRAM
——— «sv
POWER
SUPPLIES
———_—> GND)
GROUP
A
CONTROL
PBO 18 23 1) PBS
step 1
Study the truth table for the three I/O ports and the control register within the
8255 chip. Address bus bits A-0, A-1, and A-7 are used to select the specific
port_or register desired. The control signals IN and OUT are connected to RD
and WR, respectively. Therefore, the eight-bit device code, AO through A7,
identifies the particular I/0 device associated with an IN or OUT instruction.
Since the address bus is not absolutely decoded, address bits A2 through A6 can be
either 0 or 1. In defining the device codes, we have let these bits be logic 0.
Port A
0 Port B
Port C
205 Control register
In the program, the instruction bytes at LO = 003, 005, and 007 are all device
codes.
STEP 2
Wire the circuit shown. Use address bus bit A-7 for the CS input, IN for the RD
input, and OUT for the WR input. This use of the chip is an example of accumulator
1/0.
STEP 3
Load the program in read/write memory starting at HI = 003 and LO = 000. What
do you think the significance of the instruction byte at LO = 001 is?
As stated in the program, it is a control word that establishes the mode 0 operation
of the 8255 chip and whether port A, port B, and port C are input or output ports.
In this case, the control word corresponds to ports A and C'being input ports and
port B being an output port,
STEP 4
Execute the program at the full microcomputer speed. While the microcomputer
is running, change the logic switch settings and observe the output at port B.
What happens?
Port B displays the logic switch input to port C. Any changes in the logic switch
settings occur essentially instantaneously at port B. This behavior demonstrates
that we have input data into the accumulator and output it from the accumulator
to port B.
STEP 5
Change the control word at LO = 001 to 215. Execute the program at the full
microcomputer speed and observe whether or not there is any output at port B
22-5
when you change the port C logic switch settings.
CONTROL WORD =7
D;-0, <——_——_»
STEP 6
Finally, change the control word at LO = 001 to 20], which corresponds to the
following situation,
CONTROL WORD =1
D,” De Ds 0 Da 07 8; Dg
yD) ~
Note that now, only four of the bits in port C are input
bits. Remove the logic
switches from bits PC4 through PC7. Change the control word at LO = 001 and
execute the program at the full microcomputer speed.
What do you observe?
22-36
The output at port B mirrors the input at port C bits PCO through BCS. yAseiar
as our circuit is concerned, port B is once again an output port.
STEP / a ‘
The 8255 ‘chip is an interesting but somewhat complicated interface chip that
is manufactured by the Intel Corporation. For further details, obtain a copy
of the recently published "8080 Microcomputer Peripherals User's Manual" and
a copy of application note AP-15, "8255 Programmable Peripheral Interface
Applications." The 8255 chip will be the subject of Bugbook IV, which is still
being written.
Save this circuit for the following experiment, in which you use the 8255 chtp
as a memory I/O device.
EXPERIMENT NO, 7
MEMORY MAPPED 1/0 USING THE 8255 CHIP
PURPOSE
The purpose of this experiment is to
demonstrate the use of the 8255 programmable
peripheral interface chip as a memory
I/0 port.
These have been given in the preceding experiment, in which you were asked to save
the circuit
PROGRAM
LO memory Instruction
address byte Mnemonic Description
000 O41 {x02 Load register pair H with the following
two bytes
STEP 2
Load the program into read/write memory starting at HI = 003 and LO = 000.
STEP 3
Execute the program at the full microcomputer speed. Vary the logic switch settings
and observe what happens at port B. What can you conclude?
The logic switch input at port C appears as a lamp monitor output at port B.
STEP 4 ~
Change the control word at LO = 004 to 213 and then to 201. Execute the microcomput
in each case at the full microcomputer speed. Explain your observations at port B
in the space below.
With the control word of INNS port B no longer functions as an output port. For
control word 2()], port B is again an output port, but only port C bits PCO through
PC3 are input bits. Bits PC4 to PC7 are output bits with this second control word.
sTeP 5
Change the LO address byte at LO = 014 to 013. Execute the program at the full
microcomputer speed with 74] as a control word at LO = 004. Can you conclude that
the output to port B is latched?
Yes, the output to port B is latched, since any logic 1 bits remain at logic 1
despite the fact that no additional input to the accumulator occurs from port C.
Only the initial logic switch settings are latched. All subsequent changes are
ignored by the program.
22-3
EXPERIMENT NO, 8 39
INTERFACING A DIGITAL-TO-ANALOG CONVERTER
PURPOSE
The purpose of this experiment is to
test a simple parallel input program
AD7522 10-bit buffered, multiplying, digital for the
-to-analog (D/A) converter.
PROGRAM
LO memory Octal
address instruction Mnemonic Comments
000 04? START, SHLD Strobe ten bits of digital data into
the AD7522 DAC shift registers.
001 004 004 HI = 000 and LO = 004 is the memory
I/O device code for the LBS input to
002 000 000 the DAC. HI = 000 and LO = 005 is
the memory I/0 device code for the HBS
input to the DAC. [NOTE: We can use
these device codes since memory block
HI = 000 is EPROM.]
DISCUSSION
| NOz rovoroal
40
1OOvNI 408440 isnf[pD
DILWWSHOSWVYOVIC
40 LINDYID
22-4
OO!4
uIDS 4snfpD
AS=
0 ua
AO!lL~-0O
za
90
{OOPNI
ccGldVv
OV
22-l\]
The 10-bit digital-to-analog converter word consists of the data bits DBO through
DB7 strobed into the AD7522 8-bit shift register with the aid of strobe pulse LBS,
and also data bits DB8 and DB9 strobed into the AD7522 with the aid of strobe
pulse HBS. Bits DB8 and DB9 appear on the microcomputer bidirectional data bus
as bits DO and Dl.
The details of the Analog Devices AD7522 DAC is described in "Bugbook VII. Micro-
computer Conversion Devices," which first appeared during the summer of 1977.
In the Appendix to this experiment, we provide additional data on the AD7522
DAC, courtesy of Analog Devices, Inc.
fa We by,
vcc DGND voo VREF AGND
fe
BELLEED!
MsB
tot
DAC REGISTER +40 Loac
LETT
SRO
(MSB) DB9
pes ¢
aia
087
pB6 2BIT
DBS SHIFT REGISTER 8.8IT SHIFT REGISTER
(SERIAL MODE) (SERIAL MODE}/
oan
LATCH (PARALLEL MODE)
AD7522 (PARALLEL MODE)
step 1
Study the schematic diagram of the circuit that you will wire. When we performed
this experiment, V was connected to a small Volt-ohmmeter (VOM). The digital
ground, DGND, should be connected to the analog ground, AGND. Since you are using
memory 1/0 techniques, MEMW should be used instead of OUT.
To facilitate the wiring of this circuit, we have developed a small Outboard ® >
a block diagram of which is shown below. If you have this Outboard, wire the
circuit as shown. Inputs 003, 004, and 005 are the decoded output channels
obtained from an appropriate LO address byte decoder circuit.
STEP 2
Wire the DAC circuit and load the program shown at the start of this experiment
into memory starting at HI = 003 and LO = 000. If you are executing this program
on the MMD-1 microcomputer (also known as the Dyna-Micro), the 10 ms time delay rou-
tine TIMEOUT is already loaded in the Keyboard EXecutive EPROM. If you are
using some other 8080A-based microcomputer, we have provided a listing of DELAY
in the Appendix to this experiment.
Rev. 9/22/77
20-110
+12V -l2v
D4 DAC
AD/S22 our
DAC
SRI SRO
Address
codes
ooo eal
005 1 HBS
OUTBOARD ®)
03 LDAC
MEMW OUT, MEMW
fe) Sc8
0 SPC ~
Figure 22- 3. Schematic diagram of the AD7522 DAC Outboard, which contains all
of the necessary analog and digital circuitry needed to perform this
experiment (see Schematic Diagram of Circuit).
STEP 3 x
Execute the program with the Volt-ohmmeter connected to the output of the DAC.
What do you .observe? 2
ve
Execute the program once again. What change in behavior of the VOM do you
observe? Why?
Now the VOM exhibits a slow and steady decrease from + 5.6 Volts to 0 volts,
at which time the needle returns to + 5.6 Volts and repeats the process. We
decrement the value instead of incrementing it as before.
STEP 5
Remove the time delay subroutine by making the following program changes:
The DCX H instruction should still be present. Execute this modified program
and explain what you observe on the VOM.
We observed that the VOM needle oscillated about the voltage reading +2.75 Volts.
The magnitude of the oscillations was approximately +0.02 Volts. On a digital
multimeter, the readings varied between +2.83 and +2.91 Volts. In other words,
the rather fast linear ramp could not be followed by either meter; only an average
voltage reading was observed.
The negative linear ramp was easy to observe on an oscilloscope set to a sweep
rate of 10 ms/division.
Save your interface etreutt and continue to the following experiment. Additional
information for this experiment ts gtven in the Appendix on the following page.
2-ty
APPENDIX TO EXPERIMENT NO, 8
LO memory Octal
address instruction Mnemonic Comments
300 &
WN PUSH D Push contents of register pair D on
stack
On the following two pages we provide a listing of the individual pin functions on
the AD7522 digital-to-analog converter. We would like to acknowledge Analog
Devices, Inc. for the use of this information.
22-45
ew:MNEMONIC DESCRIPTION
Note 1: Logic “1” applied to a data bit steers that bit’s current to the
IOUT1 terminal.
22-H6
EXPERIMENT NO, 9
A STAIRCASE-RAMP COMPARISON ANALOG-TO-DIGITAL CONVERTER
PURPOSE i
The purpose of this experiment is to use the staircase ramp compartson technique
to convert an AD7522 10-bit buffered multiplying digital-to-analog converter into
an analog-to-digital converter (ADC) with the aid of an LM311 comparator.
Dual-In-Line Package
input
9 ourpur
maLance i 7 Bal ANCE
‘ STAnee
v
NOTE Pin 4 connected 10 case
TOP view Note: Pin 6 connected to boriom of package
Sie
Order Number LF111H, LF211H Saat
or LF311H Order Number LM311N Order Number LF111D, LF211D “S
or LF311D
shown below. :
Rev. 9/22/77
22-1\7
PROGRAM
This program is written to be stored in EPROM, starting at HI = 001 and LO = 107
and terminating at HI = 001 and LO = 210. An asterisk, * , is provided to indicate
those absolute memory locations which must be
changed to relocate the program
elsewhere in memory. Since most EPROM programmers operate in hexadeci
mal code,
the program is also listed in hex.
LO memory Instruction
address Octal Hex Mnemonic Comments
PURPOSE
»
The purpose of this experiment is to use the staircase ramp comparison technique
to convert an AD/522 10-bit buffered multiplying digital-to-analog converter into
an analog-to-digital converter (ADC) with the aid of an LM31l comparator.
Dual-in-Line Package
esis OM
: Ni ) 2 NC
7 oa taunt 7 y uance
NOTE Pin 4 connected to case ove
TOP VIEW
Note. Pin 6 connected to bottom of package
Order Number LF111H, LF211H rar view
or LF311H Order Number LM311N Order Number LF111D, LF211D
or LF311D
The DAC circuit has been shown in the preceding experiment. The output from the
DAC, Mt ee » should now be connected to input pin 2 of the LM311 comparator, as
shown below.
&
IK
Rev. 9/22/77
22-|\7
PROGRAM
This program is written to be stored in EPROM, starting at HI = 001 and LO = 107
and terminating at HI = 001 and LO = 210. An asterisk, * , is provided to indicate
those absolute memory locations which must be changed to relocate the program
elsewhere in memory. Since most EPROM programmers operate in hexadecimal code,
the program is also listed in hex.
LO memory Instruction
address Octal Hex Mnemonic Comments
120 04? 22 AGAIN, SHLD Strobe ten bits of digital data into
the AD7522 DAC shift registers
ie
#
phic)
REVIEW
|2./ What are the important considerations in the design of a data logger?
3. How would you detect a specific ASCII character that is input into the
microcomputer?
sTeP 5
Vary the potentiometer setting and test the program for the measurement of voltages
between 0.0 Volts and +2.5 Volts. Do you observe any. difficulties?
»
3. How would you detect a specific ASCII character that is input into the
microcomputer?
ANSWERS
1. A data logger is an instrument that automatically scans data produced by
another instrument or process, and records readings of the data for future use.
Die Basically you must determine how many bits of memory are required to store
the data, whether such storage is short term or long term, and how many data
points per second are to be logged. It is not difficult to exceed the capa-
bilities of an 8080A-based microcomputer (without DMA, or direct memory access)
in high-speed data logging applications.
3. You would input the ASCII character into the accumulator and then compare (CMP)
the accumulator contents with the specific ASCII code of the’ desired character.
The ASCII code could be stored in registers B, C, D, E, H, or L, or ina
memory location. When the desired character is detected, the zero flag goes
to logic l.
(*.| Time delays can be software or hardware generated. A software time delay
— loop can generate delays as short as twenty to thirty microseconds and as long
as hours or even days. Hardware methods of generating time delays include the
use of a real time clock, probably operating at 60 Hz, that interrupts program
execution, a crystal based real time clock, or a programmable interval timer.
UNIT NUMBER 23
INTRODUCTION
Flags and interrupts are useful interfacing techniques that find broad application
in any type of computer interfacing. This Unit explores their use with 8080A-based
microcomputers and provides typical hardware and software examples. Interrupt
timing problems are also discussed.
OBJECTIVES
At. the completion of this unit, you will be able to do the following:
oO Write flag servicing software for one or more flags and explain how
such software is used.
Explain some of the timing problems associated with both flags and
interrupts.
WHAT IS A FLAG?
We have seen in previous units that it is fairly easy to transfer data in and
out of a microcomputer using the IN and OUT instructions and some hardware.
In many cases the computer will be ready for data to be input much faster than
the data source can generate it. We can also have the ‘case of an output device
which may be much slower than the computer. For example, a teletypewriter can
print only 10 to 30 characters per second, whereas a typical 8080A system can
output a new character as fast as every 5 to 10 microseconds. Clearly, some
method of synchronization is needed so that the computer responds only when an
input device actually has data ready or when an output device needs more data.
We need some sort of signal to indicate the state or status of our devices.
This is called a flag.
You have already used some flags that are internal to the 8080A microprocessor
chip. These are the zero flag and the carry flag which, along with the sign,
parity, and auxiliary carry flags make up the five internal 8080A flags that
are useful to us in software. These flags, excluding the auxiliary carry flag,
are the basis for the branching or transfer of control instructions. Note that
the flags are cleared (logic 0) or set (logic 1) in response to various software
instructions. This is consistent with our definition, since the software performs
an operation, e.g., ADD, ROTATE, OR, etc. It is important to note that flags are
used to detect conditions and to remember what condition has occurred.
External flags are used to indicate conditions of input/output devices and other
digital systems or devices which the microcomputer must control. Listed below
are some of the types of conditions which flags are used to indicate:
Let us consider a typical interfacing example and see how a flag can be used. We
shall interface an 8-bit ASCII keyboard to our microcomputer by constructing an
8-bit input port. You should be able to do this based upon your experience with
device decoding and three-state input ports. For additional details, see Unit
Numbers 17 and 20. Our interface circuit is shown in Figure 23-1. A typical
Rev. 9/22/77
flow chart that illustrates how you would input characters and compare them to
the letter "E" is shown in Figure 23-2.
+5V GND
D7
D6
D5
04
ASCII D3
ENCODED D2
DI
KEYBOARD OMABDNST
PONV DO
3 : YOUPrWOAOMNYAYT
49”
on
= o
Figure 23-1. Typical keyboard input circuit based upon the use of an 8212 chip
as a three-state input port.
YES
OUTPUT 377
Figure 23-2. Software flow chart for detecting the ASCII letter, "E".
When the ASCII code for the letter "E", 305,, is finally input and detected by
the microcomputer, the software will output all logic 1s, or 377,, to an output
port, in this case, device 001. If there are LEDs at this output port, they
will all be lit when an "E" has been detected. The software needed to accomplish
this is as follows: .
LO memory Instruction
address byte Mnemonic . Description
This software will continuously input data from the keyboard even when a key is
not activated (and thus no real code is present). We would prefer to sense the
key closure and have the computer only input the information when the code is
valid. Most keyboards provide a pulse or level that indicates when data is ready
or valid. This status signal is a flag. For example, in the case of our key-
board, it is a one microsecond pulse, called VALID, which indicates that a valid
code is present. We could input this pulse directly into the microcomputer and
test to see if it were present, but in all likelihood the microcomputer would
miss it since the pulse is so short. We need some means of stretching or holding
the pulse until it can be sensed by the microcomputer. The solution is a flip-flop,
which provides the means of holding the flag information. A typical flip-flop |
flag is shown in Figure 23-3 for both the 7474 and 7476 type flip-flops.
The VALID pulse from the keyboard is used to set the flag, which may then be sensed
IN OOS
To data bus
KEYBOARD
tu | psec pulse
IN O17
D3
82l2
Status To data bus
Register
OUT O65
Simplified circuit that demonstrates how the VALID flag from the
Figure 23-4.
keyboard is tested by the 8080A microcomputer.
OUT OI6
OUT O15 TO DATA
BUS
EMPTY IN O27
TO PROCESS
SIGNAL INPUT
SIGNAL INPUT
GND
CLEAR CLEAR
Figure 23-3. Typical flip-flops used as flags. The 7476 flip-flop is a pulse-
triggered device while the 7474 flip-flop is a positive-edge-triggered
device.
As a second example of the use of flags, we wish to control the level of solvent
in a storage tank. An empty/full switch and a digitally controlled valve are
available. The system is schematically represented in‘ Figure 23-5. Two OUT
device select pulses are used to control the valve through the use of a flip-flop,
a buffer, and a solid-state relay, a technique that has been previously shown in
Figure 17-8 in Unit Number 17. As a precaution, an overflow <indicator has been
added that outputs a logic 1 when the solvent is about ready to overflow, and a
logic 0 when there is no danger of overflow. The level switch is at a logic 1
when the solvent reaches the full point, and at a logic 0 when it reaches the
empty point. Since the overflow and level indicators do not change rapidly, they
can be used directly as flags without flip-flops. Flip-flop flag indicators might
still be used in a real environment; you should be able to show how they could be
added to this system. A three-state sense register is still used to input these
signals into the microcomputer.
Your object is to write a software program to keep the liquid between the FULL
and EMPTY limits and to sense an overflow condition, which might be caused by a
poor switch or valve. Consider the flow chart shown in Figure 23-6. The flags
are sensed in software using two conditional jump instructions. Notice that in
this flow chart example, symbolic addresses have been used. These address names
or address symbols are used to simplify the programming task since actual address
values do not have to be assigned until the program is finished or assembled.
2a]
INPUT
OVERFLOW
INPUT LEVEL
OPEN VALVE
Figure 23-6. Software flow chart for controlling the level of solvent in a
storage tank.
The software for controlling the level of solvent in the tank can be written as
follows:
LO memory Instruction
address byte Mnemonic Description
015 323 OUT The tank is not full. Open the valve
and let more solvent flow in.
022 325 FULL: OUT The tank is full. Close the valve
that lets solvent flow in.
We have assumed that the address of the ALARM subroutine is HI = 003 and LO = 100.
The ALARM software might first contain a command to shut the valve, OUT 015, and
then a routine to actually sound the alarm signal.
The above software is useful in understanding other aspects of flag bit manipula-
tion. All of the bits except D5 have been masked out, or cleared, in the first
AND operation, in which the overflow status is checked. This means that the flag
25-9
information must be input again when the FULL and EMPTY limits are to be checked.
Such a step could be eliminated if the status data were saved in a memory loca-
tion, for example, in a register or on the stack. This might be important if the
six other input bits are connected to other devices and must be checked as well.
In real projects such as this, there is the possibility of errors. For example,
the FULL/EMPTY switch wires may be reversed, so that in the full position the
valve opened and in the empty position it shut. This could be disastrous, so
the fluid level control system must be checked or simulated before it goes into
actual operation. You will do this in one of the experiments. In the software
example, the microcomputer is dedicated to a small loop that continuously checks
the solvent tank. In a real situation, other tanks and levels would also be
checked. The time to fill the tank is extremely long compared to the time in
which the microcomputer can check fifty or more tanks. If, however, the micro-
computer is also performing other tasks, it may not be in a position to check
each tank except once every several seconds. Depending upon the other tasks
assigned to it, the microcomputer may actually miss a FULL level or even an
OVERFLOW condition if it takes too long to do some of these other operations.
A final point te consider is the time required to turn the valve on or off.
Depending upon the size of the valve, this time may range from one second to
five to ten seconds. In properly written software, the valve will be given
sufficient time to turn on or off before another decision on its state is made
by the microcomputer. When the solvent tank is operating near its FULL position,
software should be available to prevent the valve from opening or closing
unnecessarily.
POLLED OPERATION
was used in
The type of microcomputer operation, which we discussed above, that
called
both hardware and software for the keyboard and the solvent tank is
polled operation. Polling is defined in the following manner.
If you were interrupted while reading this page, you would probably finish the
sentence, mark your place €perhaps mentally), and then take care of the interrupt,
i.e., a phone call, meal, child, etc. After finishing with the interrupt, you
would continue reading where you left off. Computers service interrupts in much
the same way! The term, interrupt, can be defined as. follows:
o The computer may be doing other things not related to the 1/0
devices while waiting for them to require servicing.
TYPES OF INTERRUPTS
There are three basic interrupt modes, single-line, multilevel, and vectored.
Device No. |
interrupt MICRO-
Device No. 2
COMPUTER
Device No. 3
interrupt no.
Device No. |
no. 2
interrupt MICRO -
COMPUTER
Device No.2
interrupt no. 3
:
Device No. 3
vector
instruction
bits
MICRO-
COMPUTER
interrupt no.|
; | p
Device No.
Each technique is shown in Figure 23-7. Im the single-line system, many devices
may be added, but they must all be polled through a sense register using flag
flip-flops. Servicing can be slow since a long time may be consumed in polling
all of the devices in a large system. The multilevel interrupt is a mix between
vector and single-line schemes. It has limitations and takes careful software
management to use it effectively. The vectored interrupt will be discussed in
detail below.
RESTART: RST x
In this Unit, we will be mainly concerned with the vectored interrupt techniques
that are used on the 8080A microprocessor chip. This type of interrupt permits
us to provide not only an interrupt pulse, but also an instruction to the
microprocessor to tell it what to do. In simple 8080A systems, a single-byte
instruction can be forced into the computer when it is interrupted. While rotate,
increment, and other single-byte instructions might be useful in some applications,
restart instructions, t.é., single-byte subroutine call instructions, are much
more useful and flexible.
~
The usual 8080A call instructions, both conditional and unconditional, each
specify a sixteen bit address in the second (LO) and third (HI) instruction
bytes. How can there be a single byte subroutine call? The answer is that
restart instructions call subroutines at predefined addresses. These instructions
are listed below,
The subroutine locations, HI = 000. and LO = OX0,, are preset in the 8080A chips
and cannot be changed. There are other ways around this limitation if you wish
to use other locations for interrupt software.
The restart instruction 3X7 is "jammed" into the 8080A chip only during an inter-
rupt. As with other inputs such as memory read and accumulator I/0 input, the
data for the RST X instruction byte must be gated onto the 8080A bus at the
proper time. An additional signal, interrupt acknowledge (INTA or IACK), is
provided to synchronize the input of the single-byte instruction. The interrupt
acknowledge signal is used to strobe the instruction byte onto the data bus and
into the 8080A chip. The instruction byte goes directly to the instruction
register and not to any of the general purpose registers. The interrupt signal
flow is shown schematically in Figure 23-8. A standard three-state input port
Do
MEMORY:
8 bit
instruction 2
5
mo]
=£
foe)
register
DM8095 (74365) is
constructed from chips such as the 8212 puffer/latch or the
than IN 006 or some
used to input the interrupt instruction, using INTA rather
other input device select pulse as the strobe or enable pulse.
8080A and other microprocessor chips have a very useful feature: the CPU
The
requests. We may
has the ability to make itself immune to external interrupt
allow them to be accepted, or we may turn it off and
turn the interrupt on to
to be used at all.
ignore them. There are times when we do not want the interrupt
off. Tt isthe
When the 8080A is started or reset, it turns the interrupt
if the 8080A chip is
responsibility of the programmer to enable the interrupt
interrupts. This is done with a software instruction,
to accept and service
or EI. We can also perform the complementary operation, disable
enable interrupt,
interrupt, or DI.
interrupts after
373 EL Enable the interrupt system and accept
execution of the next instruction.
the flag is enabled, interrupts are gated through to the 8080A chip's control
section. When the flag is disabled, interrupts are blocked.
The interrupt input goes to another internal 8080A flag that can remember one
interrupt event, or that cambe triggered even if the interrupt is disabled. A
third control output, the interrupt enable (INTE), which is pin 16 on the 8080A
chip, may be used to indicate to external devices and interfaces that the inter-
rupt is enabled (logic 1) or disabled (logic 0). The interrupt is always
disabled after accepting an interrupt from an external device.
Let us take another look at the keyboard interface to see how an interrupt can
be used in place of a flag. In some applications, for example, where the keyboard
and a large number of other I/0 devices are connected to a computer, it may take
a long time for the computer to get back and poll the keyboard. Characters may be
missed or ignored if the software is not carefully written. The solution to this
problem is the interrupt, which provides almost immediate servicing for external
devices. To successfully use the interrupt, we need to connect the keyboard's
VALID output pulse to the 8080A chip's interrupt input at pin 14. The VALID
output is a positive pulse, as required by the 8080A chip, so no inversion or
buffering is required, We also need to provide the restart instruction byte,
in this case, RST 5, which has an instruction code.of 357. This instruction byte
is sent directly to the 8080A chip's instruction register when the interrupt is
acknowledged. With the aid of an 8212 buffer/latch chip, we can hardwire this
instruction byte at an interrupt instruction register or interrupt instruction
port, as shown in Figure 23-9.
Let us now quickly review the operation of an interrupt. First, the interrupt
flag must be enabled within the 8080A chip using the software instruction, El.
Next, an external signal causes an interrupt and the 8080A acknowledges
it by
generating the interrupt acknowledge signal, INTA, whieh is used
to gate a
single-byte restart instruction into the 8080A's instruction register.
We use
a restart instruction, specifically RST 5, to call the service subroutine
at
HI = 000 and LO = 050, the memory location where software for the
keyboard input
Starts. ~
The keyboard interrupt acts to insert the keyboard input driver routine into the
normal software flow. A typical example of how this occurs is shown below.
LO memory Instruction
address byte Mnemonic Description
052 pe
OTHER
INTERRUPT
. ° SERVICE :
eevee
g O | SOFTWARE |
Sur
IN 005
To 8080
INTERRUPT
input
To data bus
Interrupt
Instruction
Port
We treat our vector subroutines as if they were normal. subroutines, 7.e., PUSH
and POP instructions may be used to store and_retrieve register data. A typical
interrupt subroutine would appear as shown in Figure 23=10. Since there are only
PUSH >
Instructions
instructions
2-17
eight locations between the keyboard vector address, 050, and the next vector
address, 060, how can all this software be used? If 060 is used as a vector
address for another device, we certainly have a problem! We can circumvent the
problem simply by placing a three-byte JMP instruction in locations 050, 051, and
052 that transfers program control to an area in memory where there is more room
for the software. The penalty that we pay for doing this is a time delay of 10
clock states, t.@., 5 microseconds for a 2MHz microcomputer and 13.33 microseconds
for a 750 kHz microcomputer. The RET instruction at the end of the service
routine still returns program control to the point where the MAIN TASK was
interrupted and the RST 5 instruction executed, as indicated schematically in
Figure 23-11.
ae
om
MAIN 000 O50 JMP
OS! <LO> }
052 <HI>
Return to
MAIN TASK Keyboard
where erat
interrupted id a
Software
20+ steps
Figure 23-11. Relationship between MAIN TASK, the vector subroutine jump, and
the keyboard service software, which is located elsewhere in memory.
PRIORITY INTERRUPTS
Priority interrupts are interrupts that are ordered in importance so that some
interrupting devices take precedence over others. When a number of interrupts
occur at the same time, or when this possibility exists, we need some method to
determine which device should be serviced first. A priority must be established.
The easiest way to do so is to poll the interrupting devices and, with the aid
of software, determine which devices should be serviced and in what order. In
the circuit shown in Figure 23-12, three interrupts are shown for clarity, but
others could easily be added. An interrupt occurs whenever one of the flag
flip-flops is set by a pulse applied at its clock input. When the interrupt
occurs, the 8080A chip generates an INTA pulse and inputs the restart instruction
code, 357, that is pre-wired at the 8212 interrupt instruction port. The 357
instruction causes a vector to the memory address HI = 000 and LO = 050, where
the software for polling the interrupting devices starts. The vectoring and
restart instructions should be well understood at this point. We will now
discuss the polling routine, which is listed below.
LO memory Instruction
address byte Mnemonic Description
053 346 ANI Mask out all bits except bits DO,
D1, and D2
INTERRUPT
HR CLOCK input
OUT
KEYBOARD To
data
bus
OUT
CASSETTE
OUT Oll of \\
PF X
size NY
Interrupt
Instruction
Each flag bit is input as a logic 1 if service is not needed and as a logic 0
if service is needed. The three-input NAND gate provides a logic 1 to the
8080A microcomputer when any device generates an interrupt; this logic state
is input to pin 14 on the 8080A chip. Our priority is set up so that the cassette
is highest (high speed device), the keyboard next (low speed device), and the
one-hour clock last (extremely slow device). As input data to the accumulator,
we would rather have a logic 1 if service is needed and a logic 0 if service
is not needed. Our first program step would therefore be to invert, or complement,
the input flag data with the use of a CMA instruction at LO = 052. This simple
program step illustrates how easy it is to invert accumulator data and how easy
it is to eliminate three 7404 inverters or else eliminate the need to re-wire
the hardware so that the Q output, rather than the Q output, is input to the
7410 gate.
After the CMA instruction, we mask out all other device bits except bits DO,
D1, and D2. We then proceed to rotate these bits into the carry flag and to
test them for a logic 1 state, which indicates that a specific device has
generated an interrupt. Each service routine--CASSVC, KBRD, and CLOCK--is
very similar to the interrupt service routine shown in Figure 23-10, and ends
with enable interrupt, EI, and return, RET, instructions.
Some additional comments about the polling routine are in order. Although the
polling routine runs through vector addresses 060 and 070, in this case it is
not an error since we have no other interrupts that use them. We would
probably start our polling routine with a PUSH PSW instruction, since we do not
know for what purpose MAIN TASK used the acewmilator.and flags when tt was
interrupted. If we used PUSH PSW, each service routine would require a POP PSW
immediately before the enable interrupt instruction. The first thing that we
would do in each service routine is to clear the flag associated with the
interrupting device. OUT instructions work well to generate pulses that clear
the flip-flops, as shown in Figure 23-12. Thus, an OUT 011 instruction clears
the cassette flag, an OUT 012 clears the keyboard flag, and an OUT 013 clears
the one-hour clock flag. Other polling software schemes and other bit testing
methods work equally well; the one given above is simple and effective.
The one-hour clock raises an important question, Why would you build an external
one-hour hardware clock when software can do it under 50 bytes? The answer
depends on how you use your microcomputer. If the microcomputer can just sit
and perform the one-hour software loop, or if you are using interrupts and can
tolerate error, you employ software. If you need an exact time and are using
interrupts, you employ hardware. How do you reach this decision? When you
use interrupts, you interject additional software into the MAIN TASK program flow.
This all takes time since not only must the software check the interrupting devices |
but it must also service it. If you interrupt the one-hour software routine
five times with a device service routine that takes two minutes to execute, you
have really taken a total of one hour and ten minutes to reach your goal, 7.e.,
the one-hour software operations are suspended when you interrupt and perform
another task. Real time marches on while the software time is suspended. The
one-hour external clock could be called a real-time clock, since it keeps real |
time, not computer software time!
|
HARDWARE PRIORITY INTERRUPTS
74148
Figure 23-13. Pin configuration and truth table for the 74148 8-line-to-3-line
priority encoder chip.
The necessary flags and flag setting or clearing lines are not shown in Figure
23-14 for clarity. Keep in mind, however, that a flag should be used for each
interrupting device. Additional hardware refinements could be added to the
circuit to make it more efficient and effective. These would include an additional
decoder to generate the flag clearing pulse without the need for an OUT instruction,
and a mask register so that various devices could be masked on or off in external
hardware. Such additions are shown in Figure 23-15, which is a very sophisticated
priority interrupt scheme that allows great flexibility in the use of vectored
interrupts with an 8080A-based microcomputer.
In writing software, you must decide which devices are to be allowed interrupts
and which are not. A mask bit pattern is developed in which devices that are
allowed to interrupt are assigned a logic 1 and devices that are not allowed to
interrupt are assigned a logic 0. The 8-bit mask pattern is placed in the
accumulator and output to the two 7475 latches in Figure 23-15. Bit position D7
corresponds to interrupt device 7, which has the highest priority and causes a
Pi To 8080
INT chip
+5V GND
Highest . 12
eh priority D7
D6
Status signals D5
D4 To 8080A
from interrupting
D3 data bus
devices
midty Priority
Lowest
gated driver
vector to memory address HI = 000 and LO = 070. Active devices that are masked
off use a sense register input to request service; the mask can be changed under
software control to achieve great flexibility in the use of interrupts.
In Figure 23-15, interrupt requests are gated with OR gates (one is shown) and
non-masked interrupt requests are passed through to the 74100 latch. Whenever
the interrupt enabled output, INTE, from the 8080A chip indicates that interrupts
will be accepted, the 74100 is "open" and passes interrupt
to requests through
the 74148 priority encoder. The priority encoder and interrupt instruction port
have been discussed previously. When the interrupt is received, the 8080A chip
disables its internal interrupt enable flip-flop
and the INTE output goes to
logic 0, thus "closing" the 74100 latch and latching any interrupt requests present
at the inputs. The INTA control signal not only inputs the RST x instruction, it
also pulses the 7442 decoder in Figure 23-15 to generate an interrupt flag clear
pulse, which is routed back to the individual interrupt request flip-flop
associated with the interrupting device. Many other interrupt schemes may be used,
including the Intel 8214 interrupt controller
chip and the 8259 programmable
interrupt controller chip. Finally, keep in mind that interrupts, while permittin
fast response to external events or demands g
for service, also can present problems.
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INTERRUPT SOFTWARE
Let us now consider the software necessary to serve some of our interrupt needs.
Assume that we have only two devices, device 7, which has the highest priority,
and a low priority device, device 2. Each has its own restart instruction that
causes a vector to 000 070 or 000 020, respectively. We will further assume
that the high priority device interrupts on a regular basis and that it is
quickly serviced with its software service routine. Device 2, the low priority
device, interrupts on an irregular schedule and takes some time to service.
Perhaps device 2 is another microcomputer that is dumping blocks of data. When
not interrupted by these devices, the microcomputer will always be running the
MAIN TASK software. Finally, we will assume that MAIN TASK initially assigns
a stack pointer through the LXI SP <B2> <B3> instruction and also enables the
interrupt flag. :
Since our interrupts can occur at any time, we need both PUSH and POP instructions
in the interrupt service routines, an example of which has been previously given
in Figure 23-10. These instructions will save and restore any registers that are
altered in the service routines.
In Figure 23-17, the MAIN TASK starts operating and is then interrupted by the
HIGH priority device. After executing the HIGH priority device service surboutine,
control is returned to MAIN TASK, which is interrupted by the LOW priority
device
later on the time line. Control is eventually returned to MAIN TASK, which is
then interrupted at repeated intervals by the HIGH priority device. Wote that
tt takes considerably longer to reach the point # in MAIN TASK when we keep
interrupting tt. During a critical timing period, this could be disastrous
if we are relying upon software timing loops.
LX| SP
El
070
HIGH
PRIORITY |
DEVICE
SERVICE
ROUTINE
4mz-
O20
LOW
PRIORITY
DEVICE
SERVICE
ROUTINE
DI | +
LX SP
E|
¥*
%
*
0
Ww * <
2-Prpe
ecoooe eeee
Figure 23-17. Program execution time line for MAIN TASK and both the LOW and HIGH
priority device service subroutines.
Lr2T
Return to MAIN
Return to LOW
interrupting of
line that demonstrates the
Figure 23-18. Program execution time soft ware is interrupted
ice routine. The LOW interrupt
an inte rrup t serv
the HIGH prio rity device.
twice by
7 5— 92
2. £0
we are able to complete the LOW software before the LOW priority device generates
a new interrupt. It is entirely possible for the LOW priority device to
interrupt the microcomputer while it is still trying to service the last interrupt
request from the LOW device. While the interrupt response is fast, the actual
execution time may be much slower than the time required for a single pass through
the interrupt service software. This is because we can interrupt our interrupts.
Such considerations should give you a good idea of the care needed when using
priority interrupts. It is very easy for a microcomputer to become interrupt
bound, i.e., it spends all of its time checking and servicing interrupts and has
no time left for its MAIN TASK software.
In our software, we may wish to prevent interrupts from taking place because
of sensitive timing software or complex time-dependent tasks or calculations.
The disable interrupt instruction allows the microcomputer to operate under
such conditions, insensitive to external interrupts. In our ‘previous example,
we could have included such a section in MAIN TASK when we needed to be immune
from interrupts. We can always disable the interrupt flag and later re-enable
it when we have completed a sensitive task. However, during the time that the
interrupt flag is disabled, we may lose signals or data that an interrupting device
may need to input tnto the microcomputer. Such a situation is represented in
Figure 23-19. Unless we provide some type of complex hardware back-up, such data
is lost! We do not know exactly when an external device may interrupt MAIN TASK.
Therefore, we cannot be sure that such an interrupt will not be during the period
when the interrupt flag is disabled. How do we circumvent this problem? It is
not easy to do so, which is another reason why we must use a great deal of caution
when we use interrupts. “
Another type of interrupt which may be of interest, although not generally used
with an 8080A microcomputer, is a ttme-oriented interrupt. Only one interrupt
is used, a clock. The clock interrupts every 10 milliseconds, or other reasonable
period of time. When interrupted, the microcomputer uses a look-up table to
determine which devices to check to see if they need service. Some devices are
always checked, while other slower devices might be checked once every one
thousand times the clock interrupt occurs. This is a good alternative interrupt
technique, but it requires considerable amounts of sofware to work well.
Some final notes of caution. Interrupts are difficult to debug. They can occur
at almost any time, 7.e., they occur asynchronously. Typical software debugging
programs are not of much help. Special diagnostic software may need to be written
to test interrupts in a specific application. When considering interrupts, try all
other methods before settling on them. The time trying other methods will usually
be well spent.
Rev. 9/22/77
23-29
Critical missed
Task * *-— This interrupt is
EL
demonstrates the use of DI and
Figure 23-19. Program execution time line that MAIN TASK. In
task to be perfor med in
instructions to permit a critical eritical
is missed or delayed while the
this case, however, an interrupt lost for the
is being execut ed. It is quite possible for data to be
task situation.
hardware is provided for such a
missed interrupt unless external
25-30
INTRODUCTION TO THE EXPERIMENTS
PURPOSE
8095 or 74365
+5V he
A
PULSER |
re) :
ere
or
74365
Bei
PROGRAM
Memory Instruction
address byte Mnemonic Comments
STEP 1 ?
.
Wire the digital circuit shown above. Make certain that +5 Volts and ground
connections are made to all chips and to the power busses on the SK-10 breadboarding
socket.
STEP 2
Enter the program into read/write memory starting at HI = 003 and LO = 000.
Observe that the program format is different from that used in the text in this
Unit as well as in earlier units. This is the type of output that you would
obtain from a commercial 8080A resident assembler such as the one available from
Tychon, Inc. The HI octal address bytes, 003, have been deleted to simplify the
listing. We will continue to use this output format in the following experiments
so that you will get used to it. Note the use of the delimiter, / , which is a
character that indicates the beginning of a comment.
The program will input the flag bit that we have wired, test the flag bit DO to
determine if it is a logic 1, and then increment the A register and output the
data to output port 002.
Rev. 9/22/77
(ey Oe rape
23-359
STEP 3
Execute the program. What do you observe at output port 002?
The output port reading is 000, i.e., all eight LEDs are unlit.
STEP 4
Now depress and release the pulser. What changes do you observe at output port
002? Repeatedly press and release the pulser. What happens?
The first pulser clock pulse increments output port 002 by 1 so that the reading
becomes 001. Additional clock pulses from the pulser continue to increment the
output port.
step 5
If you make a mistake in wiring the circuit and wire the Q output (pin 6) of the 7474
flip-flop to the 74365 chip, will the program operate correctly?
Change the 7474 output connection to Q at pin 6 and execute the program once
more. What do you observe? Why?
With Q input into the microcomputer, we observed that all the lights on output
port 002 appeared to be on. The reason is that the program detected that bit DO
was continuously at logic 1. Owing to the nature of the program, the contents
of register A were continuously incremented and output to port 002.
STEP 6
Could you change the software to account for the error in wiring? If so, what
changes would you make? Make these changes and execute the program once again.
What do you observe?
To eliminate the effect of the error in wiring, the JNC instruction at 003 007
can be changed to a JC instruction, 332. When this change is made, the circuit
and program no behave as described in Step (bi
Return the hardware and software to thetr original forms and continue to the next
experiment.
Rev. 9/22/77
EXPERIMENT NO, 2
FLAG RESPONSE TIME
PURPOSE “
‘
PROGRAM
Memory Instruction
address byte Mnemonic Comments
003 900
: These program steps are the same as those given in Expertment No. 1.
° ‘
003 021 016 MVI C /Load register C with the
003 022 OOo1 OO1 /data byte O01
003 023 315 REPEAT, CALL /Call the KEX time delay subroutine,
003 024 P2i}i} TIMEOUT /TIMEOUT at LO = 277 and
003 025 000 ) /HI = 000
sTeP 1
The hardware and software from the previous experiment will be used in this one.
Some additional software steps have been added above to keep the microcomputer
busy for varying periods of time. The 10 millisecond KEX time delay subroutine
at 000 277 is used. A listing of TIMEOUT is provided at the end of this experiment.
In this experiment, we use the KEX stack area to save the return address for the
CALL instruction. If you are not using KEX on an MMD-1 microcomputer, you will
have to first establish a stack area. Use the LXI SP instruction to do so.
Load the above program steps in read/write memory starting at 003 021.
25-35
STEP2
000. Press and release the pulser several
Start execution of the program at 003 and the previous
this experiment
times. Do you observe any difference between
for each pulser clock pulse?
experiment, where the count incremented
We observed no difference.
STEP 3
time
omputer by providing a 10 millisecond
The added software slowsdown the microc another value, you will cause
By settin g regist er C to
delay routine to execute. thus slowing
time delay routine many more times,
the microcomputer to execute the
more.
down the overall software loop even
memory location
one at a time into the program at
Enter the following timing bytes
e the progra m in each case. Test the influence of each timing
003 022 and execut (b) applying
pulses from the pulser slowly, and
byte by (a) applying several clock can. Enter the number of counts
the pulser as fast as you
ten clock pulses from
that you observe in the table below.
Octal timing
Normal Ten fast pulses
byte Time delay
012 100 ms
024 200 ms
062 500 ms
144 1s
310 2s
behavior,
to the flag, we observed normal
When we applied clock pulses slowly However, when we
increm ented once for each clock pulse.
i.e., the output port counted pulses
the pulser, we observed only five
applied ten fast actuations of with the 1 second delay, and only
counte d pulses
with the 500 ms delay, three
second delay.
two counted pulses with the 2
step 4
—_
about the use of flags when the microcomputer
What do the results in Step 3 indicate
other time-consuming tasks to perform?
has
000 ZiT 365 TIMEOUT, PUSH PSW /Save ‘accumulator and flags
»
With an 8080A-based microcomputer operating at 750 kHz, this time delay routine
will generate a delay of 10.0 milliseconds.
EXPERIMENT NO. 3
NON-IDEAL FLAGS: INTERFACING A MECHANICAL SWITCH
PURPOSE
The purpose of this experiment is to investigate the operation of an external
flag circuit that is connected to a single-pole single-throw (SPST) switch, a
non-ideal mechanical device.
The circuit is identical to that given in Experiment No. 1 except for the pulser
input to the 7474 flip-flop. In place of the pulser, use a single-pole single-
throw (SPST) mechanical switch wired as follows:
+5V
1 kQ To pin 3
Spo of 7474
PROGRAM
The program is identical to that given in Experiment No. 1. Make certain that
the final jump instruction reads as follows:
STEP 1
The hardware and software from previous experiments will be used in this experiment
as well. If they are not already set up, wire the circuit shown in Experiment No.
1. In place of the pulser, wire the SPST switch circuit shown above or else use
a logic switch on the LR-2 or LR-25 Outboards.
STEP 2
The software used in this experiment is identical to that given in Experiment
No. 1. Make certain that it is correctly loaded into read/write memory.
B38
STEP 3
Execute the microcomputer program and actuate the single-pole single-throw (SPST)
non-ideal mechanical switch (or equivalent wire circuit). Inspect the
output at output port 000. | Do you observe a single count, as in Experiment No. 1,
or many counts? Why? :
We observed many counts. This indicates that our SPDT switch is not an "ideal"
switch, as is a "debounced" pulser. The difference between:the two switches can
be depicted as follows:
IDEAL SWITCH | |
\" Su ee
We observed many counts because the 7474 flag sensed each "bounce", or almost
every one, as an individual switch closure.
STEP 4
Actuate the SPDT switch ten times and observe the total number of counts. Repeat
this process several times, being sure to restart the microcomputer before each
trial. Summarize your results in the table below beside our results. Note
that the number of counts is expressed in octal rather than decimal.
.
fon)—N
WOPwonNe
It is likely that the microcomputer loop was not fast enough to detect all the
bounces of your imperfect mechanical switch, and the bounces are non-reproducible.
While the bounces can be eliminated with hardware, as was done in the first exper-
iment, they can also be eliminated using software. The following experiment
investigates the keyboard interface and demonstrates how you use
the KEX software
to "filter out" the bounces.
27559
EXPERIMENT NO, 4
KEYBOARD CHARACTERISTICS OF THE MMD-1 MICROCOMPUTER
PURPOSE
The purpose of this experiment is to demonstrate how to use the keyboard flag,
bit D7, to signal that a key is pressed and data is readyto be input into the
8080A microcomputer.
PROGRAM No, 1
Memory Instruction
address byte Mnemonic Comments
PROGRAM No, 2
Memory Instruction
address byte Mnemonic Comments
You will use the keyboard flag, bit D7, to signal the 8080A that a key is
pressed and data is ready to be input.
STEP 2
Execute the program and note the four least significant bits at output port 002.
Press each keyboard key in turn and list the 4-bit code that you observe under
the "Step 2" heading. Do you observe a match between your code and the expected
code?
Your code
Key Expected code Step 2 Step 3
0000
0001
0010
0011
0100 *
0101
0110
0111
1100
1101
1011
1000
1110
ale a ‘
ABP 1010
NDAFMNADAURWNHRO
We observed a match between our code for Step 2 and the expected code.
STEP 3
If your codes did not match our expected code, you may wish to use
the KEX
debounce and keyswitch filter subroutine, which is documented in the
MMD-1 manual
and also in the June, 1976 issue of Radio-Electronics magazine. Program No. 2
calls the keyboard input subroutine KBRD in KEX. Load Program No. 2 into
read/write memory starting at HI = 003 and LO = 200 and execute it. Press each
keyboard key in turn and note the least significant bits at output
port 002.
List these four bits under the Step 3 column in the above table.
Are the codes
for Step 2 and Step 3 the same? If not, why not?
23-1]
The codes for keys L, H, G, S, A, B, and C have been changed in a look-up table
employed by the KEX software. Thus, they are not the same.
STEP 4
Can you suggest why this code translation of keys L through C might be useful?
With the KEX EPROM in the system, the keyboard input routine at 000 315 may be
called to input and encode the keyboard data. They keyboard routine uses a
10 millisecond delay subroutine at 000 277 that may also be called at any time.
The delay routine is completely "transparent" and will not affect any flags or
registers. It is listed at the end of Experiment No. 2 in this unit.
25-112
EXPERIMENT NO, 5
SIMULATION OF TANK LIQUID LEVEL SENSING
PURPOSE ~
The purpose of this experiment is to implement the hardware and software necessary
to simulate the liquid level sensing example discussed in the text.
8095 or 74365
+ 5V GND
LOGIC D
SWITCH a
A= OVERFLOW | D5
D = FULL / EMPTY t anne
PROGRAM
Memory Instruction
address byte Mnemonic Comments
003 002 346 ANI /Mask out all bits except bit D5
003 003 040 040 /Mask byte = 00100000
sTeP 1
Wire the circuit shown in the schematic diagram. Logic switch A is the overflow
flag and logic switch D is the full/empty flag.
STEP 2
Load the program into read/write memory starting at HI = 003 and LO = 000.
23-ly
STEP 3
With both logic switches set to logic 0, execute the program. You will simulate
the valve with bit DO on output port 000. If bit DO is logic 1, the valve is
open; if bit DO is logic 0, the valve is closed. What do you observe when the
software is started? Why? ;
We found that bit DO was at logic 1, indicating that the valve was open. This
is because the empty/full flag is at logic 0, indicating that the tank is not
full (or perhaps empty). ;
STEP 4
Change logic switch D to logic 1 indicating that the tank is FULL. What happens
to the valve bit DO? Wny?
Valve bit DO becomes logic 0, or off, indicating that the valve is now closed.
The fluid level in the tank has tripped the full switch.
STEP 5
Switch logic switch A to a logic l, indicating an overflow condition. What
happens? Why?
2
.
STEP 6
Can you suggest a useful ALARM routine for your
microcomputer? You may wish to
test several different short software ALARM routines
. Use the space below.
25-15
In developing an ALARM routine, we decided that the first thing we should do is
to turn off the valve and then output an alarm condition at port 001. The
program is as follows: ;
Memory © Instruction
address byte Mnemonic Comments
as flags.
You should note in this experiment that you have not used flip-flops
and the FULL/
This is a valid procedure in this case since the overflow switch
action. A
EMPTY switch will maintain their respective states until we take
requesting the
flip-flop flag is generally used in those cases when the device
than a level.
attention of the microcomputer is generating a short pulse rather
23-6
EXPERIMENT NO, 6
RESTART INSTRUCTIONS
PURPOSE
The purpose of this experiment is to investigate the software characteristics
of the 8080A restart instructions, RST X.
PROGRAM
Memory Instruction
address byte Mnemonic Comments
sTeP 1
Enter the above program into read/write memory starting at 003 000. If you
are executing this program on the MMD-1 microcomputer, please keep the following
in mind: A RST X instruction calls the subroutine at 000 OX0,
but the KEX
monttor causes program control to jump to 003 0X0 for restart
instructions
RST 1 through RST 6. Restart instructions RST 0 and RST 7 are used by the KEX
monttor. You can confirm this fact by examining the contents
of the EPROM
memory locations at 000 010, 000 020, 000 030, 000
040, 000 050, and 000 060.
What instruction bytes do you find in KEX memory locations 000 050 through
000 052?
STEP 2
Execute the above program. Observe that the stack pointer is set at address
25-7
003 200, so that the stack itself will start at one less than this memory location,
or 003 177. After you execute the program, examine the contents of the two stack
locations 003 176 and 003 177 and list the contents in the space below.
003 176
003 177
Are these two bytes consistent with what you would expect for the execution of a
CALL instruction?
The two stack bytes correspond to the memory address, 003 004, which is the address
of the HALT instruction. This is exactly what we would expect for a call.
You should note that the stack pointer will again point to memory address
003 177 after the program is executed. Why?
Not only did the program execute a RST 5 instruction, it also executed
a RET instruction that popped the two bytes off the stack. Though they were
popped off the stack, the original values remained in read/write memory. Remember
that the stack pointer is an internal 8080A register and cannot be directly
examined.
STEP 3
The software routine at 003 050 can perform other tasks as well. Change the
program steps to the following:
Memory Instruction
address byte Mnemonic Comments
We observed that output port 000 incremented its count for each RESET/G cycle.
The increment software was called by the RST 5 subroutine.
STEP 4
After several increments, examine the stack locations 003 176 and 003 177 once
again. Are the stack byte values any different from those that you observed
in Step 2? How do you explain this result in view of the fact that you have
executed the restart subroutine several times?
You should observe no change in the stack bytes, which still contain the address
of the HALT instruction, 003 004. Each time that you pushed an address on the
stack as a result of the RST 5 instruction, you also popped the same two bytes
when you executed the RET instruction. Clearly, for each RESET/G cycle,
and thus each calling of the subroutine, the return address was the same.
Remember that the return address stored on the stack is for the instruction
following the one-or three-byte CALL instruction. In this case, it happens to be
a HLT instruction.
25-19
EXPERIMENT NO. 7
A SIMPLE INTERRUPT INSTRUCTION REGISTER
PURPOSE
The purpose of this experiment is to wire and test a simple interrupt instruction
register.
D7
LOGIC D6
SWITCHES 05
D4
D3
LOGIC D2
SWITCHES 01
| DO
INTA
0
PULSER =|
fo) INT
INTE
LAMP
MONITORS
>
wr
©narvronre
10
8212
PROGRAM
Memory Instruction
address byte Mnemonic Comments
sTeP 1
In the circuit shown for this experiment, the 8212 buffer/latch is the interrupt
instruction register, the pulser causes the actual interrupt, and the lamp monitor
indicates the status of the 8080A chip's interrupt enable flip-flop, which is
located within the chip.
Turn the power to the microcomputer on and off several times. Note the condition
of the interrupt enable (INTE) lamp monitor each time the microcomputer is on.
Is the interrupt enabled when the computer is turned on?
Generally it is off, but this is not a rule with all 8080 microcomputer systems.
With the MMD-1 microcomputer, there is no EI instruction in KEX, so it is not
possible to enable the interrupt even if KEX was executed accidently when the
power was turned on.
STEP 2
Execute the program provided for this experiment. What is the state of the
8080A chip's interrupt enable flip-flop when you do?
STEP 3
After the software has been started (note that it loops continuously), observe
the value of the byte present at output port 001. Write it in the space below.
Now set an 004 on the logic switches, HGFEDCBA = 00000100 = 004,, and depress
the interrupt pulser. What byte now appears at output port 001? What is the
condition of the INTE lamp monitor?
After setting the logic switches to the instruction byte, 004, and depressing the
interrupt pulser, the value of the byte at port 001 is incremented by one. The
004 instruction increments the contents of register B, INR B. The interrupt
enable lamp monitor is logic 0 after the interrupt is serviced.
STEP 4
Reset the microcomputer and again execute the program. Note the values of the
bytes at port 001 before and after you actuate the interrupt pulser. Does the
incrementing continue?
pee
IES
Yes it does. Keep in mind the fact that when the MMD-1 is first reset, KEX
outputs a HI address byte of 003 to output port 001. It is this byte that is
incremented each time you execute the program and press the interrupt pulser.
STEP 5 .
At memory address 003 007, replace the MOV A,B instruction byte with a NOP
instruction byte (000). Set the instruction, 074, on the logic switches to
the interrupt instruction port and execute the program. What happens when you
cause an interrupt by activating the interrupt pulser?
The byte at output port 001 is incremented by one. In this case, we have
executed an INR A instruction prior to outputting the accumulator contents to
port 001. This INR A instruction was jammed into the instruction register
during the interrupt.
STEP §
step /
An interrupt causes the 8080A chip to accept a single-byte instruction from the
interrupt instruction port. Does the nature of the jammed insfruction affect
the contents of the stack? If you do not know the answer to this question,
perform the following experiment: Set the contents of memory locations 003 176
and 003 177 to 000. Repeat either Step 6 or Step 7, or both, then reset the
microcomputer and examine locations 003 176 and 003 177. What do you find in
these two locations? Can you explain why?
We observed that the contents of both locations remained at 000. The execution
of either the INR A or the RRC instruction does not cause the microcomputer to
place an address on the stack. Thus, the stack contents were not changed. The
only instructions that affect the stack are subroutine calls, including the
restart instructions, subroutine returns, PUSHes, POPs, and the SPHL instruction.
STEP 8
So far, you have been able to interrupt the program only once each time the
program was executed. Why?
The JMP instruction at 003 012 caused a jump back to memory location 003 004
rather than memory location 003 003.
STEP 9
Change the jump address at location 003 013 to LO = 003. This permits the
program to jump back and enable the interrupt instruction once each loop.
Now set 017 on the logic switches and depress the interrupt pulser. What happens?
Keep the pulser depressed and observe what takes place.
The data is rotated at random. When continuously depressed, the interrupt pulser
applies a logic 1 at the INT input of the 8080A chip, which continuously
interrupts the execution of the current program. The interrupt enable lamp
monitor dims and all of the LED's at output port 001 become lit.
STEP 10
Based upon your observations in Step 10, is the interrupt input to the 8080A
chip edge-triggered or level sensitive? How can you circumvent the problem that
you observed in Step 10?
The 8080A chip's interrupt input, INT, is level sensitive. Whenever this input
pin is at logic 1, interrupts will take place as long as the interrupt flag is
enabled. To circumvent this problem, you can insert a positive-edge triggered
flag between the pulser and the INT input.
Save the hardware and software given in thts experiment and continue to
the next expertment.
EXPERIMENT NO, 8
JAMMING A RESTART INSTRUCTION
PURPOSE .
OD
OA
=©ON
eRwWwnD
Sey,
N
8212 me
PULSER
INT
PROGRAM
The program is identical to that given in Experiment No. 7.
step 1
You will need to make the following modifications to the circuit given in
Experiment No. 7:
o Connect the pulser to the STB input (pin 11) ‘on the 8212 chip.
o Connect the INT output (pin 23) on the 8212 chip to an inverter, and
then connect the inverter to INT on the bradboarding socket.
STB
which can be used to provide an interrupt signal to the 8080A chip. Keep in
mind that this circuit is already buiit into the 8212 chip; you do not have to
wire it on the breadboard.
STEP 2
Once you have made the necessary hardware changes, make certain that your program
is the same as that given in Experiment No. 7. With the interrupt instruction
register logic switches set to the instruction byte, 017, execute the program.
Assuming that the instruction byte at memory address 003 013 is 003, then you
should observe that the data at output port 001 rotates one position to the right
each time that you press the pulser. Is this true?
Yes.
STEP 3
Now you will execute a simple program through the logic switches of the interrupt
instruction register. Perform the following operations in sequence:
o Set the logic swtiches to 227. Press the pulser and interrupt the
microcomputer.
o Next, set the logic switches to 074 and interrupt the microcomputer a
second time.
o Now set the logic switches to 017 and interrupt the microcomputer a
third time.
o Finally, continue to interrupt the microcomputer several times.
When you do all of the above, what do you observe at output port 001?
A single lamp monitor in the DO position becomes lit, and then rotates to the
right for each interrupt.
STEP 4
So far, you have demonstrated that you can jam a variety of single-byte instruction
into the instruction register during an interrupt. Once in the instruction
register, they will be executed as regular instruction bytes. Now we will
demonstrate the jamming of restart instructions, RST X.
Enter the following software into read/write memory at the locations indicated:
Memory Instruction
address byte Mnemonic Comments
Execute the program once again by pressing the RESET key and then the G key.
STEP 5 -
Set the logic switches at the interrupt instruction register to 327. Observe
what happens each time that you generate an interrupt to the microcomputer.
The byte at output port 001 increments by one for each interrupt pulse.
STEP 6
Now change the logic switch setting to 357. Actuate the interrupt pulser several
times. What happens?
The data rotates to the left one position for each interrupt actuation.
STEP 7
Load 000 into memory locations 003 176 and 003 177, which are the first two bytes
in the stack. With the logic switches set at 357, RESET the microcomputer and
then execute the program. Generate a single interrupt, then RESET the micro-
computer and examine these two memory locations, which were previously at 000.
Has the stack been used? Write the contents of these two memory locations in
the table below. Repeat Step 7 several more times, again noting the results
in the space below.
Memory contents
Trial 003 177 003 176
DOP
wne
Memory contents
Trial 003 177 003 176
ad 003 006
2 003 012
3 003 007
4 003 003
5 003 003
6 003 010
The stack bytes indicated the memory address of the next instruction to be
executed after a return from the interrupt service routine. In all cases, this
memory address was within the limits of our original program. This was to be
expected, since a return from the interrupt subroutines should always point
back to the program loop. Your stack contents may vary from ours, but all
addresses should be contained within the loop.
PURPOSE »
Memory Instruction
address byte Mnemonic Comments
DELAY SUBROUTINE
003 100 016 DELAY, /Load C with
003 101 001 /data byte 001
LOGIC
SWITCHES
LOGIC
SWITCHES
rPwa,
INTA
To debounced pulser
in which the STB input (pin 11) is now connected to a debounced pulser and
the INT output (23) is connected to a 7404 inverter that is tied to the INT
input of the MMD-1 microcomputer,
PULSER
INT
LAMP INTE
MONITORS
25-60
INTERRUPT TASK
003 020 365 PUSH PSW /Save accumulator and flags
sTeP 1
Load the software into read/write memory. Observe that the interrupt task software
now contains a PUSH and a POP instruction. Why are these necessary?
The other routines use the accumulator register, so we must save it. When the
microcomputer is interrupted, we do not know what the content of the accumulator is.
STEP 2
Execute the software. Now activate the interrupt pulser. Do you observe any
significant delay between the incrementing of output port 001 and the push of
the pulser?
>
No. We did not observe any delay, and there should not be any. The DELAY subroutiné
only causes a 10 millisecond delay.
STEP 3
Change the time constant at memory location 003 101 to the values given in the
table below. As you did in Step 3 of Experiment No. 2, apply ten clock pulses
from the interrupt pulser as fast as you can (Trial 1). Enter the number of
counts that you observe in the table below. If you desire to clear B, load the
following software:
012 100 ms
024 200 ms
062 500 ms
144 1s
310 2s
We observed results that were comparable to those in the Flag Response experiment,
Experiment No. 2. Why are the interrupts so slow in this case?
No matter when the interrupt occurs, we can only re-enable the flag after program
control returns to the EI instruction at memory address LOOP. If the DELAY loop
is of long duration, it will take considerable time to return to the EI instruction.
STEP 4
Make the following changes to the interrupt task software:
The interrupt flag is now re-enabled immediately after the RETURN instruction is
executed at memory address 003 027. Remember that the enable interrupt instruction
always takes effect after the instruction that follows it,
Repeat Step 3 and note your results in the column labled Trial 2. What do you
observe?
You should observe that the response time of the microcomputer is now essentially
independent of the long delay since the enable interrupt instruc-
tion in the interrupt task software turns the interrupt back on following
of the next instruction. We no longer have to
the execution
wait for the long delay to return to the EI instruction at memory address LOOP.
25-62
step 5
Is the enable interrupt (EL) instruction at memory address 003 003 needed?
Remove it by substituting a NOP instruction (000) and try the interrupt
pulser. What happens?
Nothing. The interrupt is never turned on, so we are not able to call our
interrupt task subroutine. .
Remember: if you want to use the interrupt, enable it! This experiment should
show you that interrupts, if used properly, can be serviced immediately. There
is no time delay between the request for service and the microcomputer's
response. This was not the case with the flags in Experiment No. 1.
Save your hardware and software for the following experiment. Though not shown
in Experiment No. 10, continue to use a Lamp monitor to monitor the logte state
of the INTE output from the 8080A chtp.
EXPERIMENT NO, lO
SIMPLE PRIORITY INTERRUPTS
PURPOSE
The purpose of this experiment is to investigate the implementation of a simple
priority interrupt scheme.
+ 5V
TO 8212
PIN 18
PULSER
ae
STEP 1
Rewire the hardware. Observe that some of the connections, those marked with an
asterisk *, are the same as those used in previous experiments.
STEP 2
Execute MAIN TASK starting at memory location 003 000. The enable interrupt
(INTE) lamp monitor may be used to check the interrupt enable state. It should
be at logic 1 as soon as the software is started.
Press and release pulser #1 several times. Do you observe any change at output
port 001?
We observed that the value at output port 001 is incremented by one for each
actuation of the interrupt pulser #1.
STEP 3
Press and release pulser #2 several times. Now what happens at output port 1?
We observed that the data was rotated to the right one position for each actuation
of pulser #2. If you do not observe these results in Steps 2 and 3, please go
back and check both your hardware and software. The software entered for the LOW
and HIGH priority devices was used only to test your interface. New software will
now be used in the experiment.
25-66
STEP 4
You will now change the software for the high priority device, i.e., the high
priority device service subroutine at 003 040, so that it takes longer to
perform its task. Enter the following software into read/write memory:
003 042 365 PUSH PSW /Store accumulator and flags on stack
DELAY SUBROUTINE
003 100 016 DELAY, MVI C /Load C with
003 101 144 144 /data byte 144
(IAB)
step 5
Execute the MAIN TASK software. Generate a LOW priority device interrupt using
microprocessor
pulser #1. This causes a RST 2 instruction to be sent to the 8080
chip. What effect does this have?
STEP 6
a HIGH priority device interrupt. Observe output
Actuate pulser #2 to generate
port 000. What happens?
sTeP /
device (interrupt pulser #1) during the time that
Attempt to use the LOW priority
the time that
the HIGH priority device subroutine is being executed, i.e., during
You can accomplish this by first
the lamp monitors are still being incremented.
quickly, by activating pulser #1 several times.
activating pulser #2 and then,
What happens?
23 (ate)
The LOW priority device interrupt pulser #1 has no effect if you are fast enough
to be able to interrupt during execution of the HIGH priority software.
If you wish to slow down the HIGH priority device service subroutine still
further, change the timing byte at memory location 003 107 to 310, which
corresponds to a two second time delay.
STEP 8
Why can't the LOW priority device interrupt the HIGH priority device? Is it
because of the priority hardware?
The LOW priority device cannot interrupt because the HIGH priority task does not
re-enable the interrupt until control is returned to the MAIN TASK program. This
is completely independent of the hardware; it illustrates a potential problem:
interrupts cannot be used unless the interrupt is first enabled. Priority can
be established either in software or hardware.
Save your hardware and software for the following two experiments.
Oza
EXPERIMENT NO, 11 25-69
PRIORITY INTERRUPT TIMING
PURPOSE
The purpose of this experiment is to explore the timing relationships between
HIGH and LOW priority devices and how the priority is assigned.
STEP 1
In the previous experiment, you observed that the HIGH priority device (slow)
could monopolize the microcomputer's time and not allow the LOW priority device
to interrupt.
Load the new software to make the LOW priority device service subroutine fairly
slow.
STEP 2
Execute the software starting at MAIN TASK, memory location 003 000. Test it
by generating first an interrupt from the HIGH priority device and, later,
by the LOW priority device. What happens?
The HIGH priority device continues to increment a count slowly; the LOW priority
device rotates one bit to the left, slowly.
STEP 3
Cause a HIGH priority interrupt with the pulser; while the HIGH priority software
is operating, pulse the LOW priority software. What happens?
2
~
The HIGH priority device continues to operate; the LOW priority software starts
when the HIGH priority software is finished.
sTeP 4
Cause a LOW priority interrupt and then cause a HIGH priority interrupt using
the appropriate pulsers. What do you observe?
23-71
The LOW priority software continues to operate. When it is finished, the HIGH
priority software operates.
STEP 5
Make the following software changes to MAIN TASK:
STEP 6
Can you perform more than interrupt with this software? Why or why not?
We could not. The interrupt enable instruction has been removed from the loop.
Once it is used, we never get back to it unless we reset the microcomputer.
STEP /
Add the two enable interrupt (EI) instructions to the HIGH and LOW interrupt
service routines as follows:
Note that the previous instruction bytes at these two locations were NOPs.
step 8
Repeat Steps 3 and 4 in this experiment. Are the results the same? Why?
J i
Yes. We now re-enable the interrupt at the end of each service subroutine.
STEP 9
Move the interrupt enable instruction in the LOW priority service software from
003 177 to 003 154. To do this, make the following changes:
step 10
Repeat Step 3. Is the result the same?
step 11
Generate a LOW priority interrupt using the pulser. When the logic 1 bit has
rotated toward the center, generate a HIGH priority: interrupt. What happens?
Why?
The HIGH priority interrupt interrupts the LOW priority interrupt software,
performs the increment operation, and then returns control to the LOW priority
software. The interrupt is now enabled at the start of the LOW priority interrup
software routine, thus allowing other devices of higher priority to interrupt it
step 12
Perform Step 11 again, but generate several HI priority interrupts during the LO
priority service time. What happens?
PURPOSE
PROGRAM
The software is the same as that used in Experiment No. 11.
sTeP 1
The circuitry used in Experiment No. 10 to generate interrupts is reproduced below.
+ 5V GND
TO 8212
PIN 18
Notice that one flip-flop has its Q output applied directly to the 8212 chip
(pin 18), while the Q output of the other flip-flop goes through some NAND
gates and then to the 8212 (pin 16). In this way, the restart instructions
RST 2, 327, or RST 4, 347, are generated. Using the schematic diagram, fill
in the truth table below:
»
HIGH LOW
PRIORITY PRIORITY
DEVICE DEVICE 8212 chip
Q Q QQ pin 18 pin 16 Condition
Oo yl OuRE
Oe iL ©
Te a0 0 1
1 oO LO
Our results, in the vertical order given, were as follows:
8212 chip
0 0 No interrupts
0 if LOW priority device interrupts
al 0 HIGH priority device interrupts
al 0 Simultaneous interrupt
STEP 2
Does the above truth table indicate what would happen if both the LOW and HIGH
priority devices attempted to interrupt at the same time? What would actually
happen?
>
.
Yes. It shows that the HIGH priority device woild override the LOW priority
device and cause the HIGH priority service subroutine to be executed.
STEP 3
Reset the microcomputer. Do not start the software. Remove the wire from the
logic 0 output of puler #1 and place it in the logic 0 output of pulser #2.
Both interrupts will now be generated by the same pulser.
Now start the software. Interrupt software action may initially take place;
allow it to finish before you proceed with the experiment.
sTeP 4
Observe the lamps at ports 000 and 001 carefully. Press and release the interrupt
23-75
pulser, pulser #2. What happens?
We observed that the HIGH priority software (increment the LEDs) started; when
it had vinished, the LOW priority software (rotate a bit) started and completed
its task.
step 5
Repeat Step 4 five more times. Does the HIGH priority device software always
start the sequence?
Yes.
STEP 6
Reset the microcomputer. Do not start the software. Replace the wire, which
you moved in Step 3, to the logic 0 output of pulser #1. Cause a LOW priority
routine operation, again generate a
interrupt and, in the middle of the service
LOW priority interrupt. What happens?
step /
in Step 6? HINT: Register L is not saved on
Can you explain what you observed
the stack in this program.
What solutions could you suggest for the problem identified in Step 7?
We suggest:
1. Clear the low priority device's interrrupt service request flag at the
end of the service routine.
2. Push all of the registers to be used in the routine onto the stack.
You should never permit an interrupting device to interrupt its own software
service routine. If it does, the external device is operating too fast for
the microcomputer; the software must be simplified to speed it up. Why?
Because by the time we get into the second interrupt's service software, a
third interrupt will interrupt the second, etc. We will never be able to
complete any of the service routines.
~
25-/7
REVIEW
questions will help you review the use of flags and interrupts.
The following
types of devices can be used as flags and why are flags important?
‘1% What
5. The restart instructions, RST X, are generally the most useful. They are
single-byte calls that, when executed, cause a return address to be pushed
onto the stack. The computer then vectors to the address of the subroutine
specified by the restart instruction. RST X calls a subroutine at 000 OXO.
A return instruction must be used to end the subroutine.
7. A priority interrupt is one in which there exists a preset priority for the
order in which interrupts are serviced by the computer. Priority may be set
up in hardware or software.
8. Determination of timing and priority are the big problems. These subjects
have been convered in detail near the end of the Unit.
APPENDIX ]: REFERENCES
1. The Compact Edition of the Oxford English Dictionary, Oxford Univ. Press, 1971.
7. Donald E. Lancaster, TTL Cookbook, Howard W. Sams & Co., Inc., Indianapolis,
1974.
12. P. R. Rony and D. G. Larsen, Bugbook II. Logic & Memory Experiments Using
[TTL Integrated Circuits, E&L Instruments, Inc., Derby, Connecticut, 1974.
13. Robert L. Morris and John R. Miller, Editors, Designing with TTL Integrated
Circuits, McGraw-Hill Book Company, New York, 19/71.
BUGBOOK V
KK
AND gate A binary circuit with two or more inputs and a single output,
in which the output is logic 1 only when all inputs are
logic 1, and the output is logic 0 if any one of the inputs
is logic 0. Page 7-6. ~
astable element A two-state element that has no stable states. Page 15-2.
asynchronous Those input pins in a flip-flop that can affect the output
inputs state of the flip-flop independent of the clock. Called
preset, and reset or clear. Page 11-5.
base Also called the radix. The total number of distinct symbols
used in a numbering system. For example, since the decimal
numbering system uses ten symbols, the radix is 10. In the
octal numbering system, the radix is 8. In the binary
numbering system, the radix is 2 because there are only two
symbols (0 and i). Page 1-4.
A-5
binary A numbering system using a base number, or radix, of 2.
There are two digits (0 and 1) in the binary system. Page
7-2.
binary code A code in which each code element is one of two distinct
states. These states are usually given the symbols 0 and 1.
Page 1-4.
eLloek Any device that generates one or more clock pulses. Page
9-12.
elock pulse A complete logic cycle from logic 0 to logic 1 and back to
logic 0 (positive clock pulse), or from logic 1 to logic 0
and back to logic 1 (negative clock pulse). Page A-27.
code converston The changing of the bit grouping for a character in one
code into the corresponding bit grouping in another code.
Page 12-8.
decade counter A logic device that has ten stable states and may be cycled
through these states by the application of ten clock or
pulse inputs. A decade counter usually counts in a binary
sequence from state 0 through state 9 and then cycles back
to state 0. Also called a divide-by-10 counter. Page A-31.
fall time The time required for the negative trailing edge of a pulse
to decrease from 90% to 10% of its initial vaiue. In digital
electronics, the measured length of time required for an
output voltage of a digital circuit to change from a
high
voltage level (logic 1) to a low voltage level (logic 0).
Page 11-10.
Exclustve-OR gate A binary circuit with two inputs and a single output, in which
the output is logic 1 when the inputs are at different logic
states, and the output is logic 0 if both inputs are at the
same logic states. Page 7-11.
gate (logte A circuit having two or more inputs and one output, the
upon the combination of the logic
device) output of which depends
signals at the inputs. There are four basic gates, called
AND, OR, NAND, and NOR. Pages 7-2, 14-6, and 14-15.
is
gate ctreutt A circuit that passes a signal only when a gating pulse
present. An electronic circuit with one or more inputs and
the
one output with the property that a pulse goes out on
of
output line if and only if some specified combination
pulses occurs on the input lines. Page 14-20.
as a line
gated buffer A low-impedance driver circuit that may be used
In
driver for pulse differentiation or in multivibrators.
general, a buffer that is gated. Page 14-20.
and allows
gating etreuit A circuit that operates as a selective switch
when the
conduction only during selected time intervals or
Page 14-21.
signal magnitude is within specified limits.
it registers that
general purpose For an 8080-based microcomputer, six eight-b
The registers
registers temporarily store signal bytes of information.
are called B, C, D, E, H, and L. Page 6-2.
glttch An unwanted pulse or logic state, usually caused by poor
design and/or propagation delays. Page 13-13.
hexadecimat A digital code based upon the radix 16, in which the decimal
code numbers 0 through 9 and the letters A through F represent
the sixteen distinct states in the code. Page 12-2.
HI address byte The eight most significant bits in the 16-bit memory address
word for the 8080 microprocessor chip. Abbreviated H or HI.
Pages 2-8 and 3-5.
LED lamp A light-emitting diode (LED) that is lit in the logic 1 state
monitor and unlit in the logic 0 state. Page A-23,
LO address byte The eight least significant bits in the 16-bit memory address
word for an 8080 microprocessor chip. Abbreviated L or LO.
Pages 2-8 and 3-5.
A-9
memory Any device that can store logic 0 and logic 1 bits in such
a manner that a single bit or group of bits can be accessed
and retrieved. Page 2-6.
mnemonte symbol A symbol chosen so that it assists the human memory; e.g.,
the abbreviation MPY used for "multiply". Page 2-4.
monostable A digital circuit that has only one stable state, from which
multtvtbrator it can be triggered to change the state, but only for a
predetermined time interval, after which it returns to the
original state. Also called one-shot multivibrator, single-
shot multivibrator, or start-stop multivibrator. Page 15-2.
oetal code Pertaining to a binary coded numbering system with the radix
8, in which the natural binary values of 0 through 7 are
used to represent octal digits with values from 0 to 7.
Page 1-5.
operatton code For an 8080-based microcomputer, the eight-bit code for the
specific action that the 8080 microprocessor chip will
perform. Page 3-5.
rise time The time required for the positive leading edge of a pulse to
tise from 10% to 90% of its final value. It is proportional
to the time constant and is a measure of the steepness of the
wavefront. In digital electronics, the measured length of
time required for an output voltage of a digital circuit to
change from a low voltage level (logic 0) to a high voltage
level (logic 1). Page 11-10.
BUGBOOK VI
KKK
central proces- Also called central processor. “That part of a computer system
sing untt which contains the main storage, arithmetic unit, and special
(mainframe register groups. Performs arithmetic operations, controls
computer) instruction processing, and provides timing signals and other
housekeeping operations. Page 16-13.
central proces- A single integrated circuit chip that performs data transfer,
sing untt control, input/output, arithmetic, and logical instructions
(microprocessor) by executing instructions obtained from memory. Page 16-13.
control bus A set of signals that regulate the operation of the micro-
computer system, including I/0 devices and memory. They
function much like "traffic" signals or commands. They may
also originate in the I/O devices, generally to transfer to
or receive signals from the CPU. A unidirectional set of
signals that indicate the type of activity--memory read,
memory write, I/O read, I/0 write, or interrupt acknowledge--
in current process. Page 16-12.
Rev. 9/22/77
A-15
exc lustve A masking technique in which one either clears or sets (seldom
masking used) all bits not operated upon. Page 18-45.
general purpose In the 8080 microprocessor chip, 8-bit registers that can
regtster participate in arithmetic and logical operations with the
contents of the accumulator. Page 18-8.
instructton A decoder within the 8080 microprocessor chip that decodes the
decode instruction code into a series of actions that the micro-
processor performs. Page 18-11.
A-16
memory Any device that can store logic 0 and logic 1 bits in such a
manner that a single bit or group of bits can be accessed
and retrieved. Page 16-13.
memory mapped A term associated with 6800, 8088, and other microcomputer
I/O systems. The I/O instructions are memory reference instructions
and the data transfer occurs, in the case of the 8080 chip,
between the I/0 device and any of the general purpose registers
within the chip. Pages 20-2, 21-2, and 21-38.
open collector An output from an integrated circuit device in which the final
output pull-up resistor in the output transistor for the device is
missing and must be provided by the user before the circuit
is complete. Page 17-12.
program The 16-bit register in the 8080 chip that contains the memory
counter address of the next instruction byte that must be executed
in a computer program. Pages 18-8 and 18-49.
A-I7
stack pointer The 16-bit register in the 8080 microprocessor chip that
stores the memory address of the top of the stack, which is
a region of read/write memory that stores temporary
information. Page 18-11.
to synechrontze To lock one element of a system into step with another. Page
16-17.
timing loop A software loop that requires a precise period of time for
its execution. Page 17-3.
TRI-STATE ® device See three-state device. Page 19-3 and Unit Number 19.
There also exist the LR-l power Outboard and the LR-25 breadboarding station Outboard.
POWER OUTBOARDS
Power is applied to a separate SK-10 breadboarding socket with the aid of the LR-1
Outboard (Figure A-2) or a similar circuit on the LR-25 Breadboarding Station
Power
Rev. 9/22/77
A-20
GROUND pin
A LED lamp monitor is a light-emitting diode (LED) that is lit in the logic 1 state
the logic 0 state. It is used as display for binary digital signals.
and unlit in
LR-25
The LR-6 LED Lamp Monitor Outboards contains four LED lamp monitors, and the
Outboard contains eight LED lamp monitors. The former is shown in Figure
monitor
The use of transistor LED lamp drivers reduces the current to each lamp
to a level of only 1.5 mA.
PULSER OUTBOARDS
o Single bits
The logic states of individual flags, the outputs from gates, and the
outputs from flip-flops.
o Four bits
For the display of single bits, the LR-6 Outboard ts employed. For the display
of four bits, the LR-6 Outboard, LR-4 Seven-segment LED Display Outboard
(Figure
A-8), or LR-26 Latch/Display Outboard (Figure A-9) are used, The seven-segment
Outboard contains a display in which seven segments ate spatially arranged
in
such a manner that the digits 0 through 9 can be represented through the
selective
lighting of certain segments. On the LR-4 Outboard there is a 7447 decoder/driver
integrated circuit chip, a Hewlett-Packard 5082-7730 or Opcoa SLA-1 numeric
display, and seven current-limiting resistors to prevent the display from burning
out. The four inputs, ABCD, to the Outboard generate 0 through 9, five
unusual
symbols, and a blank display, t.e., the four inputs generate sixteen
unique display
states. Also present on the Outboard are three additional inputs to the 7447
chip,
the BLANKING INPUT (1), BLANKING OUTPUT (0), and LAMP TEST (T).
Rev. 9/22/77
A-25
Rey. 9/22/77
\-26
For the display of eight-bit octal code, which is discussed in Unit Number i
the LR-27 Octal Latch/Display Outboard is used. This Outboard contains three
sets of numeric indicators, as shown in Figure A-10, each of which has its
D input grounded. Two sets of indicators have A, B, and C inputs, whereas the
third set has the C input grounded and only A and B inputs. The strobe (STB)
inputs to the three indicators are tied together so that you can store an
entire eight-bit three-octal-digit word. This Outboard is specifically for use
as a bus monitor on the Dyna-Micro microcomputer. It permits you to monitor many
of the data transfers over the 8080A microprocessor data bus, which is an eight-bit
data bus.
For the display of several decimal digits each of which is encoded in four-bit
BCD code, the LR-28 Three Digit Latch/Display Outboard is used. This Outboard
contains three numeric or hexadecimal indicators and three sets of ABCD inputs
to each indicator. The strobe inputs to all three indicators are tied together
so that you can store a three-decimal number. A pair of indicators on this
Outboard can also be used to monitor an eight-bit microcomputer byte in two-
hexadecimal-digit code. This Outboard is shown in Figure A-11 on the following
page.
CLOCK OUTBOARDS
A clock is any device that generates at least one elock pulse, which is a complete
0, or
logic cycle, t.e., a transition from logic 0 to logic 1 and back to logic
a transition from logic 1 to logic 0 and back to logic 1. We have repeated this
very important definition for a clock pulse in our description of the pulser
Outboards. The LR-5 Clock Outboard (Figure A-12), which is also present on the
LR-25 Outboard (Figure A-3), generates a sequence of clock pulses, called a
train of clock pulses, the frequency of which depends upon the value of the timing
clock Outboard.
capacitor that is inserted into the socket pins associated with the
Outboards.
Such socket pins are easily identifiable on both the LR-5 and LR-25
Outboard is
In the absence of an inserted capacitor, the frequency of the clock
Suitable capacitors range from 10 pF to 100 uF. If you
approximately 90 kHz.
socket pin; for
use electrolytic capacitors, you will have to locate the negative
The heart of
the LR-5 Outboard, it is the pin directly below the letters LR5.
which provides
these clock Outboards is the 555 timer integrated circuit chip,
that has a frequency stability of better than 0.1%. On the LR-5 Outboard, a LED
operating properly.
indicator gives you a visual indication that the clock is
0.7 Hz; your
A 0.33 UF capacitor provides a clock frequency of approximately
+ 20% of this
clock frequency for an identical timing capacitor may vary within
The correct output pin from this Outboard is labeled CLK. External
value.
the upper frequency
resistors may be added at the remaining input pins to increase
limit of the LR-5 Outboard. The correct output pin from the LR-25 Outboard is
labeled CK, as shown in Figure A-3.
and A-13,
The LR-25 Breadboarding Station Outboard, shown in both Figure A-3
individual Outboards
consolidates the LR-1, LR-2, LR-5, LR-6 (two), LR-7, and LR-26
digital electronics
into a single Outboard that serves as essentially a complete
With it, you can perform any experiment that requires
breadboarding station.
one clock, eight lamp
no more than four logic switches, two debounced pulsers,
to four of the lamp monitors.
monitors, and a latch-display that is tied in parallel
A-28
In a subsequent module, you will learn how to decode the microcomputer device
codes to produce individual device select pulses that you can use to enable
or disable digital electronic devices. The LR-22 Decoder Outboard, which is
shown in Figure A-14, contains a single 74154 4-line-to-16-line integrated
circuit chip and a 16-pin DIP socket. This Outboard can be used to supplement
the five device select outputs that are already present on the Dyna-Micro
microcomputer (in the I/O decoder block). Each LR-22 Outboard can generate
sixteen different device select pulses.
MONOSTABLE OUTBOARD
A monostable multivibrator is a digital circuit that has only one stable state,
from which it can be triggered to change the state, but only for a predetermined
time interval, after which it returns to the original state. Such a circuit
can be used to generate individual clock pulses of precise time duration. The
LR-20 Monostable Outboard (Figure A-15) contains a 74122 retriggerable monostable
multivibrator chip that generates single clock pulses with the aid of a small
25 kQ potentiometer and external capacitors. Pulse widths ranging from 70 ns
to 5 ms can be readily generated.
‘LATCH OUTBOARD
A muiltiplemer is a digital device that can select one of a number of inputs and
pass the logic state of that input on to the output. This device acts as a uni-
directional single-pole multiposition switch that passes information only from
input to output. The LR-23 Multiplexer Outboard contains a 16-line-to-l-line 74150
multiplexer/data selector integrated circuit chip. The Outboard is shown in
Figure A-17,
COUNTER OUTBOARDS
The LR-17 Decade Counter and LR-18 Binary Counter Outboards are based, respectively,
on the popular 7490 and 7493 integrated circuit chips. A decade counter is a
states
logic device that has ten stable states and may be cycled through these
by the application of ten clock or pulse inputs. A decade counter usually counts
back to state 0.
in a binary sequence from state 0 through state 9 and then cycles
It is sometimes referred to as a divide-by-10 counter. A 4-bit binary counter
through these
is a logic device that has sixteen stable states and may be cycled
states by the application of sixteen clock or pulse inputs. Shown in Figure
A-18, each counter Outboard contains a DPDT switch which permits either a free
The
running counter or else a counter that can be reset to 0 from a remote input.
LR-17 Decade Counter Outboard can also be remotely reset to 9.
DRIVER/INVERTER/NOR OUTBOARD
Et
A teletype can transmit or receive ASCII code only via 20 mA current loops, which
are also discussed in Bugbook IIA. The LR-14 TTL/20 mA Current Loop Interface
Outboard contains a pair of GE 4N35 opto-isolators and an on-board 20 mA current
regulator. This Outboard interfaces a UART chip to any asynchroous device operating at
data transmission rates as high as 30,000 bits/second. See Figure A-2l.
If you desire to transmit or receive ASCII code via a modem tied to a telephone
line, you will need to convert TTL signals to RS-232C digital signals. The
very simple LR-13 Line Driver/Receiver and TTL/RS-232C Interface Outboard
(Figure A-22) permits you to do so. The Outboard contains a Signetics 8T15 dual
that
line driver and a 8T16 dual line receiver, plus two Zener diodes that ensure
only +12 volts is applied to the line driver chip. The Outboard is described
in greater detail in Bugbook ITA.
integrated
The LR-10 Programmable Timer Outboard is based upon the XR-2240/2340
in-line
circuit chip, which is a programmable timer/counter in a 16-pin dual
package (DIP). A programmable socket, shown in Figure A-23 programs the chip
etc.
as a timer, delay circuit, monostable multivibrator, staircase generator,
the
The circuit in the figure is for a simple programmable clock, in which
fundamental,
following clock frequencies can be produced as multiples of the
or lowest, clock frequency at output pin 0:
Multiple of
fundamental
Output pin frequency
0 i
ik Z
2 4
3) 8
4 16
5 32
6 64
7) 128
OCTAL HEX OCTAL HEX OCTAL HEX OCTAL HEX OCTAL HEX
000 00 063 33 146 66 231 99 314 CG
001 on 064 3h 147 67. 232 9A 315 cD
002 Q2 065 35 150 68 233 9B 316 CE
003 03 066 36 151 69 234 9C 317 CF
004 04 067 37 152 6A 235. 9D 320 DO
005 05 070 38 153 6B 236 9E 321 D1
006 06 O71 39 154 6C 237 oF 322 D2
007 07 072 3A 155 6D 240 AO 323 D3
010 08 073 3B 156 6E 241 Al 324 D4
011 09 074 3c 157 6F 242 A2 325 D5
012 OA 075 3D 160 70 243 A3 326 D6
013 OB 076 3E 161 71 244 A4 327 D7
014 oc 077 3F 162 1 245 A5 330 D8
015 OD 100 40 163 73 246 A6 331 D9
016 OE 101 4l 164 74 247 A7 332 DA
017 OF 102 42 165 75 250 A8 333 DB
020 10 103 43 166 76 251 AQ 334 DC
021 11 104 44 167 77 252 AA 335 DD
022 112 105 45 170 78 253 AB 336 DE
023 13 106 46 17 79 254 AC 337 DF
024 14 107 47 172 7A 255 AD 340 EO
025 15 110 48 173 7B 256 AE 341 El
026 16 111 49 174 7C 257 AF 342 E2
027 17 112 4A 175 7D 260 BO 343 E3
030 18 113 4B 176 7E 261 Bl 344 E4
031 19 114 4C 77 7F 262 B2 345 E5
032 1A 115 4D 200 80 263 B3 346 E6
033 1B 116 4E 201 81 264 B4 347 E7
034 1c 117 4F 202 82 265 BS 350 E8
035 1D 120 50 203 83 266 ~ B6 351 E9
036 1E 121 51 204 84 267 B7 352 EA
037 1F 122 52 205 85 270% B8 353 EB
040 20 123 53 206 86 Till B9 354 EC
041 21 124 54 207 87 272 BA 355 ED
042 22 125 55 210 88 73) BB_* 356 EE
043 23 126 56 211 89 274 BC 357 EF
044 24 127 57 1 8A 275 BD 360 FO
045 25 130 58 213 8B 276 BE 361 Fl
046 26 131 59 214 8C Dail BF 362 F2
047 Dy 132 5A 215 8D 300 co 363 F3
050 28 133 5B 216 8E 301 Cl 364 F4
051 29 134 5¢ 217 8F 302 C2 365 F5
052 2A 135 5D 220 90 303 C3 366 F6
053 2B 136 5E OAL 91 304 C4 367 F7
054 2¢ 137 5F 222 92 305 C5 370 F8
055 2D 140 60 223 93 306 C6 371 F9
056 2E 141 61 224 94 307 C7 372 FA
057 2F 142 62 225 95 310 C8 373 FB
060 30 143 63 226 96 311 C9 374 FC
061 31 144 64 227 97 312 CA 375 FD
062 32 145 65 230 98 313 CB 376 FE
377 FF
APPENDIX 6: DESCRIPTION OF THE MMD-1 MICROCOMPUTER
INTRODUCTION
In this appendix, you will learn how an 8080 (or 8080A) microprocessor chip
can be used to configure a small 8080-based microcomputer. You will examine
the signals entering and leaving the 8080 chip, how auxiliary chips such as
the 8224 are used to control the operation of the microcomputer, and the
development of the address, data, and control buses, which are vital in
interfacing applications. The microcomputer has been previously described
in the May, June, and July, 1976 issues of Radio-Electronics magazine. The
reader is referred to these articles or to the E&L Instruments, Inc. MMD-1
Mint Miero-Desitgner Operating Manual for additional details on the assembly
and operation of the microcomputer.
OBJECTIVES
o Identify the memory address bus, data bus, control inputs, control
outputs, and power inputs on the 40-pin 8080A microprocessor chip.
1
2
3 Ay3
4
5
6
7
8
ie Figure A6-1. The pin configuration of
9
As the 40-pin 8080 microprocessor chip.
Se
Se)
eee
es
SOoMnYHFHFHPWNAS
8-bit bidirectional
data bus.
intel Silicon Gate MOS 8080A
A-39
= =
The Intel® 8080A is acomplete 8-bit parallel central processing unit (CPU). It is fabricated on a single LSI chip using Intel’s
n-channel silicon gate MOS process. This offers the user a high performance solution to control and processing applications.
The 8080A contains six 8-bit general purpose working registers and an accumulator. The six general purpose registers may be
addressed individually or in pairs providing both single and double precision operators. Arithmetic and logical instructions set
or reset four testable flags. A fifth flag provides decimal arithmetic operation.
The 8080A has an external stack feature wherein any portion of memory may be used as a last in/first out stack to store/
retrieve the contents of the accumulator, flags, program counter and all of the six general purpose registers. The sixteen bit
stack pointer controls the addressing of this external stack. This stack gives the 8080A the ability to easily handle multiple
level priority interrupts by rapidly storing and restoring processor status. It also provides almost unlimited subroutine nesting.
This microprocessor has been designed to simplify systems design. Separate 16-line address and 8-line bi-directional data
busses are used to facilitate easy interface to memory and 1/O. Signals to contro! the interface to memory and 1/O are pro-
vided directly by the 8080A. Ultimate control of the address and data busses resides with the HOLD signal. It provides the
ability to suspend processor operation and force the address and data busses into a high impedance state. This permits OR-
tying these busses with other controlling devices for (DMA) direct memory access or multi-processor operation.
DATA BUS
BUFFER/LATCH
Wr (8 BIT)
INTERNAL DATA BUS INTERNAL DATA BUS
ACCUMULATOR INSTRUCTION
(8) REGISTER (8)
Ww (8) Z 8)
PROGRAM COUNTER
DECIMAL INCREMENTER/DECREMENTER
ADJUST ADDRESS LATCH (16)
TIMING
ANDO
CONTROL
(16)
POWER _| — +12V ADDRESS BUFFER
SUPPLIES | ——» 45v DATA BUS INTERRUPT HOLD WAIT
WRITE CONTROL CONTROL CONTROL CONTROL SYNC CLOCKS
—> -5V
—> GND
WR DBIN INTE INT HOLD HOLDWAIT SYNC 41 062 RESET roe
~
READY
ale ADDRESS BUS
This and subsequent specification sheets are courtesy of the Intel Corporation,
Santa Clara, California. All rights reserved.
Forty pins are quite a few with which to contend, so it would be useful to sub-
divide the pin functions into the following categories: power, memory address
bus, bidirectional data bus, control signals, and clock inputs.
POWER
pin 28 + 12 Volts
pin 20 +) Volts
pin 2 GROUND
pin 11 - 5 Volts
The voltage tolerances are + 5% with respect to ground potential. Any popular
power supply that provides voltages of + 15 and + 5 Volts and sufficient current
can be adapted to the 8080 chip with the aid of suitable voltage regulators.
CLOCK INPUTS
The 8080 chip requires a two-phase clock. Recall that a clock is any device
that generates at least one clock pulse, or a timing device in a system that
provides a continuous series of timing pulses. A two-phase clock is a two-output
timing device that provides two continuous series of timing pulses that are
synchronized together, with a single clock pulse from the second series always
following a single clock pulse from the first seriés. The use of timing diagrams,
shown in Figure A6-3, is helpful in explaining how a two-phase clock operates:
/— 500 ns —
Mee Ll ga Lee me ie or
Time —
Figure A6-3. Schematic diagram of the two-phase clock inputs to the 8080 chip.
Note that the leading edge of the $, series of clock pulses almost overlaps the
trailing edge of the $¢, series of pulses. In the 8080 specifications, it is
stated that the minimum pulse width for the $, clock phase is 60 nsec, whereas
for the $2 clock phase it is 220 nsec. The pin locations on the 8080 chip for
the two input clock signals are:
CONTROL SIGNALS
The control signal pins determine how the microprocessor functions in a micro-
computer system. In discussing the functions of these pins, we have not been
able to sidestep a variety of jargon, such as T1, 72, T3, 1,,, feteh eyele, My,
and related terms. We provide pin identifications and descriptions in the
listing below for future reference, when you have a better understanding of the
operation of the 8080 microcomputer.
Note that you will not see either the IN or OUT control signals in the listing
below. The reason is that these two functions are generated as status bits,
which are externally latched using latch chips such as the 74174 or 8212 and
used to generate the IN and OUT synchronization pulses mentioned previously.
The same comments apply to the generation of the control signals, MEMR, MEMW,
and INTA.
pin 12 (input) RESET. A logic 1 at this input will clear the program
counter register and allow the program to start at
memory location HI = 000 and LO = 000. The INTE and
HLDA flags are also reset, but the condition flags,
accumulator register, stack pointer register, and general
purpose registers are not cleared.
pin 23 (input) READY. A logic 1 indicates to the 8080 that valid memory
or input data is available on the data bus lines, DO through
D7. This signal is used to synchronize the CPU with slower
memory or with I/O devices. If, after sending an address
out on the address bus, the 8080 does not receive a logic 1
A-Li5
pin 13 (input) HOLD. This input pin requests the CPU to enter the HOLD
state, which allows an external device to gain control
of the 8080 address and data buses as soon as the 8080
has completed its use of these buses for the current
machine cycle. Once the CPU enters the HOLD state, the
address bus and the bidirectional data bus are in their
high impedance states. HOLD is active in the logic 1 state.
So much for the control inputs. Now let us summarize the control outputs, many of
which are flags, which can be defined as:
The six control output pins on the 8080 microprocessor chip are:
pin 24 (output) WAIT. The wait output signal acknowledges that the
central processing unit is in a WAIT state. When in a
WAIT state, this pin is at logic l.
pin 18 (output) WR, or WRITE. This output pin is used for memory WRITE
or I/O output control. When this pin is at logic 0,
the data on the data bus is stable and can be written
into memory or an I/O device.
pin 16 (output) INTE, or INTERRUPT ENABLE. This pin indicates the content
of the internal interrupt enable flip-flop. This flip-flop
may be set or cleared by the enable and disable interrupt
instructions (EI and DI, respectively) and inhibits
interrupts from being accepted by the CPU when the flip-
flop is cleared. The flip-flop is automatically cleared
(thus disabling further interrupts) at time Tl of the
instruction fetch cycle (Ml) when an interrupt is accepted.
The flip-flop is also cleared by the RESET control input.
pin 17 (output) DBIN, or DATA BUS IN. When this pin goes to a logic 1,
it indicates to external circuits that the data bus is
in the input mode. This pin should be used to enable
the gating of data onto the 8080 data bus from memory
or t/O devices.
In early 8080 microcomputer systems, the clock inputs were provided by transistor
driver circuits, MOS clock driver chips, or even open collector TTL buffer
chips. All worked reasonably well, but they complicated the design. A recent
8080 interface chip, the 8224 clock generator and driver, contains an internal
oscillator and a clock generator/driver. All you need to provide is the
appropriate crystal as well as power supply voltages of +5 and +12 Volts. Since
the 8224 will divide the crystal frequency by nine, you will require a 6.750
MHz crystal to produce a 750 kHz clock output from the clock generator.
The Intel spedification sheets for the 8224 clock generator/driver are shown on
the following pages. The functional description of the chip is excellent, so we
need not repeat it. Observe how the divide-by-nine counter circuit within the
8224 chip is used to generate the individual clock phases $9) and $2, which
"swing" between +12 Volts and ground.
~
The inputs to and outputs from the 8224 chip can be summarized as follows:
pin 2 (input) RESIN. With the aia of a Schmitt trigger circuit that
is internal to the chip and an external RC network,
this input converts a slow transition in the power supply
to a clean, fast edge that resets the 8080 microprocessor
chip. A RESET output pulse can also be obtained by
applying a logic O at RESIN.
pin 1 (output) RESET. A logic 1 from this output pin applied at the
RESET input of the 8080 chip will reset the 8080.
pin 5 (input) SYNC. The SYNC pin on the 8080 chip provides a synchro-
AUS
intel Schottky Bipolar 8224
CLOCK GENERATOR AND DRIVER
FOR 8080A CPU
= Single Chip Clock Generator/Driver = Oscillator Output for External
for 8080A CPU System Timing
@ Power-Up Reset for CPU = Crystal Controlled for Stable System
™ Ready Synchronizing Flip-Flop Operation
w Advanced Status Strobe = Reduces System Package Count
by a crystal, selected by
The 8224 is a single chip clock generator/driver for the 8080A CPU. It is controlled
the designer, to meet a variety of system speed requirements.
synchronization of ready.
Also inc!uded are circuits to provide power-up reset, advance status strobe and
and timing
The 8224 provides the designer with a significant reduction of packages used to generate clocks
for 8080A.
F BLOCK DIAGRAM
PIN CONFIGURATION
fs> xTAU
OSCILLATOR osc [i2>
14> XTAL2
TANK o,(TTU[6>
penne
SYNC ose
¢ =
: 5> SYNC stste [7>
CONNIE ;
STSTB $2 [=>
vs RESINiN
GND Yoo SCHMITT
INPUT Reset [1 >
Cc
PIN NAMES
1 .
Crystal Frequency = — times 9 XTALI
CY
XTAL2
Example 1: (500ns tcy) fs> tank
2mHz times 9 = 18mHz™
ey {>
Example 2: (800ns tcy)
2
1.25mHz times 9 = 11.25mHz
9(TTU[6>
5-2
SCHOTTKY BIPOLAR 8224
A-47
STSTB (Status Strobe) The READY input to the 8080A CPU has certain timing
specifications such as ‘‘set-up and hold” thus, an external
At the beginning of each machine cycle the 8080A CPU is-
synchronizing flip-flop is required. The 8224 has this feature
sues status information on its data bus. This information
built-in. The RDYIN input presents the asynchronous “‘wait
tells what type of action will take place during that machine
request’’ to the ‘‘D” type flip-flop. By clocking the flip-flop
cycle. By bringing in the SYNC signal from the CPU, and
with 2D, a synchronized READY signal at the correct in-
gating it with an internal timing signal (1A), an active low
put level, can be connected directly to the 8080A.
strobe can be derived that occurs at the start of each ma-
chine cycle at the earliest possible moment that status data The reason for requiring an external flip-flop to synchro-
is stable on the bus. The STSTB signal connects directly to nize the ‘‘wait request’ rather than internally in the 8080
the 8228 System Controller. CPU is that due to the relatively long delays of MOS logic
such an implementation would “rob” the designer of about
The power-on Reset also generates STSTB, but of course, 200ns during the time his logic is determining if a ‘‘wait’’
for a longer period of time. This feature allows the 8228 to is necessary. An external bipolar circuit built into the clock
be automatically reset without additional pins devoted for generator eliminates most of this delay and has no effect on
this function. component count.
LJ
FOR OVERTONE
to the RESIN input in addition to the power-on RC net- CRYSTALS
network. —T 7 3-10 pF
| (ONLY NEEDED
4 ABOVE 10 MHz)
OSCILLATOR
=> SYNC
& RESIN
STSTB (TO 8228 PIN 1)
[32> RovIN
5-3
ALS
pin 11 (output), >, and $9. The two-phase clock that is input into the
pin 10 (output) 8080 chip. These two outputs "swing" between +12 Volts
and ground; they are not normal TTL outputs.
pin 6 (output) o2(ITL). This is a TTL output clock that has the same
frequency and timing characteristics as does $2. It is
used for external timing purposes.
pin 7 (output) STSTB. Status strobe output. This output pin is used
to latch status bits that appear on the bidirectional
data bus.
pin 12 (output) OSC. Buffered crystal oscillator output signal that can
be used to generate other system timing signals.
It should be clear that the 8224 clock generator/driver chip is well designed for
its particular function. Connections between it and the 8080 microprocessor
chip are direct, and require no intermediate inverters, gates, or flip-flops.
There is little incentive to use transisistor driver circuits, MOS clock driver
chips, or open collector TTL buffer chips. The power to the 8224 chip is
already available, since both +5 Volts and +12 Volts are required by the 8080.
Shown in Figure A6-4 is the central processor section of the MMD-1 microcomputer.
The figure is provided courtesy of Radio-Electronics magazine, which described
the microcomputer in the May, June, and July, 1976 issues. We would now like to
examine the component chips in the circuit as well as the signal flow between
them. Our objective here is to demonstrate that a microcomputer is a very
straightforward and reasonable device, and that you should not feel intimidated
by a circuit diagram such as given in Figure A6-4, %
POWER 2
.
It is assumed that power supplies for the required +5 Volts, -12 Volts, and
+12 Volts are available. They are relatively inexpensive, but be wary of the
very cheap supplies. The intermediate voltages of -5 Volts and -9 Volts
required by our microcomputer are easily derived from voltage regulator inte-
grated circuit chips such as the LM320 series, or from zener diode shunts, as
shown in the upper left-hand corner of Figure A6-4. The zener diodes IN746
(chip D26) and IN751A (chip D25) provide the -9 Volts for the EPROMS and the
-5 Volts for pin 11 on the 8080A chip.
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use it in the MMD-1 microcomputer. Even a fan-out of 1 is insufficient to drive
the required memory chips and output latches. Consequently, 8216 bus drivers
are also required. These will be described below under the bus driver
sub-section. The specification sheet for the 8080A chip has been shown previously.
CONTROL LINES ~
The control section of the MMD-1 microcomputer is shown at the lower left-hand
corner of Figure A6-4 and consists of the 8224 clock generator/driver chip
connected directly to the 8080A, a pair of 1 kQ resistors, a reset switch, and
a 6./50 MHz crystal. The remaining control lines on the 8080A chip, those not
connected to the 8224 chip, are HOLD, HLDA, INTE, INTERRUPT, WAIT, WR, and
DBIN. Five of these lines are not used in the MMD-1 microcomputer, but are made
available if you wish to experiment with them. The HOLD input permits you to
drive the 8080A chip into the hold state and disable the address and data buses.
The HLDA control output acknowledges the existence of a hold state. The
INTERRUPT input permits you to interrupt the 8080A program execution, provided
that the interrupt flip-flop within the 8080A chip is enabled. If it is enabled,
the INTE output is at logic 1. Finally, the WAIT output permits the 8080A chip
to signal that it is not ready or that it is waiting for some external event.
If the HOLD input to the 8080A pin 13 is not used, it must be grounded. This
is easily accomplished with the aid of a jumpber, as shown in Figure A6-4.
The final two control lines are both outputs. The WRITE (WR) signal is active
when at logic 0, and indicates that the 8080A chip is sending data out to some
device. The remaining signal, DATA BUS IN (DBIN), indicates that the data bus
is being used for the input of data. It is active in the logic 1 state. In
the 8080A chip and other related microprocessor chips, the data bus is bidirectional,
i.e., data transfers into and out of the chip occur over the same wire connections.
Careful management of the data bus is necessary for the data to flow properly.
This data bus management capability is built into the microprocessor chip itself,
but we must make certain that our external devices do not attempt to place their
data on the bus at the same time, or when some other device or perhaps the 8080A
chip is trying to use it. Only one device should be transmitting data over the
data bus at any given instant of time.
x
BUS DRIVERS
2
In order to drive the memory chips and output latches on the MMD-1 microcomputer,
a fan-out of at least ten is required for each output line on the data bus.
In addition, the bidirectional character of the data bus must be maintained.
The device used to accomplish such objectives is the Intel Corporation 8216
4-bit parallel bidirectional bus driver chip, the specifications of which are
shown, courtesy of the Intel Corporation, on the following several pages.
Consider output DBy in the 8216 logic diagram. The following truth table applies:
DI, > DB), i-e., data is output from the 8080A chip
ah 0 DB) > DI)» i.e., data is input into the 8080A chip
= Data Bus Buffer Driver for 8080 CPU = 3.65V Output High Voltage for Direct
# Low Input Load Current — .25 mA Interface to 8080 CPU
Maximum = Three State Outputs
= High Output Drive Capability for = Reduces System Package Count
Driving System Data Bus
A non-inverting (8216) and an inverting (8226) are available to meet a wide variety of applications for buffering in micro-
computer systems.
—
Dl, oO Poo ae
t— DB, ——— ¢——_-© 98,
00, o— mer dhe DO, Oo = oc]
——--9
Dl, © — ll Dl, o +. Po
Ce DB, ——— o——_-O DB,
—— DB,
DO, o—
Di,
DB,
| 0B,DB, DO,
_ i dnd
D1, Di, | DATA INPUT
bt. ~—
DO,-00,) DATA OUTPUT
Dien” | DATA IN ENABLE |
DIRECTION CONTROL |
ae Ps
cs | CHIP SELECT ‘ © CS
DIEN DIEN
5-147
\-52 SCHOTTKY BIPOLAR 8216/8226 7
FUNCTIONAL DESCRIPTION
5-148
SCHOTTKY BIPOLAR 8216/8226
APPLICATIONS OF 8216/8226
The bus driver section of the MMD-1 microcomputer is*shown in the lower left-hand
corner of Figure A6-4, to the right of the 8080A chip. Observe that DBIN is
connected to DIEN (pin 15 on the 8216 chip) and that each 8216 chip is permanently
enabled. The truth table relating DBIN and DIEN is,
DBIN DIEN
According to the Intel Corporation specification sheets for the 8216, the absolute
maximum output current at a logic 0 state is 125 mA, which is a substantial drive
capability.
STATUS INFORMATION
If you carefully study the Intel specification sheets for the 8080A microprocessor
chip, you will observe that certain important control signals are not present on
the chip itself. Included among these signals are memory read (MEMR), memory
write (MEMW), input (IN), output (OUT), and interrupt acknowledge (INTA). To
generate such control signals, the 8080A chip uses a "look ahead" technique:
since the data bus is not in use at all times for data transfer, the 8080A can
use the bus to transfer additional control information. Such information is
generated very early in the machine cycle to permit the microcomputer to use such
control signals to facilitate the transfer of data to or from memory and I/O
devices. ;
The status information appears on the data bus for a very short period of time,
approximately 1.33 us for an 8080 system operating at a 750 kHz clock rate.
Since the information is to be used at a later time, it must be latched. The
SYSTEM STROBE (STSTB) is generated at pin 7 on the 8224 chipxat the correct time
to latch, or capture, the status information. Note that the STSTB signal is
generated from the system clock signal $; and the SYNC signal from the 8080A.
Any type of 8-bit latch chip may be used. At the lower middle portion of Figure
A6-4, a 74174 6-bit positive-edge triggered latch chip is employed; it is clocked
at pin 9.
All eight bits on the data bus provide some sort of status information, but not
all eight are needed. The information provided by Intel Corporation on the
status bits and types of machine cycles is given on the following page. In
the MMD-1 microcomputer, the WO and STACK status signals are ignored since they
are not very useful. HLTA and Ml are latched but are not used either. The
important status signals are INTA (interrupt acknowledge), INP (input), OUT
(output), and MEMR (memory read). Together with the DBIN and WR outputs from
the 8080A chip, these four signals provide five very important control signals
that basically comprise most of the control bus on the MMD-1 microcomputer:
A-55
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A-50
MEMR. Memory read. Used to strobe data from a memory chip into the
8080A microprocessor chip.
MEMW. Memory write. Used to strobe data output from the 8080A chip
into read/write memory.
»
IN. Input. Used to strobe data from an input device into the accum-
ulator within the 8080A chip.
OUT. Output. Used to strobe data from the accumulator into an output
device external to the 8080A chip.
The other signals associated with the control bus are RESET, INT (interrupt
request), and INTE (interrupt enable). These eight control signals permit
you to read and write into and from memory and input-output devices. They
also allow you to process interrupts.
There is now a system controller and bus driver chip, the Intel 8228, that
performs both the bidirectional data bus buffering as well as the latching
and gating of the status signals. A typical interface circuit, courtesy of the
Intel Corporation, is shown on the following page. A special feature of the 8228
chip is that it can generate three INTA pulses in sequence during an interrupt
request; this feature is required when you attempt to strobe a two- or three-byte
instruction into the instruction register. One problem with the 8228 chip is
that it is expensive. The data bus buffering is limited to a standard fan-out of
10 TTL loads, or 16 mA current sink capability.
MEMORY
The necessary control section for the 8080A chip, inclauding the status latch
and associated status bits, has been discussed. We are now ready to add external
devices to the MMD-1 microcomputer. The first such devices that will be needed
are semiconductor memory chips. Semiconductor memory comes in various forms and
types, but we shall only consider two types, read/write memory and electrically
programmable read-only memory (EPROM), both of which are randoti access memories.
Random access means that any single memory location may be accessed
after any
other location.
We have chosen the 2111 (or 8111) read/write memory chip, the specificati
on sheet
for which is given on a following page, since it is easy to interface to the
8080A. It is organized as 256 memory locations each with four bits per location,
i.e., it is a 1024-bit memory chip. The 8111-2 has common input and output lines
(1/0) over which data is transferred to and from the 8080A microproces
sor chip.
Clearly, these I/O lines are bidirectional. Each 8111-2 memory chip has eight
address inputs (AO through A7) to uniquely define a single
memory location among
the 256 possible locations. The control inputs to the 8111-2 include the read/
write input (R/W), two chip enable inputs (CE, and CE,), and an output disable
input (OD).
Since the word length in each 8111 chip is only four bits, pairs
of such chips
must be enabled and disabled simultaneously in order to provide
the 8-bit word
required by the 8080A microprocessor chip. Figure A6-4 demonstrates that MEMW
(memory write, or MW) is connected to pin 16 and that MEMR (memory read, or MR)
is connected to pin 9 on the 8111 read/write memory chip.
Assuming that the
SCHOTTKY BIPOLAR 8228 A-57
}- ADDRESS BUS
13
SYSTEM DMA REQ, ————>|
INT. ENABLE
oo (TTL) —___—
3 3 oa 8228 we)
RDYIN ——| eae eet ae —_—_—_—_ DB,
5-12
4.53 intel Silicon Gate MOS 8111-2
1024 BIT (256 x 4) STATIC MOS RAM
WITH COMMON I/O AND OUTPUT DISABLE
® Organization 256 Words By 4 Bits Fully Decoded — On Chip Address
=®Access Time — 850 nsec Max. Decode
= Common Data Input and Output Inputs Protected — All Inputs Have
Protection Against Static Charge
# Single +5V Supply Voltage
= Directly TTL Compatible — All Inputs Low Cost Packaging — 18 Pin Plastic
and Output Dual-In-Line Configuration
® Static MOS — No Clocks or Low Power — Typically 150 mW
Refreshing Required Three-State Output — OR-Tie
® Simple Memory Expansion — Chip Capability
Enable Input
The Intel 8111-2 is a 256 word by 4 bit static random access memory element using normally off N-channel
MOS devices integrated on a monolithic array. It uses fully DC stable (static) circuitry and therefore requires
no clocks or refreshing to operate. The data is read out nondestructively and has the same polarity as the
input data. Common input/output pins are provided.
The 8111-2 is designed for memory applications in small systems where high performance, low cost, large bit
storage, and simple interfacing are important design objectives.
It isdirectly TTL compatible in all respects: inputs, outputs, ancka single +5V supply. Separate chip enable
(CE) leads allow easy selection of an individual package when outputs are OR-tied.
The Intel 8111-2 is fabricated with N-channel silicon gate technology. This technology allows the design and
production of high performance, easy-to-use MOS circuits and provides a higher functional density on a mon-
olithic chip than either conventional MOS technology or P-channel silicon gate technology.
Intel’s silicon gate technology also provides excellent protection against contamination. This permits the use
of low cost silicone packaging.
A Ps 18
G ae GG
Ae ®
>) j— MEMORY ARRAY OND,
A =
Pema etree
ROW
32 ROWS
32 COLUMNS
DATA
CONTROL
PIN NAMES
aM 0 ut 0 Memory read
The decoding of the address bus is depicted in Figure A6-4 on the right-hand side
of the 8080A chip. The desired truth table for address bus bits AO through Al5 is:
One Olas Ome O nem One msOLamodL el. oe eX. X | Block 3 (reserved for 8111 R/W memory)
dOMoM
bX XO
XR
MX PO
PS
KH MM Pd
MO PO
MP O
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fee
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(eo
Ee)
Observe that this truth table, though implemented with open collector inverters,
is identical to that fora 6-input NOR gate. The unique logic state is Q = 1g
0.
and this output condition occurs only when all inputs are at logic
A-€0
Whenever the output from the wired-OR circuit is at logic 1, we know that A10
through Al5 are at logic O and that our memory address must be within one of
the four selected 256-byte blocks of memory. We must further narrow our memory
selection process to a specific memory block. This is done with the aid of a
74LS155 decoder chip, the block diagram and pin configuration of which are given
below, .
+5V GND
SELECT OUTPUTS :
DATA sTRB INPUT
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Block O
Block |
Block 2
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circuit
DATA STRBSELECT, 1¥3 1v¥2 ikl 1¥0, GNO
alen 1G) INPUT
B OUTPUTS
74155 74LS155
Figure A6-5. Pin configuration of the 74155 chip and diagram of the MMD-1 circuit.
The 74LS155 chip is enabled and disabled using the output from the wired-OR
circuit, where disabled corresponds to logic 0 (mo blocks selected) and enabled
corresponds to logic 1 (one and only one memory block selected). The truth
table for the 74LS155 chip is as follows: bs
0 0 None selected
al 0 Block 0 (read EPROM memory)
1 0 Block 1 (read EPROM memory)
uf 0 Block 2 (read R/W memory)
i 0 Blocl: 3 (read R/W memory)
1 iL None selected
il nh None selected
Al al Block 2 (write into R/W memory)
1 dl: PRHOOFRHOOS
FOPOFOHORM
PORPRPREPHBPFEOP
ORPRRFPRFPHOPRRH
PRRPEPRPORHRH
Block 3 (write
PRPRPRPORRRPE into R/W memory)
The outputs to blocks 2 and 3 go to the CE, inputs (pin 15) of the respective
pairs of 8111 read/write memory chips, as can be seen for Block 3 in Figure
A6-4. When pin 15 of the 8111 chip is at logic 0, the chip is enabled since
CE, is wired to logic 0.
*DATA OUT 1
*DATA OUT 2
*DATA OUT 3
"DATA OUT 4
*DATA OUT 5
*DATA OUT 6
*DATA OUT 7
*DATA OUT 8
Vec PROGRAM
1702A
8702A
Figure A6-6. Pin configuration of the 1702A/8702A chip. Some of the power input
pins are used only during programming. We shall assume here that the
chip has been properly programmed prior to its inclusion in the MMD-1
microcomputer.
Figure A6-6. Observe that there are eight address inputs, AO through A7, and
eight data output pins, DATA OUT 1 through DATA OUT 8, a chip select input
(pin 14), and several power input pins. In Figure A6-4, you can see how this
is incorporated into the MMD-1 microcomputer. Pins 12, 13, 15, 22, and
chip
23 are all tied to +5 Volts. Pins 16 and 24 are connected to -9 Volts. The
from the 74LS155 decoder chip is connected to the CS input of the
Block 0 output
1702A (pin 14). Observe that you can only read the 1702A chip; it is a
read-only memory chip, not a read/write memory chip.
INPUT/OUTPUT
section of the MMD-1 microcomputer is shown in Figure A6-7.
The input/output
this book, you have already become familiar with 1/0
In Unit Number 20 in
of 7475 latch chips and 8095 three-state buffer chips.
decoding and the use
discuss the I/O section of the MMD-1 only briefly here.
Consequently, we shall
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Chip 74L42 is wired as a 3-line-to-8-line decoder in Figure A6-7 and has the
following truth table:
Channels 0, 1, and 2 are gated with the OUT control signal and used to strobe
information from the bidirectional data bus into the latch chips for Ports 0,
1, and 2, respectively. Channel 0 is gated with the IN control signal and used
to strobe input data present at the 8095 three-state buffer chip into the 8080A
microprocessor chip. The inputsto the 8095 chip consist of the outputs from a
pair of 74148 8-line-to-3-line priority encoder chips, which are used to encode
the 15-key keyboard. Included in the keyboard are keys 0 through 7, the See/Store
key (S), the Go key (G), the HI address byte key (H), the LO address byte key
(L), and three additional keys (A, B, and C) that have no specified use. The
pin configuration of the 74148 chip and a truth table is provided in Figure A6-8.
are non-ideal mechanical switches that are debounced using software
The keys
routines.
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4 5 6 7 El A2 Al, GNO L x L BAe oH ibe A AAS 3 L H
INPUTS OUTPUTS 2 A es I a aa Wi ln Me) H]t_H
74148
Figure A6-8. Pin configuration and truth table for the 74148 priority encoder
chip.
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"The TIMOUT and KBRD software subroutines have specific tasks. The TIMOUT will
count its way through various loops for about 10 milliseconds, while the KBRD
subroutine will input a code from the keyboard. The KBRD subroutine has some
unique features that illustrite an interesting hardware-software tradeoff. The
keyswitches used in the Dyna-Micro [MMD-1] are not bounce free, so that when the
switches are opened or closed, they can often re-make or re-break the contacts.
This can be confusing to the computer since it can't distinguish between a real
switch closure and a bounce. We don't want the computer to sense each bounce
as a key closure so we would like some way to filter them out. Additional
circuitry including latches, clocks and monostables could do this for
us, but it
complicates the system. We can also do the debouncing via software."
"The KBRD subroutine will recognize any key closure, but it will only input the
key codes after being sure that the key is closed and not bouncing.
It does
this by waiting after sensing a closure and then rechecking the switch
to be
sure it is still closed. It also checks when we release a key to be sure that
it has stopped bouncing before it tries to sense another key
being depressed by
the user. We have traded some additional software steps for a great deal
of
hardware. Since there was plenty of PROM left, it was easy to include."
"The TIMOUT and KBRD software segments have been set ‘up as subroutines and can
be used in your software and in the experiments. Each of these subroutines may
be started with a CALL instruction, 315. The TIMOUT subroutine does not affect
any of the registers or flags and it only serves to delay the’ software flow by
10 ms."
"An important distinction between the 8008 and the 8080 processors
is in the use
of subroutines. In the 8008, return-pointer addresses were stored in the 8008
Ic itself. In the 8080, these return-pointer addresses are stored in a portion
of the R/W memory. This is called a "stack" area. Whenever a subroutine is
used, we want to execute the subroutine and then return
back to the normal program
flow. These return addresses are very important to the computer
since they
provide the only link between the subroutine and the
main program. If we are
to store them in a portion of R/W memory, the computer
must know where this
storage area is if it is to be able to use the addresses
properly. In the KEX
software, this is preset to be the top of the R/W
memory with instructions at
locations 070, 071 and 072. The LXISP instruction loads an internal 8080
stack-pointer register to HI = 004, LO = 000. Since the stack-pointer register
is decremented to point to a new location before anything is stored, the first
A-69
000 123 027 RAL
TABLE li—KEYBOARD EXECUTIVE (KEX) PROGRAM 000 124 027 RAL
000 125 346 ANI /MASK OUT LEAST
*000 000 SIG. OCTAL DIGIT
)00 000 303 JMP 000 126 370 370
070 START 000 2% 260 ORAB /OR IN NEW OCTAL
00 001
000 0 DIGIT
00 002
000 130 117 MOVCA /PUT NEW DATA
BACK INTO BUFFER
/JUMP UP TO R/W MEMORY TO
000 131 303 JMP
BE USED BY RESTARTS &
000 132 105 POINT B
VECTORED INTERRUPTS
600 133 000 0
*000 010 000 134 376 POINT D, CPI
303 JMP 000 135 011 oll (SE KEY
000 010
010 000 136 302 JNZ /JUMP IF NOT AN "L"
000 oll id
003 003 000 137 145 POINT E
000 Ole
*000 020 000 140 000 0
JMP 000 141 151 MOVLC /PUT BUFFER DATA
000 020 303
020 INL
000 021 020
003 003 000 142 303 JMP
000 O22
*000 030 000 143 O76 POINT A
303 JMP 000 144 000 0
000 030
000 031 030 030 000 145 376 POINT E, cPI
003 000 146 010 010 /"H" KEY
000 032 003
*000 040 000 147 302 JNZ / JUMP IF NOT AN "H"
JMP 000 150 156 POINT F
000 040 303
040 040 000 151 000 0
000 041 MOVHC /PUT BUFFER DATA
000 042 003 003 000 152 141
*000 J50 IN H
JMP 000 153 303 JMP
000 050 303
050 000 154 O76 POINT A
000 051 050
003 000 155 000 0
000 052 003
*000 060 000 156 376 POINT F, cPI
JMP 000 157 013 013 /"S" KEY
000 060 303 JNZ /JUMP IF NOT "S"
000 061 060 060 000 160 302
003 000 161 170 POINT G
000 062 003
000 162 000 0
000 163 161 MOVMC /PUT TEMP. DATA
/BEGINNING OF MAIN PROGRAM INTO MEMORY
*000 070 000 164 043 INHX /INCREMENT H & L
START, LXISP /SET STACK POINTER 000 165 303 JMP
000 070 061
TO TOP OF R/W MEM. 000 166 O76 POINT A
000 000 167 000 0
000 O71 000
004 000 170 376 POINT G, CPI
000 O72 004
300 O73 041 LXIH _/ INITIAL VALUE FOR 000 Pr 012 012 /"G" KEY
is) Bie, 000 We? 302 JNZ /JUMP IF NOT "G"
000 000 173 110 POINT C
000 074 000
003 000 174 000 0
000 075 003
000 O76 116 POINT A MOVCM /LOADMEM DATA INTO 000 175 351 PCHL /GO EXECUTE PGM
TEMP DATA BUFFER POINTED TO BY
MOVAH /OUTPUTHI TO LED'S H&L
000 O77 174
000 100 323 OUT /THIS 10 MSEC DELAY
000 101 001 001 DISTURBS NO REGISTERS OR
000 102 175 MOVAL /OUTPUT LOW TO FLAG
LED'S
000 103 323 OUT *000 277
000 104 000 000 000 realit 365 TIMOUT, PUSHPSW /SAVE REGISTERS
000 105 171 POINT B, MOVAC /OUTPUT TEMP. DATA 000 300 325 PUSHD
BUFFER DATA TO LXID /LOAD D & E WITH
LED'S VALUE TO BE
000 106 323 ouT 000 301 O21 DECREMENTED
000 107 002 002 000 302 046 046
000 110 315 POINT C, CALL /WAIT & INPUT NEXT 000 303 001 001
KEY CLOSURE 000 304 033 MORE, DCxD /JUMP IN THIS
000 111 315 KBRD LOOP UNTIL
000 112 000 0 000 305 172 MOVAD /D & E ARE BOTH
000 113 376 CPI ZERO
000 114 010 010 000 306 263 ORAE
000 115 322 JNC / JUMP IF KEY WAS < 000 307 302 JNZ
010 000 310 304 MORE
000 116 134 POINT D /(0-7, OCTAL 000 311 000 0
DIGIT) 000 312 321 POPD
000 Ly. 000 0 000 313 361 POPPSW /RESTORE
000 120 107 MOVBA /SAVE KEY CODE REGISTERS
000 Ved 171 MOVAC /GET OLD VALUE 000 314 311 RET
900 122 027 RAL /ROTATE 3 TIMES
/THE KBRD ROUTINE
DEBOUNCES KEY CLOSURES
/AND TRANSLATES KEY CODES
A-70 /FLAGS A ND REG A ARE
CHANGED
/AO-A3 = CODE; A4-A7 =
0000
000 315 333 KBRD, IN /INPUT FROM
KEYBOARD
ENCODERS
000 316 000 000
000 317 267 ORAA /SET FLAGS
000 320 372 JM / JUMP BACK IF LAST
KEY NOT RELEASED
000 321 315 KBRD
000 S22 0Qo 0
000 323 315 CALL WAIT 10 MSEC
000 324 PACH TIMOUT
000 325 000 0
000 326 333 FLAGCK, IN
000 327 000 000
000 330 267 ORAA
000 331 362 JP / JUMP BACK TO WAIT
FOR A NEW
000 332 326 FLAGCK /KEY TO BE PRESSED
000 333 000 0
000 334 315 CALL /WAIT 10 MSEC FOR
BOUNCING
000 335 rarele TIMOUT
000 336 000 0
000 337 333 IN
000 340 000 000
000 341 267 ORAA
000 342 362 JP /JUMP BACK IF NEW
KEY NOT STILL
000 343 326 FLAGCK /PRESSED (FALSE
ALARM)
000 344 000 0
000 345 346 ANI /MASK OUT ALL BUT
KEY CODE
000 346 017 O17
000 347 345 PUSHH /SAVE H & L
000 350 046 MVIH /ZERO H REG
000 351 000 000
000 352 306 ADI /ADD THE ADDRESS
OF THE BEGINNING
000 353 360 360 /OF THE TABLE TO
THE KEY CODE
000 354 157 MOVLA /
000 355 176 MOVAM /FETCH NEW VALUE
FROM TABLE
000 356 341 POPH /RESTORE H & L
000 357 311 RET
"you can use the stack as set up by the KEX (generally a good idea) or you can
put your own stack anywhere you want, just by using the LXISP instruction.
to avoid the stack area when writing your programs. Remember, too,
Remember
put the stack in an area of non-existent memory or in PROM."
that you can't
Quy DESCRIPTION
Capacitors: 100 pF
200 pF
ee
we
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Sd
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ce
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Miscellaneous: Volt-ohmeter
SPDT Microswitch
Hookup Wire
A-7l APPENDIX 8: INDEX
Base, A-2
(see also Radix)
Battery, 9-11
BCD ;
addition program, 18-72/18-75
- to-decimal decoder 7-14
- to-8-bit binary program, 18-70/18-71
(see also Binary coded decimal)
Bidirectional data bus
definition, 16-12; A-14
8080A , 16-14; A-41/A-42
1/0 port, 22-27/22-30
Binary, 7-2; A-3
code, 1-4/1-5; A-3
coding, 1-2/1-3; 7-2
signals, 14-2; A-3
Binary coded decimal (BCD)
definition, A-3
demonstration, 9-35
explanation, 12-4/12-5
Binary counter
definition, 13-2; A-3
example, 13-11
Binary counting system, 1-4
(see also Binary code)
Binary-to-BCD conversion program, 18-76/18-82
Binary-to-Octal conversion, 1-7
Biquinary counter, 13-11
Bistable element, 11-2; 15-2; A-3
(See also Flip-flop)
Bit, 1-3; A-3
Boolean algebra, 8-2/8-4; A-3
Bounce (contact), 13-38/13-40
Branch instructions, 3-9; 18-48/18-58
(see also Unconditional jump and specific instruction desired)
Breadboarding, 9-2; A-3
station outboard, 9-39/9-41; A-27
A-76
Buffer/driver, 7-13
definition, 14-20/14-21; A-3
three-state, 19-3/19-8
Buffer gate, 7-13; A-3
Bugback, 9-13 »
Bus R
definition, 16-12; 19-2
drivers (MMD-1)3} A-14; A-50/A-54
MMD-1, A-61
monitor, 17-20/17-24; 22-24/22-26; A-14
systems, 19-4/19-5
three-state, 19-2/19-3
Byte, 2-6; 18-11/18-12; A-4; A-14
Call
conditional, 18-54
unconditional, 18-50/18-51
CALL addr, 18-50/18-51
Capacitance, A-4
Capacitor
definition, A-4
symbol, 9-11
valve prefix, 9-11
Cascading, 13-3/13-4
decade counter, 13-8/13-10
demonstration, 13-32/13-37
Cathode (diode), 9-12
CC, 18-54
Central processing unit
block diagram (8080A), 18-10
definition, 16-13; A-14
Character, 2-3
detection program, 22-20/22-23
Chip identification, 10-17/10-18 >
Clear input (flip-flop)
definition, 11-5
demonstration, 11-32/11-33
general rules, 11-17/11-18
Clock
definition, 11-5; A-4
frequency determining circuits, 13-18/13-21; 13-32/13-35; 14-30/14-32; 15-20/15-21
general, 9-12
input (flip-flop), 11-5; A-4
MMD-1, 4-9; A-44/A-48
outboard description, A-27
outboard symbol, 9-12
pulse, 9-37; A-4
pulse train waveform, 11-9
Clocked logic
definition, 11-2
explanation, 11-18
CM, 18-54
A-77
CMA, 18-48
CMC, 18-48
CMP, 18-40/18-41
CNC, 18-54
CNZ, 18-54
Code conversion, 12-8; A-4
binary-to-hex, 12-3
binary-to-octal, 1-7
octal-to-ASCII, 12-7
octal-to-binary, 1-6
octal-to-hex, A-36
Communication, 1-2; A-4
Compare operation (CMP), 18-40/18-42
Complement, 7-8; 8-7; A-4
accumulator, 8-7/8-8; 18-48
carry, 18-48
(see also INVERTER)
Computer
interfacing, 16-17
program, 2-2; 5-2; A-4
(see also Digital Computer)
Conditional branch instruction, 6-7
Condition flags, 18-19/18-20 ©
Contact bounce demonstration, 13-38/13-40
Control, 16-12; A-14
lines (MMD-1), A-50
signals (8080A), A-42/A-44
Control bus
definition, 16-12; A-14
8080A, 16-14/16-16
Controllable inverter, 10-46/10-48, 14-12/14-13
Controller, 16-7; A-14
Count direction, 13-3
Counter
binary, 13-11
biquinary, 13-11
characteristics, 13-2/13-4
comparison of types, 13-4
decade (see Decade counter)
definition, 13-2; A-5
divide-by-twelve, 13-12
gated, 14-22/14-24
outboard, A-31
CP, 18-54
CPE, 18-54
CPI data, 18-41/18-42
CPO, 18-54
CPU, (see Central processing unit)
Current loop outboard, A-33
Current-sinking logic, 10-36
CZ, 18-54
A-/8
DAA, 18-36/18-38
DAD rp, 18-40 .
Data :
byte, 3-5; A-5
logger, 22-2
Data bus
monitor, 17-20/17-24
in output, A-44
Data logging, 22-2/22-3; A-14
demonstration, 22-12/22-19
Output, 22-7
program examples, 22-3/22-9
Data processor, 16-5
Data register functions (MMD-1), 4-9
Data storage demonstration, 4-22/4-23; 5-13
Data transfer instructions, 18-21/18-30
(see also specific instruction desired)
Date codes (IC), 10-17/10-18
DBIN, (see Data bus in output)
DCR, 18-39
DCX rp, 18-39/18-40
Debounce circuit, 11-6/11-9
demonstrated, 13-38/13-40 Be:
Decade counter
cascaded, 13-8/13-10
definition, 13-2; A-5
demonstration, 13-16/13-17, 13-32/13-37
example, 13-4/13-5
waveforms, 13-7/13-8
Decade sequencer, 13-27/13-29
Decimal adjusted operations, 18-36/18-38
Decode, 12-6; A-5 %
Decoder
absolute, 17-9; 17-49/17-52
outboard, A-29
output (MMD-1), 17-35/17-39
types, 12-15
2 to 4-line, 12-13/12-14; 12-27/12-28
3 to 8-line, 12-12/12-13; 12-22/12-24
4 to 16-line, 12-11/12-12; 12-25/12-26
4 to 10-line, 12-9/12-10; 12-19/12-21
(also called 1-of-10 decoder and BCD-to-decimal decoder )
Decrement
demonstration, 6-17/6-18
memory, 18-39
register, 6-7;
18-39
register pair, 18-39
Definitions
Bugbook V, A-2/A-12
Bugbook VI, A-13/A-18
Delay time (see Propagation delay time)
Delimiter, 23-32
De Morgan's Theorem, 8-6/8-7; A-6
A-79
Gate
Boolean statements for, 8-3/8-4
characteristics, 10-15/10-16
circuit, 14-20; A-7
for data control, 14-6/14-16
definition, 7-2; 14-6; 14-15; A-7
multiple signal, 14-14/14-15
A-81
Gate (continued )
pulse, 14-20; A-7
signal, 14-20; A-7
vs. switch, 14-21
symbols, 7-5/7-6
uses of, 7-4
(see also specific gate desired)
Gated
buffer, 14-20; A-7
counter, 14-22/14-24
counter demonstration, 14-26/14-32
driver, 14-21; A-7
General purpose register, 6-2; 18-8; A-7; A-15
Glitch, 13-13/13-14; A-8
Ground, 9-11
Inhibit, 14-20
(see also Disable)
Input circuits (buffered), 20-13/20-14
INPUT cycle, 17-16
Input data to accumulator (IN), 8-12; 20-15
Input-output (MMD-1)
accumulator’ (isolated), 20-2
control signals, 16-15/16-16
general, A-61/A-63
memory, 20-2
ports, 4-10
strobe pulse counting, 17-30/17-34
Input/Output (1/0) device
definition, 16-13; 16-19; A-15
instructions, 17-15/17-16; 20-15
Input-output terminals (SK-10), 9-2; 9-7
Inputs (unconnected), 10-17
Input techniques, 20-13
INR, 18-38/18-39
Instruction byte nomenclature, 3-6
Instruction code
definition, 18-11; A-15
description, 18-12
(see also Operation code)
Instruction cycle, 2-5; A-8
Instruction decoder, 18-11; A-15
Instruction register, 18-11; A-16
Instructions (general)
defined, 2-3; A-8
forms of, 2-3/2-4
multi byte, 3-2/3-4
Instructions (8080A)
common, 3-6; 5-2
complete table, 6-4; 8-11
detailed descriptions, 18-18/18-68
format, 18-18/18-19
groups of, 18-18
octal/hex, 18-83/18-88
processor instruction summary, 18-68
reference set, 18-7
summary by bytes, 18-89
(see also specific instruction desired)
INT (see interrupt request)
INTE (see Interrupt enable)
Integrated circuit (IC)
definition, 10-2; A-8
history, 10-2/10-3
Integrated circuit chip
catagories, 14-16
definition, 2-2
dimensions, 10-19/10-20
drive capability, 20-12
hints and suggestions, 10-22/10-24
manufacturers, 10-18
numbers and date codes, 10-17/10-18
pin identification, 10-4
symbol, 9-13
symbolic representation, 10-3/10-15
A-83
KEX
instructions, 17-26/17-28; 20-30/20-32
operation, A-67/A-71
program, 13-40; 13-42; A-69/A-70
A-844
Keyboard
characteristics (MMD-1), 23-39/23-41
functions (MMD-1), 4-7
input subroutine (KEX), 20-80/20-31
interfacing, 23-2/23-6
interrupt driven, 23-14/23-17
tests, 4-17/4-2]
Kilobyte, 16-13
Lamp Monitor
definition, A-8
demonstration, 9-22/9-28
outboard description, A-23
outboard symbol, 9-12
Language, 1-2; A-8
Large scale integration (LSI), 10-2; 14-16
Latch
buffer circuit, 19-17/19-18
comparisons, 11-21/11-23
definition, 11-5; A-8
demonstration, 11-34/11-36; 13-22/13-23
example, 11-6/11-9
vs. flip-flop, 11-37/11-41
outboard description, A-29
output circuits, 20-6/20-12
Latch/display
demonstration, 9-42/9-44, 11-45/11-46
description, 9-14; 11-25/11-26
outboard description, A-24/A-27
LDA addr, 18-26 .
LDAX rp, 18-28/18-29
Least significant nibble (LSN), 18-37
LED lamp monitor,
(see Lamp monitor)
Level control
demonstration, 23-42/23-45
example, 23-5/23-9
Level-triggered flip-flop, 11-19
LHLD addr, 18-26/18-27
Library submittal form, 18-94/18-95
LO address byte, 2-8; 3-5; A-8
Load instruction
accumulator direct, 18-26
accumulator indirect, 18-29
HL direct, 18-26/18-27
registers, 18-23/18-24
Logical instructions (operations), 8-2; 18-42/18-46; A-9
(see also specific instruction desired)
Logic gate, (see Gate)
Logic states
binary, 1-4
demonstration, 9-22/9-24
A-85
Logic switches
definition, A-9
demonstration, 9-30/9-32
outboard description, A-22
outboard symbol, 9-12
Loop, 3-9
demonstration, 5-12
sample program, 5-6
time delay demonstration, 6-22/6-28
time delay example, 6-11/6-13
LSI, (See Large scale integration)
LSN, (See Least significant nibble)
LXI rp, data 16, 18-23/18-24
Machine cycle
definition, 17-16; A-16
memory read/write, 21-10
Machine language (code), 2-4/2-5; 18-18; A-9
Manufacturers (IC chip), 10-18
Masking, 8-13; 18-45; A-9; A-16
demonstrated, 8-19/8-20
Medium scale integration (MSI), 10-2; 14-16
Memory
blocks (MMD-1), 4-10
definition, 2-6; 16-13; A-9; A-16
groups (microcomputer), 2-7/2-8
MMD-1, A-56/A-61
size, 2-7
Memory address, 2-7/2-8; A-9
bus, A-41
HI/LO, 2-8; 3-5
monitor functions, 4-7/4-8
Memory bytes, 3-4/3-5
Memory element, 11-2/11-3
(see also Flip-flop)
Memory 1/0
vs. accumulator I/0, 21-2/21-3
bidirectional, 22-27/22-30
circuit examples, 21-12/21-14
definition, 20-2; A-16
instructions, 21-8/21-10
program examples, 21-11; 21-14/21-20
with programmable interface, 22-37/22-38
select pulse generation, 21-3/21-6
summary of characteristics, 21-2/21-3
Microcomputer
definition, 2-2; A-9
vs. microprocessor, 16-5/16-7
typical 8080A, 16-12
(see also MMD-1)
A-86
Microprocessor chip
definition, 2-2
description, A-38/A-40, A-48/A-50
MMD-1 Microcomputer
clock specifications, 4-9
control stgnal terminals, 16-15/16-16
data register functions, 4-9
data storage demonstration, 4-22/4-23; 5-13
decoding circuit, 17-12
description, 4-2/4-10; A-37/A-71
function diagram, 4-4
input/output instructions, 17-15/17-16
input-output ports, 4-10
instruction set, 18-18/18-68
keyboard characteristics, 23-39/23-4]
keyboard debounce, 13-40
keyboard functions, 4-7
keyboard tests, 4-17/4-2]
logic gate simulation, 10-39/10-41
memory, 4-10
memory address monitor functions, 4-7/4-8
mnemonic table, 18-14/18-16
as octal sequencer, 13-41/13-42
Operations, 18-12/18-13
output example, 5-4; 5-11
pictorals, 4-5
power requirements, 4-3
power supply tests, 4-15
programming information, 18-2/18-6
program storage demonstration, 4-24/4-25
registers, 6-2; 18-8
sample programs, 5-4/5-8
single-step circuit, 11-42/11-44, 17-25/17-29
time-delay subroutine, 13-42
Mnemonics, 2-4; A-9
Modulo, 13-2; A-9
Monostable Multivibrator, 15-2/15-13; A-9
common types, 15-2
definition, 15-2
dual, 15-8
outboard, A-29
pulse width formulas, 15-5; 15-7; 15-9
pulse width measurement, 15-15/15-19
(see also Timer (555))
Most significant nibble (MSN), 18-37
Move
HL to SP, 18-64
immediate to accumulator (MVI A), 3-8; 5-2
immediate to register (MVI r), 6-6; 18-22/18-23
register data (MOV), 6-5/6-6; 18-21/18-22
MOV rl, r2, 18-21/18-22
MSI (see Medium scale integration)
MSN (see Most significant nibble)
Multi-bit logic operations, 8-4/8-6
Multi-byte instructions, 3-2/3-4; 18-19
A-8/
NAND gate
Boolean statement, 8-3
for data control, 14-10/14-11
definition, 7-8; A-9
as a latch, 11-6/11-9
pin configurations, 10-7; 10-11/10-12
truth table determination, 10-26/10-36; 10-42/10-45
Negation (see INVERTER)
Negative clock pulse, 11-18
Negative edge
definition, 11-10; 13-6; A-10
triggered flip-flop, 11-19
Nibble, 18-37; A-16
No operation (NOP), 3-7; 5-2; 18-66/18-67
NOR gate
Boolean statement, 8-4
for data control, 14-9/14-10
definition, A-10
description, 7-10/7-11
pin configurations, 10-8/10-9; 10-14
truth table determination, 10-26/10-31; 10-37/10-38; 10-42/10-45
NOT gate (See INVERTER)
NOT operation, 8-6
Numeric indicator, 11-25/11-26
latch demonstration, 13-24/13-26
(see also Seven-segment LED display)
0
Octal code, 1-5/1-7; A-10
Octal conversion
to binary, 1-6
to hex, A-36
Octal counting system, 1-6
(see also Octal code)
Octal/Hex 8080 instruction set, 18-83/18-88
Octal latch/display, 9-14
Octal sequencer, 13-41/13-42
One-bit tables, 8-2
One-shot multivibrator
(see Monostable multivibrator)
Open collector output
definition, A-16
description, 17-12
Operation
catagories (8080A), 3-2; 18-12/18-13
definition, 3-2; A-10
on digital signal, 14-3/14-5
Operation code, 3-5; A-10
ORA, 18-43
OR gate
Boolean statement, 8-3
for data control, 14-8/14-9
description, 7-9/7-10
pin configurations, 10-8
truth table determination, 10-26/10-31; 10-37/10-38
ORI, 18-44
OR- instructions
immediate, 8-9; 18-44
memory, 18-43
register, 8-9; 18-43
Oscillator output, A-48
OUT, 18-64/18-65; 20-15
(see also Output data instruction)
Outboards, 9-9; A-19/A-35
care of, 9-20
catagories of, A-19
(see also individual outboard desired)
OUTPUT cycle, 17-16 i
Output data instruction (OUT), 3-9; 5-2; 20-15
demonstration, 5-11; 6-19/6-21
example, 5-4
technique, 20-5/20-6
Output decoder (MMD-1), 17-35/17-39
Output drive capability, 20-12
(see also Fan-Out)
Output latch circuits, 20-6/20-12
EB
PCHL, 18-58
Pin identification (IC), 10-4
Polled operation, 23-9
Polling, 23-9; A-16
POP, 18-59/18-63
Positive clock pulse, 11-18
Positive edge
definition, 11-9; 13-6; A-10
triggered flip-flop, 11-19
Power bus terminals (SK-10), 9-2; 9-7
Power dissipation (TTL), 10-16
Power outboards, A-19/A-21
Power requirements
IC chips, 9-8; 10-16
MMD-1, 4-3; A-48
Power source (SK-10), 9-6/9-9
Qutboard, A-19/A-21
symbol, 9-11
A-89
Q
Quad gate, 10-3
SBB, 18-34
SBI, 18-34
Scaler, 13-2
Schematic diagram, 9-10; A-11
Schottky TTL, 10-15/10-16
Select time, 12-16
Service routine, 23-18/23-20; A-17
Set carry, 18-48
Seven-segment LED display
code, 12-5
demonstration, 9-33/9-35
outboard, 9-13
segment identification, 12-5
SHLD addr, 18-28
Simultaneous interrupts, 23-73/23-76
Single-byte instruction, 3+2; A-1]
table, 18-89
Single-line interrupt, 23-10; A-17
Single-shot multivibrator
(see Monostable multivibrator )
Single-step circuit (MMD-1), 11-42/11-44; 17-25/17-29
SK-10 socket
care of, 9-4
description, 9-2
pictorals, 9-3; 9-7
Small scale integration (SSI), 10-2; 14-16
Sof tware
definition, 16-7; A-17
for hardware substitution, 17-2/17-5
interrupts, 23-24/23-29
SPHL, 18-64
SSI (see Small scale integration)
STA addr, 18-25
Stack pointer, 18-11; A-17
Starting address, 5-3
Start-stop multivibrator
(see Monostable multivibrator )
Status information signals (MMD-1), A-54/A-56
Status strobe output, A-48
STAX rp, 18-29/18-30
STC, 18-48
Step-by-step logic
(see Clocked logic)
Store accumulator direct (STA), 3-10; 5-2
example, 5-7
Store instruction
accumulator indirect, 18-29/18-30
HL direct, 18-28
Strobe, 11-12; 14-16; A-11
STSTB
(see Status strobe output)
SUB, 18-33
A-92
Subtract instructions
immediate, 18-33/18-34
immediate/borrow, 18-34/18-36
memory, 18-33 bs
memory/borrow, 18-34
register, 18-33
register/borrow, 18-34
Subtraction example, 18-35/18-36
SUI data, 18-33/18-34
Switch
definition, 14-21; A-11
vs. gate, 14-2]
Symbols
definition, 9-10; A-11
instruction set, 18-20
tabular summary, 9-11/9-14
Sync
definition, 16-17; A-17
input (clock), A-44/A-48
output (8080A), A-43
Synchronism, 13-3
Synchronization pulses, 16-17; A-17
Synchronous
computer, 16-17; A-17
counter, 13-3
definition, 11-5; 16-17; A-17
inputs, 11-5; 16-17; A-11; A-17
operation, 16-17; A-17
Synchronous logic, 16-17; A-17
(see also Clocked logic)
Tank, A-44
Three-byte instruction, 3-2; A-11
table, 18-89
Three-state
buffer demonstration, 19-11/19-12
bus example, 19-13/19-16
bussing, 19-2/19-3
devices, 19-9; A-18
gates, 14-4
Time delay
(see Propagation delay time)
Time delay loop
definition, 7-3; A-12
demonstration, 6-22/6-28
example, 6-11/6-13; 22-5/22-6
generation methods, 22-10
MMD-1 subroutine, 13-42; 20-31/20-32
Time line, 23-24
examples, 23-25/23-27
A-93
XCHG, 18-27>
XOR (see Exclusive-OR gate)
XRA, 18-44
XRI, 18-44/18-46
XTHL, 18-64
This Bugbook on one of an expanding series of such books that will cover the field of digital
electronics from basic gates and flip-flops through microcomputers and digital telecommunications.
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BUGBOOKS
AO Slope 1s)
Blacksburg, Virginia 24060
THE BLACKSBURG GROUP
According to Business Week magazine (Technology July 6, 1976) large scale integrated circuits
or LSI “chips” are creating a second industrial revolution that will quickly involve us all. The
speed of the developments in this area is breathtaking and it becomes more and more difficult
to keep up with the rapid advances that are being made. It is also becoming difficult for new-
comers to ‘‘get on board.”
It has been our objective, as The Blacksburg Group, to develop timely and effective educa-
tional materials and aids that will permit students, engineers, scientists and others to quickly
learn how to apply new technologies to their particular needs. We are doing this through a
number of means, textbooks, short courses, monthly computer interfacing columns and
through the development of educational “hardware” or training aids.
Our group members make their home in Blacksburg, found in the Appalachian Mountains of
southwestern Virginia. While we didn’t actively start our group collaboration until the Spring of
1974, members of our group have been involved in digital electronics, minicomputers and
microcomputers for some time.
Some of our past experiences and on-going efforts include the following:
e@ The design and development of the Mark-8 computer, featured in Radio-Electronics maga-
zine in July 1974. This is generally recognized as the first widely available hobby computer.
the Micro-Designer®
|t was based upon the 8008 processor chip. Since then we have designed
Designer® (MMD-1). This last computer was also featured in
(MD-1) and the Mini-Micro
Radio-Electronics as the Dyna-micro.
e The Blacksburg Continuing Education Series™ has now expanded to over 15 titles, covering
subjects from basic electronics through microcomputers, operational amplifiers and active
filters. Text, experiments and examples have been provided in each book. We are strong
believers in the use of detailed experiments and examples to reinforce basic concepts. This
series originally started as our Bugbook series and many titles are now being translated into
Chinese, Japanese, German and Italian.
e@ We have pioneered the use of small, self-contained computers in hands-on courses aimed at
microcomputer users. Our expanding line of solderless breadboarding modules or OUT-
BOARDS® make the design and testing of circuits much easier than was possible in the past.
Our educational hardware is marketed by E & L Instruments, Inc., Derby, CT 06418, USA.
of pro-
e@ Our short course programs have been presented throughout the world. Two series
offered, one through Tychon Incorporated and the other through the Virginia
grams are
hands-on
Polytechnic Institute and State University Extension Division. Each provides
Continu-
experiences with digital electronics and microcomputer hardware and software.
ing Education Units (CEUs) are provided. Courses are presented to open groups, com-
in hands-on experiences in these
panies, schools and other groups. We are strong believers
courses, so much time is spent in laboratory sessions.
monthly column, ‘Microcomputer Interfacing’ appears in four domestic electronic
@ Our
mil-
publications as well as in four overseas periodicals, reaching about three-quarters of a
and Italian.
lion readers. The columns are currently being translated into German
in microcomputer soft-
Besides our educational activities, our members have also been involved
ware development and scientific instrument automation.
of Chemistry and
Mr. David Larsen and Dr. Peter Rony are on the faculty of the Departments
at Virginia Polytechnic Institute and State University. Mr. Jonathan Titus
Chemical Engineering
Virginia.
and Dr. Christopher Titus are with Tychon, Incorporated, all of Blacksburg,
Mr. David G. Larsen is an Instructoi in the Department
of Chemistry at Virginia Polytechnic Institute & State
University, where he teaches undergraduate and graduate
courses in analog and digital electronics. He is
co-author of the other Bugbooks and the monthly
columns on microcomputer interfacing. He is co-instructor,
along with Dr. Rony, of a series of one- to five-day
workshops on the digital and microcomputer revolution,
taught under the auspices of the Extension Division of
the University, that attract professionals from all
parts of the world. }
.
ISBN-0-89704-008-2